CN1076548A - 用pvd和cvd法形成难熔金属覆盖的低阻金属导体线与通路 - Google Patents

用pvd和cvd法形成难熔金属覆盖的低阻金属导体线与通路 Download PDF

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CN1076548A
CN1076548A CN93101333A CN93101333A CN1076548A CN 1076548 A CN1076548 A CN 1076548A CN 93101333 A CN93101333 A CN 93101333A CN 93101333 A CN93101333 A CN 93101333A CN 1076548 A CN1076548 A CN 1076548A
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alloy
refractory metal
metal
low resistivity
deposit
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CN1044649C (zh
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雷吉夫·V·乔西
杰罗姆·J·库欧莫
霍玛兹雅·M·达拉尔
路易斯·L·苏
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International Business Machines Corp
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Abstract

本发明一般涉及电的导体线与通路的制法。采 用物理汽相淀积低电阻率金属或合金之后接着化学 汽相淀积难熔金属与随后的平整化两者的结合可制 出优良的导线和通路。CVD施加难熔金属盖时，改 变SiH4与WF6之比可以控制硅掺入钨的盖层的 量。准直溅射可在介质开口产生难熔金属衬垫，适合 于作铜基金属化以及CVD钨的扩散阻挡层。

Description

本发明一般涉及电的导体线与通路的制法，以连接衬底，诸如半导体上的电路与相应的封装件，尤其还涉及采用物理汽相淀积（PVD）法淀积低阻金属和化学汽相淀积（CVD）法淀积，难熔金属的组合来填充衬底上的缝或孔的一种低成本的方法。本发明特别适用于亚微米电路的制作。
低阻金属，诸如铝和铜以及它们的二元或三元的合金已广泛用于半导体制作的细线互连。细线互连金属的曲型例子，包括AlxCuy，其中x与y之和等于1，且x与y都大于或等于0而又小于或等于1，三元合金，如Al-Pd-Cu、Al-Pd-Nb及Al-Cu-Si和其它以低阻金属为基的合金。如今要强调的是随超大规模集成（VLSI）电路制作的线条宽度的尺寸按比例缩小，已经带来包括不适当的绝缘、电迁移及平面化方向的可靠性问题。
IBM技术公开公报Ahn等人（Vol、33，No.5，Oct，1990，pp.217-218）披露了用WF6和SiH4的含氢混合物选择性淀积制造包覆以钨的铜导体与通孔。密封了的互连线，像Ahn等人做的那样，具有很高的抗电迁移能力，并且选用晶粒尺寸小的钨膜，以减小反射率，因而增强光刻设备聚焦的能力与光刻胶的解象能力。但是，采用Ahn等人描述的低温方法所形成的钨层理应是富硅（如，3-4%），而且对铜不会是一种良好的扩散阻档层，因为形成铜的硅化物将会恶化铜的电阻率。因此，在低温下用选择法难以淀积一层扩散阻挡层。况且，Ahn等人的技术依赖于环形在导线底部的形成，而通常这是由释放的湿气与WF6反应产生的，还认为环形的出现的不会是可靠的。
Dalton等人（VMIC Conference，June12-13，1990，pp.289-292）指出，含SiH4与H2还原WF6的一种热壁CVD反应，在铝或合金导体上形成选择的钨层，其结果在铝与钨和界面含有氟团，该氟团是WF6与铝的一种副产物，如反应式1所示：
WF6+2Al→2AlF3+W
氟化铝薄层会增加金属1到金属2通路的串联接触电阻。Dalton报告说，用CVD的钨密封之前，在铝的顶面先溅射TiW膜，可以消除吸附氟的问题。
Dalton披露一种形成互连线的传统方案，这里，首先在一平整的表面上淀积铝，溅射一层TiW以覆盖其上（只是与传统不同的过程），然后，用光刻胶成象和显影，接着通过反应离子刻蚀（RIE）把该铝层刻成图案。再将所得到的结构覆盖一层纯化介质，如SiO2或聚酰亚胺，随后本身也经RIE刻成图案并且金属化，实现一种多层结构。图1引自Dalton报告，并示出通过传统工艺方式生产的多层器件，在金属导线的局部的介质层中有缝，而且顶面很不平整。
采用RIE法很难实现介质的平整化。平整度部分取决于图形的密度，以及由后继金属化时涂覆问题形成的不平表面，如果将RIE技术用于聚酰亚胺，当刻蚀导线到聚酰亚胺表面时，因除去光刻胶的过程也会除去聚酰亚胺，所以，需要为以铝或铜为基的导线的顶面上除去光刻胶而设置一刻蚀阻挡层。任何含铜量高的，铝或铜的合金的RIE都极为困难。传统工艺方法的严重缺点，包括金属的RIE，由于粒子的缺陷随着几何尺寸的微细化大量的金属短路势必增多。
Brown等人的美国专利4，824，802披露一种多层VLSI金属化结构的层间介质通路或接触孔的填充方法。详细地说，一种过渡金属，诸如钨或钼，通过CVD法或是选择地淀积在绝缘层的开孔中，或是非选性地淀积在绝缘层的整个表面及开孔中，然后，将平整化保护层，诸如偶氮苯醌酚醛型清漆、聚甲基丙烯酸酯、聚酰亚胺，或其它的热塑性的材料加到过渡金属的顶面上。通过刻蚀直至带保护层的过渡金属被整平的位置，从而得到平整了的结构。Brown等人的方法避免不了侵蚀金属及与刻蚀有关的其它问题，还不能用于平整化Al-Cn或别的软合金材料，因它们的性质不同于诸如钨与钼之类的较硬金属。因此，采用Brown等人的方法，难以完全填满通路及导线。
Beyer等人的美国专利4，944，836披露一种可用在衬底上产生共平面的金属/绝缘物膜的化学-机械抛光技术。尤其是，Beyer等人预料，可将底下的绝缘层刻出图形、淀积Al-Cu膜，然后采用化学-机械抛光技术，在这里用稀硝酸氧化铝粉悬浮液来机械研磨表面，除去Al-Cu。以该抛光混合物除去Al-Cu，势必应比除去底下绝缘物有更高的速度。这样所得的结构就包含有由绝缘层平整化了的Al-Cu导线，而且为制造多层结构就方便地添加后续的多层。
Cote等人的美国专利US-4，956，313披露了一种通路填充与平整化技术，其中Al-Cu合金导线成图在衬底的第一纯化层的顶面上。这些导线又涂敷上第二纯化层，该层以掺杂的玻璃，诸如磷硅玻璃（PSG）或硼磷硅玻璃（BPSG）为好，它能与Al-Cu合金导线各外形适配，然后在第二纯化层上开出通路以露出导线，再用CVD法将钨加到第二纯化层的表面及通路中，Cote等人的报告指出，CVD钨适合于共形，又能填充通路而不会产生空隙。而后，该结构经磨料悬浮液抛光平整化。
无论Beyer等人还是Cote等人都认为对低电阻率、软金属，如Al-Cu合金等予以抛光是不实际的。这是因为在悬浮液的作用下，这些材料势必表面受擦伤、被沾污及侵蚀。况且，按照Cote等人产生的平整化结构需用多道工艺步骤，会增加成本降低生产率。
Rossnagel等人在J.Vac.Sci.Technol.2∶261（Mar/Apr.1991））披露了一种用以淀积薄膜的准直磁控溅射淀积技术，该技术与剥离刻制图形技术和孔的填充是兼容的。该技术也出现在美国专利4，824，544中，于此可参照结合。
Shiozaki等人在固态器件与材料的第19届会议文摘（Abstracts    of    The    19th    Conference    on    solid    state    Devices    and    Materials）披露采用选择的钨淀积技术，填充在高电阻率硬金属，如Mosi上面的孔，并与软金属的密封无关。
因此，本发明的一个目的是提供一种在衬底上按亚微米级形成低成本、无侵蚀、耐磨损、抗电迁移的电导体的互连电路，有高工艺成品率的方法。
本发明的另一目的是提供一种廉价地形成密封的微细导电线的技术，尤其可应用于亚微米电路的制造，而不必将导线暴露于RIE之下。
本发明的再一个目的是提供一种耐磨损，有坚固盖层能减小电迁移的低阻导线或通路。
本发明的又一个目的是提供用CVD难熔金属密封的由PVD低电阻率形成的极好互连线。
本发明的还一个目的是提供一种增进大的高宽比通路或互连线的CVD钨的粘结的方法，包括在CVD钨之前提供由难熔金属，或合金或其组合物形成的通路中的衬垫或互连线。
根据本发明，提供了一种简单而低费用可行的技术，所得的电导体无侵蚀，具有耐磨损与抗电迁移，还证实工艺成品率高。最重量要的是，这种技术，因首先淀积只在平表面上进行，而完全避免了麻烦的介质平整化工序。本技术采用普通一组或单圆片的PVD工艺过程，诸如蒸发、溅射或准直溅射，接着用共形淀积难熔金属。
上述的及其它目的，各种情况及优点参照附图从下面的本发明优选的实施例的详细描述中，将能得到更好的理解，其中：
图1是表示顶同不平的现有技术半导体衬底的剖面侧视图;
图2A到2E是说明本发明一种改变的半导体衬底的连续剖面侧视图;
图3A至3B是有器件的衬底的连续侧视剖面图，在刻制绝缘物图形之前，其上涂敷了待整平的绝缘物;
图4A到4E是说明本发明的另一种改型的半导体衬底的连续剖面侧视图;
图5A至5E是说明本发明还有一种改型的半导体衬底的连续剖面侧视图;
图6是用PVD淀积在通路中的衬垫的扫描电子显微照片（SEM）;
图7A和7B是说明本发明的再一种改型的半导体衬底的连续剖面侧视图;
图8是举例的，多层镶嵌结构，其中PVD AlxCuy合金覆盖着CVD钨的剖面图;以及
图9A和9B分别是化学-机械抛光之前与之后具有被钨覆盖的Al-Cu合金导线的结构剖面SEM的显微照片。
本发明一般涉及衬底上形成金属填充的通路及导体线的方法，而该通路及导体线包括软的低电阻率的金属，该软金属又覆盖着相当硬的难熔金属，能抗侵蚀、耐磨损以及抗电迁移，此外，该通路及导体线用涂敷在衬底上的介质层予以平整化。采用的PVD淀积技术，按图2A-E、图4A-E及图7A-B描述的工艺过程，可以创造出多种不同的新颖结构。应当理解为，这些技术与所得到的结构不应限于使用任何特定的衬底和介质盖层（例如，象图2A-E与5A-E所示的使用无机的与有机的多层组合，同样可用无机或有机绝缘材料的单层）。而且，本发明也不限于任何特殊铁金属组合;宁可说，本发明的目的是将能耐磨损、抗侵蚀及抗电迁移的难熔硬金属盖在低阻的软金属上。本发明尤其和使用铝与铜合金的电层系有关，因为已经发现采用PVD准直溅射能以可靠的大高宽比填充到亚微米通路和槽中，淀积出均匀共形的难熔金属衬垫材料涂覆层。该难熔金属衬垫在后续的过程中将用作铜的有效的扩散阻挡层。
参见图2A，首先，将衬底10涂敷一层介质，接着把介质层刻出图形。衬底10优选的是适于制造集成电路的硅、砷化镓，或其它材料。然而，该衬底10也可以是常用于封装半导体，与制造薄膜互连线的陶瓷、玻璃、或复合材料。该衬底10最好于其中形成了许多半导体器件，可包括场效应晶体管（FET）、双极晶体管、电阻，肖特基二极管，或类似器件。应该理解，图3A-B、4A-E、5A-E、7A-B、以及图8各个所示的衬底10可以有上面讨论过任何特征，再加上本技术领域公知的其它的任何特征。
图2A所示的介质复合层，分别包括顶上和底下的无机介质层11和13，可以是二氧化硅（SiO2），氮化硅（Si3N4），或类似物，该无机物层11和13两者最好用等离子增强化学汽相淀积（PECVD）法淀积，在导电的衬底10上，90乇下，首先淀积SiO2上，再制备对可动离子扩散起阻挡作用的Si3N4（0.075至0.1μm）。一较厚的有机介质层12，诸如聚酰亚胺之类，淀积在无机层11和13之间。也可以采用一种无机物介质，诸如SiO2、PSG或BPSG的，或有机物介质，诸如聚酰亚胺，并且可用众所周知的许多技术的任一种，诸如在氮化气氛中、溅射，或PECVD法生长一层单层，去替代由层11，12和13所形成的介质复合层。虽然，图2A-E和5A-E表示应用复合结构，而图3A-B、4A-E及7A-B表示运用单无机物的或介质层，但应理解，该介质层不限于本发明的实践，而且在本发明的实施中，可以采用所用的任何介质（如，无机或有机的）本身或组合。
图2A示出介质复合层中形成了的开口14，这样的开口可以是一通路或导线的槽。VLSI应用中，该衬底10或许有如图2A所示的数百到几千个开口14，最后，得到密集复杂的图形终归要在衬底上或之中互连成电路。最好采用增强反差的不刻（CEL）法，随后用多圆片装置利用CHF3和O2刻蚀槽或孔，刻蚀以适当的过腐蚀为佳，以确保该开口14有所要求的尺寸，并延伸到衬底10表面的接触点作为一通路柱塞的图形.至于导线图形，最好将介质层局部刻蚀到这样的深度，要比待采用的金属厚度大约高10%，刻蚀聚酰亚胺12时，以低温下的O2RIE为佳。应该知道，如图2A-E、4A-E、5A-E及7A-B所指的开口14成形在本领域内都是熟知的，还可以用许多不同的技术产生。
如图3A和3B所示，若开始衬底10其上有一形成的器件（与图2A所示的不带向上凸出的器件的平整的衬底10相反），制造成开口22之前，首先要将涂覆器件18的绝缘物20平整化。平整化可以用RIE、化学机械抛光、RIE和化学机械抛光的结合，或其他方法实现。
图2B-2E说明本发明的第一种改型，其中平面刻成的结构，可以是图2A所见的一个，或是图3B所见的一个，或是在涂覆的介质上形成了开口14的任何其它结构，然后，有一淀积的难熔金属层15盖在该无机介质层13以及在间隙14底部露出的衬底10上。为达到此目的，最好采用薄膜工艺技术手册（Handbook    of    Thin    Film    Technology，eds.Maissel和Glen，McGraw-Hill    Co，1983，pp1-100）所述的蒸发PVD技术。此刻采用蒸发PVD的一个重要优点在于难熔金属层15不会覆盖住介质开口14的侧壁。应该理解，PVD准直溅、类似于美国专利4，824，544叙述的方法都能用于本发明的实施，但是，与图2B所示的情况相反，准直溅射产生共形层会涂敷开口14的侧壁。使用准直溅射产生难熔衬垫将于下面详细讨论。难熔金属可以是钛（Ti）、钛合金或复合物，诸如Ti/TiN、钨（W）、钛/钨（Ti/W）合金、或铬（Cr），或钽（Ta）及其合金，或某些其它合适的材料。要是待形成的为铜基的导线或通路，那末就应使用对铜能起扩散阻挡作用的难熔金属，使得在开口14中淀积铜的后续工艺时，能防止铜扩散到衬底10中。
接着，用蒸发PVD法在难熔金属15上面淀积单一的、二元或三元的金属化层16，再说，由于采用蒸发法，开口14的侧壁不会涂敷上该金属。但是，应该理解，金属化16层也能用准直溅射施加上，这种情况下，开口14内和介质叠层的顶上，为共形的金属化涂层。最好，该金属化为AlxCuy，这里x与y的和等于1，而x与y两者都大于或等于0，且小于或等于1;可是，三元合金，如Al-Pd-Cu和多元合金，如Al-Pd-Nb-Au也都是适合的。金属化层16的本质特点在于，与难熔金属15比较，金属化层16为一种低阻率的软材料。更可取的是，表示导线图形或层间通路图形的开口14要用金属化层16填充到比导线或通路表面低100至400nm的深度。应该明白，图4A-E、5A-E和7A-B表示的金属化16层应是上述相类的东西。
图2c表示出一种难熔金属17，诸如钨、钴、镍、钼，或合金/化合物，如Ti/TiN被淀积在该结构上。难熔金属17的淀积可以是一步CVD或两步工艺过程，而图4A-E作出最好的说明，其中第一步骤包括准直溅射或类似工艺淀积一层，增进粘合的化合物如钛或氮化钛，以形成共形的复盖涂膜，而第二步骤包括淀积一钨的薄CVD层，以达到高度的共形性。CVD淀积难熔金属最好用SH4或H2还原WF6来实现。尤其好的CVD工艺过程包括SiH4还原WF6后继之以H2还原WF6。因为，在TiN层的顶上，用SiH4还原WF6的CVD钨，生长平整，但用H2还原则不然。难熔金属17为底下开口14中的低电阻率软金属化层17提供耐磨损、抗侵蚀，以及抗电迁移的涂层。采用SiH4还原WF6做CVD特别优越，SiH4与WF6的比率可以改变，能把不同的硅量混入到钨中以达到有益的特性。举例来说，填充介质中的开口14时，以0.5SiH4比WF6的比率淀积难熔金属17应是更可取的，因为这么做会得到低阻难熔金属;但是，用于介质顶面的淀积，则按2.0SiH4对WF6的比率，因为这样得到的会混入更多的硅使难熔金属更耐磨损。利用上述的CVD技术，可用掺硅的钨作为抗磨损的涂层或抛光阻挡物（例如，化学-机械抛光中更能经受用硝酸铁的氧化铝粉悬浮液）。由于通过蒸发施加的金属化层16不会覆盖着开口14的侧壁，而CVD施加的难熔金属17却产生环绕金属化层16的锥状侧壁，且该金属化层16完全被密封在难熔金属17与底下难熔金属15之中。
图2D和2E表示CVD施加难熔金属17产生一种结构后被平整化了的结构，其中的两部分导电通路或导线包括中心的低阻软金属化层16及密封金属化层16的耐磨损硬难熔金属17，其顶面与衬底10上介质复合层的顶面一般齐。用悬浮液，诸如稀硝酸铁的氧化铝粉液化学-机械抛光，或在含SF6或者氯基的化学物中RIE，可以在一步或两步工序中完成平整化。如果采用化学-机械抛光法，则要选择能除去该叠层上不同金属层的悬浮液。举个例，用氧化铝粉的稀硝酸铁悬浮液能除去铜顶面上的Ti/TiN/W，然后。换用不含氧化铝粉的悬浮液就能除去留下的铜。
RIE除去难熔金属层17之后，结合用化学-机械抛光留下物金属化层16，预料也能留下无机或有机层13顶面上的难熔金属17，设想一种特定的平整化过程，包括或者用化学-机械抛光或者用SF6或Cl2基的化学物的RIE除去钨的难熔金属层17，直至如图2D所示的Al-Cu合金金属化层16的表面，然后，利用钨作掩模，刻蚀Al-Cu CVD层直到无机层13的表面，最后，介质表面留下的钨17或经抛光、湿法腐蚀或在Cl2中RIE腐蚀，就得到图2E所见的结构。
图4A到4E表示出本发明的另一种改型，与上面相同的类似构件在各图中均标以相同的标号。如图4A所示，铜金属化层16淀积在衬底上形成的无机或有机介质15产生的开口14中。图4A所示结构与图2B所示结构的主要区别在于，淀积铜金属化之前，准直溅射淀积一薄难金属金属层24，诸如钛、氮化钛（TiN）、钨、钽，或合金及其化合物盖在无机或者有机介质15的表面及开口14通路的内侧。
如上所述，对准直溅射，Rossnagel等的美国专利4，824，544已作概述，其中还讨论过剥离操作过程。本发明已经发现，采用准直溅射，在高压下散射占优势，相反在低压下定向性淀积占优势，可容许在大高宽比的亚微米级槽或通路内形成共形涂层（例如，侧壁和底面都被涂敷上）。高宽比，一般是指槽或通路的高度对沟槽的宽度或通路的直径之比。对高宽比大于2的槽或通路，通常认为具有大的高宽比。就准直溅射来说，高于1毫乇（mTorr）气压，散射往往占优势（最好在3毫乇（3mTorr）附近），而低于1毫乇（1mTorr），则定向淀积占优势。结合图5A-E和图6，下面将更详细地陈述准直溅射。
当用铜基合金金属化层16时，如图4A所示，用一难熔金属层24完全覆盖开口14的底面与侧壁就尤其重要，因为后续的高温处理会使铜扩散到衬底10中，如果不设置扩散阻挡层就会破坏器件。无论用蒸发PVD、准直溅射还是其它技术都可以淀积铜金属化层16。当要填充的是亚微米大高宽比的孔时，现有的CVD技术对用铝与铜基合金来填充这样的孔已经失败;因此，最好的填充方法是通过PVD技术。
淀积金属化层16之后，再把钛、Ti/TiN，钽或铬的薄层26施加在该铜金属化层16的表面，以增进粘结力。然后，通过CVD，用SiH4或H2还原WF6淀积难熔金属，如钨，产生图4B所示的结构，正如上面已解释的，CVD时可利用改变SiH4与WF6的比，以利于制成较硬，更耐磨损，靠近介质15的顶面的含硅钨层。界面上的薄层26应这样选择，即不会浸蚀底下的铜金属化层16。
图4c指明，首先经抛光或经RIE将钨平整化，而图4d表明，经湿法腐蚀，有选择地除去铜。如果要形成的是铜或铜合金线，以过氧化氢（H2O2）和四氧化氢（H2O4）为基的湿法腐蚀液来平整铜是有利的。室温下，这类溶液决不会腐蚀钨或介质，但会腐蚀掉位于介质上的所有的铜，因为没有保护铜不受湿法腐蚀液腐蚀（例如，在室温下，H2O2几乎有无限的选择性。图4e表明，湿法腐蚀后，该钨17可以用RIE、抛光或其它技术有选择地除去。除去难熔金属17钨的可取方法，是用氧化铝粉的硝酸铁悬浮液之类化学-机械抛光介质15表面之上的凸出物，因为钨是一种很硬的材料，经受化学-机械抛光时，不会受擦伤或侵蚀。上面详述的决不是三步工序的方法，更可取的是用化学-机械抛光一步工序，以除去钨的难熔金属17、薄层26的粘结增进层，以及位于绝缘物15表面上的铜金属化层16。
图5A至图5E表示本发明还有一种改型，其中同样的标号指同样的结构。图5A表明，在用准直溅射，如Rossnagel等人在J.Vac.Sci.Technol.2，261（mar/Apr.1991）和美国专利4，824，544合并参照的准直溅射法，以全部或局部的共形方式金属化之前，在开口14内淀积一层难熔金属衬垫28。准直溅射时，在气压大于0.5毫乇（mTorr）下，难熔金属原子穿过深度对面积的高宽比大于1的蜂窝状结构。表1给出已用于衬垫淀积的条件。
表1
准直淀积衬垫
高宽比    复盖高差厚度    底部/顶面(%)
侧壁/顶面(%)
1:1    38    60
1:2    39    70
1:4    42    100
非准直
0    10    12
在表1所给出的研究中，压力从0.5毫乇mT变到15毫乇mT，而功率从0.5千瓦变到12千瓦。表1清楚地指出，不用准直溅射时的恶劣复盖高差厚度比。采用较高的气压（如，3毫乇）而准直器的高宽比至小1∶1用Ti/TiN或Ti/W双层来涂敷高宽比大于7至8的通路或接触孔，所得到的复盖高差厚度比，对底面大于40%，对侧壁大于30%，对本技术领域来说，这是很大进步，因此容许半导体制造者在大高宽比的通路或槽中制备共形层，将增强CVD钨的粘结力。并且，正如下面将详加陈述的，制成的TiN或其它合适材料的共形层将给铜基合金提供一种有效的扩散阻挡层。如上所述，为了充份地覆盖槽或通路的侧壁及底部，应采用散射淀积占优势的气压（如，高于1毫乇），而不应采用定向淀积居优势的低气压。
如上所述，图6呈现的是一幅PVD准直溅射在通路中产生的一个难熔金属衬垫的SEM显微照片。图6表明，能够实现通路底部及侧壁的完全覆盖，用N2等离子，与氩一起在钛靶下，就地淀积TiN。该衬垫能改善粘结力及防止CVD钨对底下衬底的任何浸蚀。当准直器的高宽比增大时，衬垫的共形度也增加了。
如把铜导线或通路用之于该结构，就需要坚固的衬垫用作扩散阻挡层。低压准直溅射的难熔金属衬垫（如，Ta、Ti/TiN，或Ti/W等）会在介质中开口14的侧壁上造成一种多孔的结构。为防止这种多孔结构，而在侧壁上制出致密的结构，要采取两步准直工序。详细说，第一步骤，用低于0.8毫乇的气压淀积一薄的衬垫层，达到底高大于60%的覆盖范围，而第二步骤，原处不动，将气压增至3到4毫乇，使用相同的准直器，在侧壁上得到一种致密的微结构。本发明之前，没有一种方法能够在很大的高宽比的亚微米孔中，尤其在低温下，形成一种衬垫。这些结果，类似于用Ti/W和Ti/TiN双层衬垫做CVD难熔金属17或低阻软金属的扩散阻挡层。
图5B-E表示出本发明另一种改型中，实施类似于图2B-E和图4A-E表示的那些工序。与图4A相似，图5B示明有一种粘结增进剂层26，诸如Ti、Cr、Ta、Ti/N之类，用PVD蒸发淀积，盖在难熔金属衬底顶上与间隙14的底部。与图2B相似，图5B示明，通过PVD蒸发技术将Al-Cu合金或别的金属化层16淀积到介质层表面以下100至400nm的水平位置。图5C-E分别表示出淀积共形层钨或其他难熔材料，以覆盖低阻金属化层16，通过RIE或抛光平整化钨，等等之类，而平整化该结构可用H2O2湿法腐蚀铝-铜合金之后，接着化学-机械抛光钨的两步工序如图4c和4d所示，或者通过RIE或化学-机械抛光的一步工序简单地加以平整化。关于一步工序化学-机械抛光，悬浮液可采用与用于抛光钨相同的悬浮液。类似图2E所示结构，图5E所示的结构有密封着低阻金属化层16的CVD难熔金属17，还有一锥形的难熔金属17区。
图7A和7B表示本发明的再一种改型，其中相同的标号相同的构件。正如图7A所示，不论共形的，以难熔金属为好的衬垫/扩散阻挡层28，还是共形的AlxCuy或其它合适的材料的低阻合金或金属化层16都用PVD准直溅射淀积在衬底10的无机或有机介质的开口中，接着，CVD淀积难熔金属17覆盖层，诸如钨、钛、钽、之类包覆该结构。图7B示出经RIE，化学-机械抛光或其它技术使之平整化了的结构。将图7B的结构与图5E的结构予以对比，可以看出，通路或导线的形状是很不同的。虽然，两种结构都包含一个由难熔金属17包覆的低阻金属层16，但这两种金属化很可能适用于不同的环境。
已经用按上面陈述的技术制造的难熔金属包覆的导线进行实验检测，实验中，该导线长度从13.45cm变到50cm，芯片面积接近1.6mm2。金属间距从1μm变到2μm。要填充的孔的高宽比为2至8，而导线为2到4。
表2
抛去后，钨覆盖的低电阻率金属导线的电阻a
（A）采用蒸发形成的b
a）全部实验中，导线的长度从13.5cm变到50cm，芯片面积接近1.6mm2。金属间距从1μm变到2μm。填充孔的高宽比为2至8，以及对导线为2至4。
b）蒸发实验中，用准直溅射淀积Ti/TiN双层。
c）准直高宽比为1∶1。
d）溅射的气压范围在0.5至0.8毫乇间。
表2的结果表明，新技术加工的成品率很高，并且导线电阻不因有钨的包覆而变化较大。某些上面的数据表明，Al-Cu合金下面有钛时，电阻增大了，这是由于界面处形成TiAl3的缘故。还发现，在钛与铝-铜层之间设置一层钛合金或化合物（例如，TiN）可以防止形成TiAl3，因而仍能保持电阻较小。表2末尾的项目表明，如果采用非准直溅射法，即该种溅射应在低气压（例如，低于1毫乇）下进行，也就是定向溅射占了优势。
可以预料，在化学-机械抛光之后，对难熔金属覆盖层施行RIE，用H2O2，或H2O4作湿法腐蚀，把该覆盖层的厚度降至最起码的层厚限度。一层厚的难熔金属会增加不希望有的电容。之所以考虑用后抛光湿法腐蚀或RIE过程，使半导体设计者有可能用厚的难熔金属及为其底下的低阻Al-Cu导线或通孔在化学-机械抛光时提供最大的保护，还能随后除去任何过剩的难熔金属，实现难熔金属覆盖很薄的一种结构，举例说，可敷设一层500-600nm厚的难熔金属，用双抵挡抛光损伤，而后，通过湿法腐蚀或RIE，可以再把难熔金属层降至50nm的层厚。
图8显示出一多层半导体器件的实例，该器件包括一几乎与绝缘层顶面齐平的有钨覆盖的AlxCuy合金导线的顶面。如上面详细陈述的那样，CVD钨的通路或槽，最好包含一准直溅射以增进粘结力的TiN衬垫。在本发明的实际范围内，还可制造出许多其它半导体器件。
图9A和9B是一种半导体器件的剖面SEM显微照片。图9A显示了由SiO2之间和顶部以Al-Cu合金隔开，从硅表面向上伸出的SiO2部分。而Al-Cu合金之间及顶上为CVD钨层。图9A是表示抛光前，有盖层导线的一种结构。图9B则显示化学-机械抛光除去SiO2伸出部分顶面上的钨与Al-Cu合金后的多层结构剖面的SEM显微照片。
虽然本发明是用最佳实施例来描述，但本领域的技术人员均应认识到，后附的权利要求书的精神与范围内的修改都可实施本发明。

Claims (33)

1、一种器件，包括：
一衬底；
一位于所述衬底上的介质层；其特征在于，
金属化位于所述介质的开口中，从与靠近所述衬底的所述介质层表面相平的表面伸出，所述金属化由难熔金属或合金密封的低电阻率金属或合金组成，所述低电阻率金属或合金填充所述开口的底部且从靠近与所述介质层的所述表面相平的表面，所述开口的相对的两侧壁向上伸延并限定一覆盖区，而所述的难熔金属或合金就位于所述底部之上以及向上伸出的所述低电阻率金属或合金的侧部之间所述覆盖区内，所述难熔金属或合金具有与所述介质层相平的表面。
2、一种按照权利要求1的器件，其特征在于，所述难熔金属或合金选自包括钛、钨、钽及铬、及其合金、导电氧化物、氮化物和硅化物组成的组。
3、一种按照权利要求1的器件，其特征在于，所述低电阻率金属或合金是铝或铜的二元或三元合金。
4、一种按照权利要求1的器件，其特征在于，所述低电阻率金属是一种通式为AlxCuy的铝和铜的合金，其中x与y之和等于1。且x与y两者都大于或等于0。
5、一种按照权利要求1的器件，其特征在于，所述难熔金属或合金具有不同的或渐变的组分的掺硅量;在接近所述金属化表面部位的掺硅量比紧靠衬底部位的高。
6、一种按照权利要求1的器件，其特征在于，金属化完全穿过所述介质层并与所述衬底接触。
7、一种按照权利要求1的器件，其特征在于，难熔金属或合金衬垫位于所述介质层与所述低电阻率金属或合金之间的所述开口中。
8、一种器件，包括：
一衬底;
一位于所述衬底上的介质层;其特征在于，
金属化位于所述介质的开口中，从与靠近所述衬底的所述介质层表面相平的表面伸出，所述金属化由位于所述开口内侧表面的难熔金属或合金衬垫与位于所述用难熔金属或合金盖层覆盖的衬垫上的低电阻率金属或合金组成，其中，所述衬垫的难熔金属或合金不同于所述盖层的难熔金属或合金。
9、一种按照权利要求8的器件，其特征在于，所述盖层与所述衬垫的所述难熔金属选自由钛、钨、钽、铬以及其合金、导电氧化物、氮化物及硅化物组成的组中。
10、一种按照权利要求8的器件，其特征在于，所述低电阻率金属或合金为二元或三元的铝或铜的合金。
11、一种按照权利要求10的器件，其特征在于，所述低电阻率金属或合金是一种通式为AlxCuy的铝与铜的合金，其中x与y之和等于1。且x与y两者都大于或等于0。
12、一种按照权利要求8的器件，其特征在于，导电的粘结层位于至少的一部分所述低电阻率金属或合金与所述难熔金属合金之间。
13、一种按照权利要求12的器件，其特征在于，所述粘结层选自包括钛、钨、铬、钽以及其合金的组。
14、一种按照权利要求13的器件，其特征在于，所述粘结层为钛-钛氮合金或化合物。
15、一种按照权利要求8的器件，其特征在于，所述难熔金属或合金具有不同的或渐变的组分的掺硅量;在接近所述金属化表面部位的掺硅量比紧靠衬底部位的高。
16、一种按照权利要求8的器件，其特征在于，所述金属化完全穿过所述介质层并与所述衬底接触。
17、一种在大高宽比的亚微米孔及线路中产生衬垫的方法，其特征在于，通过准直器把难熔金属或合金在散射淀积占优势的气压下溅射到介质中的大高宽比的亚微米孔或线路中的步骤，直至衬垫厚度足以增进按着要淀积于所述衬垫上的化学汽相淀积的金属的粘结。
18、一种按照权利要求17的方法，其特征在于，所述孔或线路的高宽比大于2∶1，而所述准直器有大于1∶1的高度比，及所述气压大于1毫乇。
19、一种大的高宽比的亚微米孔与线路中形成衬垫的方法，其特征在于其步骤包括：
通过准直器把难熔金属或合金在定向淀积占优势的气压下溅射到介质中的大高宽比的亚微米孔或线路中，以在所述高宽比的亚微米孔或线路中产生第一层;以及
通过准直器把难熔金属或合金在散射淀积占优势下的气压下溅射到所述介质中的所述大高宽比的亚微米孔或线路中盖在所述第一层上。
20、一种按照权利要求19的方法，其特征在于，同样的准直器用于两个溅射步骤，所述的第一溅射步骤在气压低于1毫乇下进行，而所述第二溅射步骤在气压高于1毫乇下进行。
21、一种按照权利要求19的方法，其特征在于，所述第二溅射步骤所溅射的难熔金属选来用以阻挡铜及其合金的扩散。
22、一种在衬底上产生金属化线和通路的方法，其特征在于，其步骤包括：
产生一位于衬底上介质中的开口，所述开口有顶部及底部;
淀积第一难熔金属或合金或化合物于所述介质的顶面和所述开口的底面;
淀积低电阻率金属或合金，盖在所述介质的所述顶面与所述开口所述底面上的所述难熔金属上，直至-低于所述开口的所述顶部位置;
淀积第二难熔金属或合金，盖在所述介质的所述顶面与所述开口所述底面上的所述难熔金属上的所述低电阻金属或合金上;以及，
除去所述第一难熔金属或合金或化合物、所述低电阻率金属或合金，以及所有高于所述介质的所述顶部位置的所述第二难熔金属或合金，从而，产生一种平面结构，该结构包括有以所述介质平整化了的难熔金属或合金覆盖的低电阻率金属或合金的金属化部位。
23、一种按照权利要求22的方法，其特征在于，所述淀积所述第一难熔金属或合金或化合物的步骤是用准直溅射实现的，而衬垫则是与所有的所述开口的内侧表面和所述介质的所述顶面共形产生。
24、一种按照权利要求23的方法，其特征在于，准直溅射是由以下各步骤进行的：
在定向淀积占优势的第一气压下，通过准直器溅射所述难熔金属、合金或化合物到所述开口中的第一薄层;以及
在散射淀积占优势的第二气压下，通过准直器将所述难熔金属、合金或化合物的第二薄层溅射到所述开口中，盖在所述第一薄层上。
25、一种按照权利要求24的方法，其特征在于，进行所述第一溅射步骤的所述第一气压低于1毫乇，而进行所述第二溅射步骤的第二气压高于1毫乇。
26、一种按照权利要求22的方法，其特征在于，淀积所述低电阻率金属或合金的所述步骤采用物理汽相淀积法实现，而淀积所述第二难熔金属或合金的所述步骤则采用化学汽相淀积法实现。
27、一种按照权利要求22的方法，其特征在于，淀积所述第一难熔金属或合金的所述步骤是采用蒸发法实现，因此，所述难熔金属仅涂敷所述开口的所述底部，但不涂敷所述开口的侧壁。
28、一种按照权利要求22的方法，其特征在于，淀积所述第二难熔金属或合金的所述步骤是采用SiH4还原WF6的化学汽相淀积钨的方法实现。
29、一种按照权利要求22的方法，其特征在于，淀积粘结增进层的步骤是在淀积所述第一难熔金属、合金或化合物之后，而在淀积所述低电阻率金属或合金之前进行。
30、一种按照权利要求22的方法，其特征在于，除去所述第一难熔金属或化合物、所述低电阻率金属或合金以及所述第二难熔金属或合金的所述步骤包括反应离子腐蚀所述介质顶面上材料的步骤。
31、一种按照权利要求22的方法，其特征在于，除去所述第一难熔金属或化合物、所述低电阻率金属或合金以及所述第二难熔金属或合金的所述步骤包括化学-机械抛光所述介质顶面上材料的步骤。
32、一种按照权利要求22的方法，其特征在于，除去所述第一难熔金属或化合物、所述低电阻率金属或合金以及所述第二难熔金属或合金的所述步骤包括反应离子腐蚀和化学-机械抛光所述介质顶面上材料的两个步骤。
33、一种按照权利要求22的方法，其特征在于，除去所述第一难熔金属或化合物、所述低电阻率金属或合金以及所述第二难熔金属或合金的所述步骤包括用过氧化氢或四氧化氢的湿法腐蚀的步骤。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456617A (zh) * 2010-10-27 2012-05-16 国际商业机器公司 形成自对准局部互连的方法和由此形成的结构

Families Citing this family (328)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
EP0558304B1 (en) * 1992-02-28 2000-01-19 STMicroelectronics, Inc. Method of forming submicron contacts
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5561082A (en) * 1992-07-31 1996-10-01 Kabushiki Kaisha Toshiba Method for forming an electrode and/or wiring layer by reducing copper oxide or silver oxide
US5596172A (en) * 1993-05-07 1997-01-21 Motorola, Inc. Planar encapsulation process
US5412250A (en) * 1993-09-24 1995-05-02 Vlsi Technology, Inc. Barrier enhancement at the salicide layer
JP3297220B2 (ja) * 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
JP2699839B2 (ja) * 1993-12-03 1998-01-19 日本電気株式会社 半導体装置の製造方法
KR0179677B1 (ko) * 1993-12-28 1999-04-15 사토 후미오 반도체장치 및 그 제조방법
US5430328A (en) * 1994-05-31 1995-07-04 United Microelectronics Corporation Process for self-align contact
US5472913A (en) * 1994-08-05 1995-12-05 Texas Instruments Incorporated Method of fabricating porous dielectric material with a passivation layer for electronics applications
EP0697730B1 (en) * 1994-08-05 1999-11-24 International Business Machines Corporation Method of forming an Al-Ge alloy with WGe polishing stop
US5686356A (en) 1994-09-30 1997-11-11 Texas Instruments Incorporated Conductor reticulation for improved device planarity
KR0171069B1 (ko) * 1994-10-27 1999-03-30 문정환 반도체 장치의 접촉부 형성방법
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
EP0792515A1 (en) * 1994-11-18 1997-09-03 Advanced Micro Devices, Inc. Method of making a chemical-mechanical polishing slurry and the polishing slurry
US5580823A (en) * 1994-12-15 1996-12-03 Motorola, Inc. Process for fabricating a collimated metal layer and contact structure in a semiconductor device
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
EP1098366A1 (en) * 1994-12-29 2001-05-09 STMicroelectronics, Inc. Semiconductor connection structure and method
DE69418206T2 (de) * 1994-12-30 1999-08-19 Co.Ri.M.Me. Verfahren zur Spannungsschwelleextraktierung und Schaltung nach dem Verfahren
US6285082B1 (en) 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
US5920296A (en) * 1995-02-01 1999-07-06 Pixel International Flat screen having individually dipole-protected microdots
US5545592A (en) * 1995-02-24 1996-08-13 Advanced Micro Devices, Inc. Nitrogen treatment for metal-silicide contact
TW290731B (zh) * 1995-03-30 1996-11-11 Siemens Ag
US6348708B1 (en) * 1995-04-10 2002-02-19 Lg Semicon Co., Ltd. Semiconductor device utilizing a rugged tungsten film
TW298674B (zh) * 1995-07-07 1997-02-21 At & T Corp
US5747879A (en) * 1995-09-29 1998-05-05 Intel Corporation Interface between titanium and aluminum-alloy in metal stack for integrated circuit
JPH11511593A (ja) * 1995-09-29 1999-10-05 インテル・コーポレーション 専用チャンバによる２層のチタン薄層を有する集積回路用金属スタック
US5573633A (en) * 1995-11-14 1996-11-12 International Business Machines Corporation Method of chemically mechanically polishing an electronic component
KR0175410B1 (ko) * 1995-11-21 1999-02-01 김광호 액정 표시 장치용 박막 트랜지스터 기판 및 그 제조 방법
US6726776B1 (en) 1995-11-21 2004-04-27 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
JPH09148431A (ja) * 1995-11-21 1997-06-06 Nec Corp 半導体装置の製造方法
US6077781A (en) * 1995-11-21 2000-06-20 Applied Materials, Inc. Single step process for blanket-selective CVD aluminum deposition
US6066358A (en) * 1995-11-21 2000-05-23 Applied Materials, Inc. Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
US5877087A (en) 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US5776836A (en) * 1996-02-29 1998-07-07 Micron Technology, Inc. Self aligned method to define features smaller than the resolution limit of a photolithography system
US5950099A (en) * 1996-04-09 1999-09-07 Kabushiki Kaisha Toshiba Method of forming an interconnect
US5654234A (en) * 1996-04-29 1997-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a void-free tungsten-plug contact in the presence of a contact opening overhang
US5756396A (en) * 1996-05-06 1998-05-26 Taiwan Semiconductor Manufacturing Company Ltd Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
US5993686A (en) * 1996-06-06 1999-11-30 Cabot Corporation Fluoride additive containing chemical mechanical polishing slurry and method for use of same
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
JPH1064902A (ja) * 1996-07-12 1998-03-06 Applied Materials Inc アルミニウム材料の成膜方法及び成膜装置
US6077768A (en) * 1996-07-19 2000-06-20 Motorola, Inc. Process for fabricating a multilevel interconnect
US5783485A (en) * 1996-07-19 1998-07-21 Motorola, Inc. Process for fabricating a metallized interconnect
US6001420A (en) * 1996-09-23 1999-12-14 Applied Materials, Inc. Semi-selective chemical vapor deposition
US5965459A (en) * 1996-10-11 1999-10-12 International Business Machines Corporation Method for removing crevices induced by chemical-mechanical polishing
US6020263A (en) * 1996-10-31 2000-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of recovering alignment marks after chemical mechanical polishing of tungsten
US5849367A (en) * 1996-12-11 1998-12-15 Texas Instruments Incorporated Elemental titanium-free liner and fabrication process for inter-metal connections
AU5411498A (en) * 1996-12-12 1998-07-03 Asahi Kasei Kogyo Kabushiki Kaisha Method of manufacturing semiconductor device
US6110828A (en) * 1996-12-30 2000-08-29 Applied Materials, Inc. In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
JPH10209279A (ja) * 1997-01-27 1998-08-07 Matsushita Electron Corp 金属プラグの形成方法
US6139697A (en) * 1997-01-31 2000-10-31 Applied Materials, Inc. Low temperature integrated via and trench fill process and apparatus
US6268661B1 (en) * 1999-08-31 2001-07-31 Nec Corporation Semiconductor device and method of its fabrication
US5916855A (en) * 1997-03-26 1999-06-29 Advanced Micro Devices, Inc. Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films
US6139905A (en) * 1997-04-11 2000-10-31 Applied Materials, Inc. Integrated CVD/PVD Al planarization using ultra-thin nucleation layers
US6080665A (en) * 1997-04-11 2000-06-27 Applied Materials, Inc. Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum
JP3111924B2 (ja) * 1997-04-11 2000-11-27 日本電気株式会社 半導体装置の製造方法
US5981374A (en) * 1997-04-29 1999-11-09 International Business Machines Corporation Sub-half-micron multi-level interconnection structure and process thereof
US6849557B1 (en) * 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
US6149974A (en) * 1997-05-05 2000-11-21 Applied Materials, Inc. Method for elimination of TEOS/ozone silicon oxide surface sensitivity
US6605197B1 (en) 1997-05-13 2003-08-12 Applied Materials, Inc. Method of sputtering copper to fill trenches and vias
US6130161A (en) 1997-05-30 2000-10-10 International Business Machines Corporation Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
US6069068A (en) * 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6240199B1 (en) 1997-07-24 2001-05-29 Agere Systems Guardian Corp. Electronic apparatus having improved scratch and mechanical resistance
US5989623A (en) 1997-08-19 1999-11-23 Applied Materials, Inc. Dual damascene metallization
US6080655A (en) 1997-08-21 2000-06-27 Micron Technology, Inc. Method for fabricating conductive components in microelectronic devices and substrate structures thereof
US6096576A (en) 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US5994775A (en) * 1997-09-17 1999-11-30 Lsi Logic Corporation Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
US5990011A (en) * 1997-09-18 1999-11-23 Micron Technology, Inc. Titanium aluminum alloy wetting layer for improved aluminum filling of damescene trenches
JP3545177B2 (ja) * 1997-09-18 2004-07-21 株式会社荏原製作所 多層埋め込みＣｕ配線形成方法
SG70654A1 (en) * 1997-09-30 2000-02-22 Ibm Copper stud structure with refractory metal liner
US6133139A (en) * 1997-10-08 2000-10-17 International Business Machines Corporation Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
US6060388A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Conductors for microelectronic circuits and method of manufacture
EP1034566A1 (en) 1997-11-26 2000-09-13 Applied Materials, Inc. Damage-free sculptured coating deposition
US7253109B2 (en) 1997-11-26 2007-08-07 Applied Materials, Inc. Method of depositing a tantalum nitride/tantalum diffusion barrier layer system
TW374946B (en) * 1997-12-03 1999-11-21 United Microelectronics Corp Definition of structure of dielectric layer patterns and the manufacturing method
US6129613A (en) * 1998-01-30 2000-10-10 Philips Electronics North America Corp. Semiconductor manufacturing apparatus and method for measuring in-situ pressure across a wafer
US6424040B1 (en) * 1998-02-04 2002-07-23 Texas Instruments Incorporated Integration of fluorinated dielectrics in multi-level metallizations
KR100275728B1 (ko) 1998-02-24 2001-01-15 윤종용 반도체장치의 장벽 금속막의 제조방법 및 이를 이용한 반도체장치의 금속배선막의 제조방법
US6287436B1 (en) 1998-02-27 2001-09-11 Innovent, Inc. Brazed honeycomb collimator
US6211073B1 (en) 1998-02-27 2001-04-03 Micron Technology, Inc. Methods for making copper and other metal interconnections in integrated circuits
US6281121B1 (en) * 1998-03-06 2001-08-28 Advanced Micro Devices, Inc. Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal
JP3116897B2 (ja) * 1998-03-18 2000-12-11 日本電気株式会社 微細配線形成方法
US6455937B1 (en) * 1998-03-20 2002-09-24 James A. Cunningham Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects
US6303881B1 (en) 1998-03-20 2001-10-16 Viasystems, Inc. Via connector and method of making same
US6598291B2 (en) 1998-03-20 2003-07-29 Viasystems, Inc. Via connector and method of making same
US6140236A (en) * 1998-04-21 2000-10-31 Kabushiki Kaisha Toshiba High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring
US6218306B1 (en) 1998-04-22 2001-04-17 Applied Materials, Inc. Method of chemical mechanical polishing a metal layer
US6111301A (en) * 1998-04-24 2000-08-29 International Business Machines Corporation Interconnection with integrated corrosion stop
US6022800A (en) * 1998-04-29 2000-02-08 Worldwide Semiconductor Manufacturing Corporation Method of forming barrier layer for tungsten plugs in interlayer dielectrics
US6015749A (en) * 1998-05-04 2000-01-18 Taiwan Semiconductor Manufacturing Company Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure
US6218288B1 (en) 1998-05-11 2001-04-17 Micron Technology, Inc. Multiple step methods for forming conformal layers
US6127276A (en) * 1998-06-02 2000-10-03 United Microelectronics Corp Method of formation for a via opening
US6153521A (en) * 1998-06-04 2000-11-28 Advanced Micro Devices, Inc. Metallized interconnection structure and method of making the same
US6056869A (en) * 1998-06-04 2000-05-02 International Business Machines Corporation Wafer edge deplater for chemical mechanical polishing of substrates
JPH11354637A (ja) * 1998-06-11 1999-12-24 Oki Electric Ind Co Ltd 配線の接続構造及び配線の接続部の形成方法
US6211087B1 (en) * 1998-06-29 2001-04-03 Vlsi Technology, Inc. Chemical wet etch removal of underlayer material after performing chemical mechanical polishing on a primary layer
US6391771B1 (en) * 1998-07-23 2002-05-21 Applied Materials, Inc. Integrated circuit interconnect lines having sidewall layers
US6303986B1 (en) 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
US6287977B1 (en) * 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6284656B1 (en) 1998-08-04 2001-09-04 Micron Technology, Inc. Copper metallurgy in integrated circuits
US6060383A (en) * 1998-08-10 2000-05-09 Nogami; Takeshi Method for making multilayered coaxial interconnect structure
TW436366B (en) * 1998-08-21 2001-05-28 United Microelectronics Corp Method of fabricating a plug
US6048787A (en) * 1998-09-08 2000-04-11 Winbond Electronics Corp. Borderless contacts for dual-damascene interconnect process
US6288442B1 (en) 1998-09-10 2001-09-11 Micron Technology, Inc. Integrated circuit with oxidation-resistant polymeric layer
US6150269A (en) * 1998-09-11 2000-11-21 Chartered Semiconductor Manufacturing Company, Ltd. Copper interconnect patterning
US6180506B1 (en) 1998-09-14 2001-01-30 International Business Machines Corporation Upper redundant layer for damascene metallization
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6057230A (en) * 1998-09-17 2000-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dry etching procedure and recipe for patterning of thin film copper layers
US6245668B1 (en) * 1998-09-18 2001-06-12 International Business Machines Corporation Sputtered tungsten diffusion barrier for improved interconnect robustness
US6221775B1 (en) * 1998-09-24 2001-04-24 International Business Machines Corp. Combined chemical mechanical polishing and reactive ion etching process
JP3169907B2 (ja) * 1998-09-25 2001-05-28 日本電気株式会社 多層配線構造およびその製造方法
US6069082A (en) * 1998-10-13 2000-05-30 Chartered Semiconductor Manufacturing Ltd. Method to prevent dishing in damascene CMP process
US6149776A (en) * 1998-11-12 2000-11-21 Applied Materials, Inc. Copper sputtering target
US6909114B1 (en) 1998-11-17 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having LDD regions
US6184137B1 (en) 1998-11-25 2001-02-06 Applied Materials, Inc. Structure and method for improving low temperature copper reflow in semiconductor features
KR100493013B1 (ko) * 1998-11-30 2005-08-01 삼성전자주식회사 반도체소자의 금속 배선층 형성방법_
US6140240A (en) * 1999-01-07 2000-10-31 Vanguard International Semiconductor Corporation Method for eliminating CMP induced microscratches
US6114246A (en) * 1999-01-07 2000-09-05 Vlsi Technology, Inc. Method of using a polish stop film to control dishing during copper chemical mechanical polishing
US6358790B1 (en) 1999-01-13 2002-03-19 Agere Systems Guardian Corp. Method of making a capacitor
US6323537B1 (en) * 1999-01-13 2001-11-27 Agere Systems Guardian Corp. Capacitor for an integrated circuit
US20020127845A1 (en) * 1999-03-01 2002-09-12 Paul A. Farrar Conductive structures in integrated circuits
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6350690B1 (en) * 1999-04-09 2002-02-26 Advanced Micro Devices, Inc. Process for achieving full global planarization during CMP of damascene semiconductor structures
US6235633B1 (en) 1999-04-12 2001-05-22 Taiwan Semiconductor Manufacturing Company Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process
US6329280B1 (en) 1999-05-13 2001-12-11 International Business Machines Corporation Interim oxidation of silsesquioxane dielectric for dual damascene process
US6071808A (en) * 1999-06-23 2000-06-06 Lucent Technologies Inc. Method of passivating copper interconnects in a semiconductor
US6046108A (en) * 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US6130157A (en) * 1999-07-16 2000-10-10 Taiwan Semiconductor Manufacturing Company Method to form an encapsulation layer over copper interconnects
US6521532B1 (en) 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
US6551872B1 (en) 1999-07-22 2003-04-22 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby
JP2001036080A (ja) 1999-07-26 2001-02-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6413854B1 (en) 1999-08-24 2002-07-02 International Business Machines Corp. Method to build multi level structure
JP2001135168A (ja) * 1999-08-26 2001-05-18 Sharp Corp 金属配線の製造方法
US7071557B2 (en) 1999-09-01 2006-07-04 Micron Technology, Inc. Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same
US6433429B1 (en) * 1999-09-01 2002-08-13 International Business Machines Corporation Copper conductive line with redundant liner and method of making
US6441492B1 (en) 1999-09-10 2002-08-27 James A. Cunningham Diffusion barriers for copper interconnect systems
US6734559B1 (en) 1999-09-17 2004-05-11 Advanced Micro Devices, Inc. Self-aligned semiconductor interconnect barrier and manufacturing method therefor
US6207558B1 (en) 1999-10-21 2001-03-27 Applied Materials, Inc. Barrier applications for aluminum planarization
US6348736B1 (en) 1999-10-29 2002-02-19 International Business Machines Corporation In situ formation of protective layer on silsesquioxane dielectric for dual damascene process
JP4236778B2 (ja) * 1999-11-01 2009-03-11 株式会社ルネサステクノロジ 半導体装置
US6417106B1 (en) 1999-11-01 2002-07-09 Taiwan Semiconductor Manufacturing Company Underlayer liner for copper damascene in low k dielectric
US6551924B1 (en) 1999-11-02 2003-04-22 International Business Machines Corporation Post metalization chem-mech polishing dielectric etch
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
US6344419B1 (en) 1999-12-03 2002-02-05 Applied Materials, Inc. Pulsed-mode RF bias for sidewall coverage improvement
US6403465B1 (en) 1999-12-28 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to improve copper barrier properties
US7211512B1 (en) 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US7262130B1 (en) 2000-01-18 2007-08-28 Micron Technology, Inc. Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6376370B1 (en) * 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
JP2001223460A (ja) * 2000-02-08 2001-08-17 Fujitsu Ltd 実装回路基板及びその製造方法
US6633083B2 (en) * 2000-02-28 2003-10-14 Advanced Micro Devices Inc. Barrier layer integrity test
EP1143506A3 (en) * 2000-04-04 2004-02-25 Nippon Telegraph and Telephone Corporation Pattern forming method
JP2001319928A (ja) * 2000-05-08 2001-11-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
US6674167B1 (en) * 2000-05-31 2004-01-06 Micron Technology, Inc. Multilevel copper interconnect with double passivation
US6554979B2 (en) 2000-06-05 2003-04-29 Applied Materials, Inc. Method and apparatus for bias deposition in a modulating electric field
US6501180B1 (en) * 2000-07-19 2002-12-31 National Semiconductor Corporation Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
US6218301B1 (en) 2000-07-31 2001-04-17 Applied Materials, Inc. Deposition of tungsten films from W(CO)6
JP2002050595A (ja) * 2000-08-04 2002-02-15 Hitachi Ltd 研磨方法、配線形成方法及び半導体装置の製造方法
JP2002050767A (ja) * 2000-08-04 2002-02-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6617689B1 (en) 2000-08-31 2003-09-09 Micron Technology, Inc. Metal line and method of suppressing void formation therein
US7518284B2 (en) * 2000-11-02 2009-04-14 Danfoss A/S Dielectric composite and a method of manufacturing a dielectric composite
US7548015B2 (en) * 2000-11-02 2009-06-16 Danfoss A/S Multilayer composite and a method of making such
US8181338B2 (en) * 2000-11-02 2012-05-22 Danfoss A/S Method of making a multilayer composite
DE10054247C2 (de) * 2000-11-02 2002-10-24 Danfoss As Betätigungselement und Verfahren zu seiner Herstellung
US6436814B1 (en) 2000-11-21 2002-08-20 International Business Machines Corporation Interconnection structure and method for fabricating same
US6503641B2 (en) * 2000-12-18 2003-01-07 International Business Machines Corporation Interconnects with Ti-containing liners
US6680514B1 (en) * 2000-12-20 2004-01-20 International Business Machines Corporation Contact capping local interconnect
US6388327B1 (en) 2001-01-09 2002-05-14 International Business Machines Corporation Capping layer for improved silicide formation in narrow semiconductor structures
JP2002208633A (ja) * 2001-01-10 2002-07-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002217292A (ja) * 2001-01-23 2002-08-02 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
US6524929B1 (en) 2001-02-26 2003-02-25 Advanced Micro Devices, Inc. Method for shallow trench isolation using passivation material for trench bottom liner
US6486038B1 (en) 2001-03-12 2002-11-26 Advanced Micro Devices Method for and device having STI using partial etch trench bottom liner
US7087997B2 (en) * 2001-03-12 2006-08-08 International Business Machines Corporation Copper to aluminum interlayer interconnect using stud and via liner
US6521510B1 (en) 2001-03-23 2003-02-18 Advanced Micro Devices, Inc. Method for shallow trench isolation with removal of strained island edges
US6534379B1 (en) 2001-03-26 2003-03-18 Advanced Micro Devices, Inc. Linerless shallow trench isolation method
US6504225B1 (en) * 2001-04-18 2003-01-07 Advanced Micro Devices, Inc. Teos seaming scribe line monitor
US6743666B1 (en) * 2001-04-27 2004-06-01 Advanced Micro Devices, Inc. Selective thickening of the source-drain and gate areas of field effect transistors
JP4350337B2 (ja) * 2001-04-27 2009-10-21 富士通マイクロエレクトロニクス株式会社 半導体装置
US7372160B2 (en) * 2001-05-31 2008-05-13 Stmicroelectronics, Inc. Barrier film deposition over metal for reduction in metal dishing after CMP
JP2002367998A (ja) * 2001-06-11 2002-12-20 Ebara Corp 半導体装置及びその製造方法
US6521523B2 (en) 2001-06-15 2003-02-18 Silicon Integrated Systems Corp. Method for forming selective protection layers on copper interconnects
US6782205B2 (en) 2001-06-25 2004-08-24 Silicon Light Machines Method and apparatus for dynamic equalization in wavelength division multiplexing
US6747781B2 (en) 2001-06-25 2004-06-08 Silicon Light Machines, Inc. Method, apparatus, and diffuser for reducing laser speckle
TW591089B (en) * 2001-08-09 2004-06-11 Cheil Ind Inc Slurry composition for use in chemical mechanical polishing of metal wiring
US6953389B2 (en) * 2001-08-09 2005-10-11 Cheil Industries, Inc. Metal CMP slurry compositions that favor mechanical removal of oxides with reduced susceptibility to micro-scratching
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
JP2003068848A (ja) * 2001-08-29 2003-03-07 Fujitsu Ltd 半導体装置及びその製造方法
US6989108B2 (en) * 2001-08-30 2006-01-24 Micron Technology, Inc. Etchant gas composition
US6930364B2 (en) * 2001-09-13 2005-08-16 Silicon Light Machines Corporation Microelectronic mechanical system and methods
US6746591B2 (en) 2001-10-16 2004-06-08 Applied Materials Inc. ECP gap fill by modulating the voltate on the seed layer to increase copper concentration inside feature
JP4198906B2 (ja) * 2001-11-15 2008-12-17 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
US6815342B1 (en) * 2001-11-27 2004-11-09 Lsi Logic Corporation Low resistance metal interconnect lines and a process for fabricating them
DE60224844T2 (de) * 2001-12-21 2009-01-08 Danfoss A/S Dielektrisches betätigungsglied oder sensorstruktur und herstellungsverfahren
KR100435784B1 (ko) * 2001-12-21 2004-06-12 동부전자 주식회사 반도체 소자의 금속배선 형성 방법
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
US6770566B1 (en) 2002-03-06 2004-08-03 Cypress Semiconductor Corporation Methods of forming semiconductor structures, and articles and devices formed thereby
US7294567B2 (en) * 2002-03-11 2007-11-13 Micron Technology, Inc. Semiconductor contact device and method
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6822797B1 (en) 2002-05-31 2004-11-23 Silicon Light Machines, Inc. Light modulator structure for producing high-contrast operation using zero-order light
US6829258B1 (en) 2002-06-26 2004-12-07 Silicon Light Machines, Inc. Rapidly tunable external cavity laser
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US6714337B1 (en) 2002-06-28 2004-03-30 Silicon Light Machines Method and device for modulating a light beam and having an improved gamma response
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
EP1540807B1 (en) * 2002-09-20 2013-01-09 Danfoss A/S Elastomer actuator and method of making the actuator
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
US6713873B1 (en) * 2002-11-27 2004-03-30 Intel Corporation Adhesion between dielectric materials
DE60328913D1 (de) * 2002-12-12 2009-10-01 Danfoss As Berührungssensorelement und sensorgruppe
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
ES2309502T3 (es) 2003-02-24 2008-12-16 Danfoss A/S Vendaje de compresion elastico electroactivo.
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US20040248405A1 (en) * 2003-06-02 2004-12-09 Akira Fukunaga Method of and apparatus for manufacturing semiconductor device
US20040245636A1 (en) * 2003-06-06 2004-12-09 International Business Machines Corporation Full removal of dual damascene metal level
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
KR100528069B1 (ko) * 2003-09-02 2005-11-15 동부아남반도체 주식회사 반도체 소자 및 그 제조 방법
JP4130621B2 (ja) * 2003-10-30 2008-08-06 株式会社東芝 半導体装置およびその製造方法
KR100561523B1 (ko) * 2003-12-31 2006-03-16 동부아남반도체 주식회사 알루미늄 배선 형성 방법
KR100590205B1 (ko) * 2004-01-12 2006-06-15 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
US7090516B2 (en) * 2004-02-09 2006-08-15 Adc Telecommunications, Inc. Protective boot and universal cap
JP2005235860A (ja) * 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7956672B2 (en) * 2004-03-30 2011-06-07 Ricoh Company, Ltd. Reference voltage generating circuit
US7378744B2 (en) * 2004-05-10 2008-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
US7067409B2 (en) * 2004-05-10 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
KR20050114784A (ko) * 2004-06-01 2005-12-07 동부아남반도체 주식회사 반도체 소자의 구리배선 형성방법
KR100628242B1 (ko) * 2004-06-24 2006-09-26 동부일렉트로닉스 주식회사 반도체 소자의 베리어층 형성 방법
KR100602087B1 (ko) * 2004-07-09 2006-07-14 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
KR101101192B1 (ko) * 2004-08-26 2012-01-03 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
JP4503401B2 (ja) * 2004-09-08 2010-07-14 株式会社荏原製作所 金属膜の成膜方法及び配線の形成方法
KR100552857B1 (ko) * 2004-10-25 2006-02-22 동부아남반도체 주식회사 반도체 소자의 콘택 형성 방법
US20060113675A1 (en) * 2004-12-01 2006-06-01 Chung-Liang Chang Barrier material and process for Cu interconnect
US7105445B2 (en) * 2005-01-14 2006-09-12 International Business Machines Corporation Interconnect structures with encasing cap and methods of making thereof
US7335588B2 (en) * 2005-04-15 2008-02-26 International Business Machines Corporation Interconnect structure and method of fabrication of same
US7323410B2 (en) 2005-08-08 2008-01-29 International Business Machines Corporation Dry etchback of interconnect contacts
US7563704B2 (en) * 2005-09-19 2009-07-21 International Business Machines Corporation Method of forming an interconnect including a dielectric cap having a tensile stress
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
US7253100B2 (en) * 2005-11-17 2007-08-07 International Business Machines Corporation Reducing damage to ulk dielectric during cross-linked polymer removal
US7863183B2 (en) * 2006-01-18 2011-01-04 International Business Machines Corporation Method for fabricating last level copper-to-C4 connection with interfacial cap structure
TWI293499B (en) * 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI287273B (en) * 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
US8193087B2 (en) * 2006-05-18 2012-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Process for improving copper line cap formation
US20080077436A1 (en) * 2006-06-01 2008-03-27 Igeacare Systems Inc. Home based healthcare system and method
CA2653434A1 (en) * 2006-06-01 2008-03-27 Igeacare Systems, Inc. Remote health care system with stethoscope
WO2007138489A2 (en) * 2006-06-01 2007-12-06 Rajiv Muradia Remote health care system with treatment verification
US20080091470A1 (en) * 2006-06-01 2008-04-17 Igeacare Systems Inc. Remote health care diagnostic tool
EP2051287A4 (en) * 2006-08-10 2014-05-21 Ulvac Inc METHOD FOR FORMING A CONDUCTIVE FILM, THIN FILM TRANSISTOR, PANEL WITH THIN FILM TRANSISTOR AND METHOD FOR PRODUCING A THIN FILM TRANSISTOR
US7880371B2 (en) * 2006-11-03 2011-02-01 Danfoss A/S Dielectric composite and a method of manufacturing a dielectric composite
US7732999B2 (en) * 2006-11-03 2010-06-08 Danfoss A/S Direct acting capacitive transducer
US7569475B2 (en) * 2006-11-15 2009-08-04 International Business Machines Corporation Interconnect structure having enhanced electromigration reliability and a method of fabricating same
US7576003B2 (en) * 2006-11-29 2009-08-18 International Business Machines Corporation Dual liner capping layer interconnect structure and method
DE102007004884A1 (de) * 2007-01-31 2008-08-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht
US7859113B2 (en) * 2007-02-27 2010-12-28 International Business Machines Corporation Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method
US7655556B2 (en) * 2007-03-23 2010-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for semiconductor devices
US7790599B2 (en) * 2007-04-13 2010-09-07 International Business Machines Corporation Metal cap for interconnect structures
US8502272B2 (en) 2007-05-16 2013-08-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Metal-oxide-semiconductor high electron mobility transistors and methods of fabrication
TWI339444B (en) * 2007-05-30 2011-03-21 Au Optronics Corp Conductor structure, pixel structure, and methods of forming the same
US7732924B2 (en) 2007-06-12 2010-06-08 International Business Machines Corporation Semiconductor wiring structures including dielectric cap within metal cap layer
JP4637872B2 (ja) * 2007-06-12 2011-02-23 シャープ株式会社 配線構造およびその製造方法
US7884018B2 (en) * 2007-06-21 2011-02-08 International Business Machines Corporation Method for improving the selectivity of a CVD process
US8138604B2 (en) 2007-06-21 2012-03-20 International Business Machines Corporation Metal cap with ultra-low k dielectric material for circuit interconnect applications
US7927990B2 (en) * 2007-06-29 2011-04-19 Sandisk Corporation Forming complimentary metal features using conformal insulator layer
KR100905872B1 (ko) * 2007-08-24 2009-07-03 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법
US7615831B2 (en) * 2007-10-26 2009-11-10 International Business Machines Corporation Structure and method for fabricating self-aligned metal contacts
US7964923B2 (en) * 2008-01-07 2011-06-21 International Business Machines Corporation Structure and method of creating entirely self-aligned metallic contacts
US7998864B2 (en) * 2008-01-29 2011-08-16 International Business Machines Corporation Noble metal cap for interconnect structures
US7834457B2 (en) * 2008-02-28 2010-11-16 International Business Machines Corporation Bilayer metal capping layer for interconnect applications
US7830010B2 (en) 2008-04-03 2010-11-09 International Business Machines Corporation Surface treatment for selective metal cap applications
EP2283265A2 (en) * 2008-04-30 2011-02-16 Danfoss Polypower A/S A power actuated valve
US20110189027A1 (en) * 2008-04-30 2011-08-04 Morten Kjaer Hansen Pump powered by a polymer transducer
US7956466B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
US8772156B2 (en) * 2008-05-09 2014-07-08 International Business Machines Corporation Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
US8354751B2 (en) * 2008-06-16 2013-01-15 International Business Machines Corporation Interconnect structure for electromigration enhancement
US8013446B2 (en) * 2008-08-12 2011-09-06 International Business Machines Corporation Nitrogen-containing metal cap for interconnect structures
US7939911B2 (en) * 2008-08-14 2011-05-10 International Business Machines Corporation Back-end-of-line resistive semiconductor structures
US7977201B2 (en) * 2008-08-14 2011-07-12 International Business Machines Corporation Methods for forming back-end-of-line resistive semiconductor structures
US8232645B2 (en) 2008-08-14 2012-07-31 International Business Machines Corporation Interconnect structures, design structure and method of manufacture
US8823176B2 (en) * 2008-10-08 2014-09-02 International Business Machines Corporation Discontinuous/non-uniform metal cap structure and process for interconnect integration
JP5406556B2 (ja) * 2009-02-23 2014-02-05 関東化学株式会社 金属積層膜用エッチング液組成物
US20100276764A1 (en) 2009-05-04 2010-11-04 Yi-Jen Lo Semiconductor structure with selectively deposited tungsten film and method for making the same
TWI459507B (zh) * 2009-06-18 2014-11-01 United Microelectronics Corp 一種製作矽貫通電極的方法
KR101604054B1 (ko) * 2009-09-03 2016-03-16 삼성전자주식회사 반도체 소자 및 그 형성방법
US8039966B2 (en) * 2009-09-03 2011-10-18 International Business Machines Corporation Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects
US8411970B2 (en) * 2010-03-16 2013-04-02 Pixia Corp. Method and system for determining statistical data for image pixels having a higher bit depth per band
US9425146B2 (en) 2010-09-28 2016-08-23 Infineon Technologies Ag Semiconductor structure and method for making same
DE102010063294B4 (de) * 2010-12-16 2019-07-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Metallisierungssystemen von Halbleiterbauelementen, die eine Kupfer/Silizium-Verbindung als ein Barrierenmaterial aufweisen
WO2012133400A1 (ja) * 2011-03-30 2012-10-04 東京エレクトロン株式会社 Ｃｕ配線の形成方法
EP2535441A1 (en) * 2011-06-14 2012-12-19 Atotech Deutschland GmbH Copper filled opening with a cap layer
JP5949294B2 (ja) * 2011-08-31 2016-07-06 日亜化学工業株式会社 半導体発光素子
US8877645B2 (en) 2011-09-15 2014-11-04 International Business Machines Corporation Integrated circuit structure having selectively formed metal cap
US8492274B2 (en) 2011-11-07 2013-07-23 International Business Machines Corporation Metal alloy cap integration
US8692442B2 (en) 2012-02-14 2014-04-08 Danfoss Polypower A/S Polymer transducer and a connector for a transducer
US8891222B2 (en) 2012-02-14 2014-11-18 Danfoss A/S Capacitive transducer and a method for manufacturing a transducer
US8796853B2 (en) * 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
KR101907694B1 (ko) * 2012-03-06 2018-10-12 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
CN103390647A (zh) * 2012-05-10 2013-11-13 无锡华润上华半导体有限公司 一种功率mos器件结构
US9034664B2 (en) * 2012-05-16 2015-05-19 International Business Machines Corporation Method to resolve hollow metal defects in interconnects
KR101992352B1 (ko) 2012-09-25 2019-06-24 삼성전자주식회사 반도체 장치
US9312203B2 (en) 2013-01-02 2016-04-12 Globalfoundries Inc. Dual damascene structure with liner
US8883020B2 (en) * 2013-01-30 2014-11-11 GlobalFoundries, Inc. Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
US9536830B2 (en) 2013-05-09 2017-01-03 Globalfoundries Inc. High performance refractory metal / copper interconnects to eliminate electromigration
US9171801B2 (en) 2013-05-09 2015-10-27 Globalfoundries U.S. 2 Llc E-fuse with hybrid metallization
US9305879B2 (en) 2013-05-09 2016-04-05 Globalfoundries Inc. E-fuse with hybrid metallization
US8962479B2 (en) 2013-05-10 2015-02-24 International Business Machines Corporation Interconnect structures containing nitrided metallic residues
US9558999B2 (en) 2013-09-12 2017-01-31 Globalfoundries Inc. Ultra-thin metal wires formed through selective deposition
US9202749B2 (en) 2014-02-06 2015-12-01 International Business Machines Corporation Process methods for advanced interconnect patterning
US9281211B2 (en) 2014-02-10 2016-03-08 International Business Machines Corporation Nanoscale interconnect structure
US10079174B2 (en) 2014-04-30 2018-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Composite contact plug structure and method of making same
US9379221B1 (en) 2015-01-08 2016-06-28 International Business Machines Corporation Bottom-up metal gate formation on replacement metal gate finFET devices
US9913382B2 (en) * 2015-04-23 2018-03-06 Viasystems Technologies Corp. L.L.C. Method for anchoring a conductive cap on a filled via in a printed circuit board and printed circuit board with an anchored conductive cap
US9595473B2 (en) 2015-06-01 2017-03-14 International Business Machines Corporation Critical dimension shrink through selective metal growth on metal hardmask sidewalls
US9588298B2 (en) 2015-06-04 2017-03-07 Elenion Technologies, Llc Edge coupler
JP6738556B2 (ja) * 2015-06-26 2020-08-12 三菱マテリアル株式会社 表面被覆切削工具
US9748169B1 (en) 2016-04-04 2017-08-29 International Business Machines Corporation Treating copper interconnects
CN107564850B (zh) * 2016-07-01 2020-07-07 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
US10593563B2 (en) * 2017-04-13 2020-03-17 Invensas Corporation Fan-out wafer level package with resist vias
KR102378672B1 (ko) * 2017-05-17 2022-03-24 이매진 코퍼레이션 고정밀 섀도 마스크 증착 시스템 및 그 방법
CN107170788A (zh) * 2017-06-06 2017-09-15 武汉华星光电技术有限公司 一种显示屏
DE102017216937A1 (de) * 2017-09-25 2019-03-28 Robert Bosch Gmbh Verfahren zum Herstellen zumindest einer Durchkontaktierung in einem Wafer
US10886225B2 (en) 2018-03-05 2021-01-05 International Business Machines Corporation BEOL alternative metal interconnects: integration and process
US11018087B2 (en) 2018-04-25 2021-05-25 International Business Machines Corporation Metal interconnects
CN109003767B (zh) * 2018-07-18 2023-11-28 昆山万盛电子有限公司 一种横卧安装的压敏电阻器及其制备方法
US11081493B2 (en) * 2019-05-16 2021-08-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor memory device with sacrificial via
CN116013853B (zh) * 2023-03-27 2023-06-02 合肥晶合集成电路股份有限公司 互连结构的制备方法

Family Cites Families (114)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1399163A (en) * 1972-11-08 1975-06-25 Ferranti Ltd Methods of manufacturing semiconductor devices
US3911562A (en) * 1974-01-14 1975-10-14 Signetics Corp Method of chemical polishing of planar silicon structures having filled grooves therein
CH611938A5 (zh) * 1976-05-19 1979-06-29 Battelle Memorial Institute
DE2705225C2 (de) * 1976-06-07 1983-03-24 Nobuo Tokyo Nishida Ornamentteil für Uhren usw.
JPS5425178A (en) * 1977-07-27 1979-02-24 Fujitsu Ltd Manufacture for semiconductor device
US4244775A (en) * 1979-04-30 1981-01-13 Bell Telephone Laboratories, Incorporated Process for the chemical etch polishing of semiconductors
US4293374A (en) * 1980-03-10 1981-10-06 International Business Machines Corporation High aspect ratio, high resolution mask fabrication
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4339305A (en) * 1981-02-05 1982-07-13 Rockwell International Corporation Planar circuit fabrication by plating and liftoff
JPS5815250A (ja) * 1981-07-21 1983-01-28 Fujitsu Ltd 半導体装置の製造方法
JPS5821844A (ja) * 1981-07-31 1983-02-08 Nippon Telegr & Teleph Corp <Ntt> 配線構造体の製造方法
JPS5830147A (ja) 1981-08-18 1983-02-22 Toshiba Corp 半導体装置
DE3141567C2 (de) * 1981-10-20 1986-02-06 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von aus Tantal, Wolfram oder Molybdän bestehenden Schichten bei niedrigen Temperaturen und Verwendung dieser Schichten
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
JPS58210634A (ja) * 1982-05-31 1983-12-07 Toshiba Corp 半導体装置の製造方法
JPS5982746A (ja) * 1982-11-04 1984-05-12 Toshiba Corp 半導体装置の電極配線方法
JPS59121835A (ja) * 1982-12-28 1984-07-14 Fujitsu Ltd 半導体装置及びその製造方法
JPS59175763A (ja) * 1983-03-25 1984-10-04 Fujitsu Ltd 半導体装置
US4565157A (en) * 1983-03-29 1986-01-21 Genus, Inc. Method and apparatus for deposition of tungsten silicides
KR910006249B1 (ko) * 1983-04-01 1991-08-17 가부시기가이샤 히다찌세이사꾸쇼 반도체 장치
GB2137808A (en) * 1983-04-06 1984-10-10 Plessey Co Plc Integrated circuit processing method
US4486946A (en) * 1983-07-12 1984-12-11 Control Data Corporation Method for using titanium-tungsten alloy as a barrier metal in silicon semiconductor processing
US4600624A (en) * 1983-09-20 1986-07-15 International Business Machines Corporation Composite insulator structure
US4532702A (en) * 1983-11-04 1985-08-06 Westinghouse Electric Corp. Method of forming conductive interconnection between vertically spaced levels in VLSI devices
JPS60115245A (ja) * 1983-11-28 1985-06-21 Toshiba Corp 半導体装置の製造方法
JPS60117719A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd 半導体装置の製造方法
CA1260754A (en) * 1983-12-26 1989-09-26 Teiji Majima Method for forming patterns and apparatus used for carrying out the same
JPS60142545A (ja) * 1983-12-27 1985-07-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 多層複合構造体
JPS60173857A (ja) * 1984-02-20 1985-09-07 Toshiba Corp 半導体装置の製造方法
US4851295A (en) * 1984-03-16 1989-07-25 Genus, Inc. Low resistivity tungsten silicon composite film
US4845050A (en) * 1984-04-02 1989-07-04 General Electric Company Method of making mo/tiw or w/tiw ohmic contacts to silicon
US4640004A (en) * 1984-04-13 1987-02-03 Fairchild Camera & Instrument Corp. Method and structure for inhibiting dopant out-diffusion
FR2566181B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
US4526631A (en) * 1984-06-25 1985-07-02 International Business Machines Corporation Method for forming a void free isolation pattern utilizing etch and refill techniques
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias
US4720908A (en) * 1984-07-11 1988-01-26 Texas Instruments Incorporated Process for making contacts and interconnects for holes having vertical sidewalls
US4751197A (en) * 1984-07-18 1988-06-14 Texas Instruments Incorporated Make-link programming of semiconductor devices using laser enhanced thermal breakdown of insulator
JPH0713295B2 (ja) * 1985-02-22 1995-02-15 株式会社日立製作所 スパツタリング装置
US4560435A (en) * 1984-10-01 1985-12-24 International Business Machines Corporation Composite back-etch/lift-off stencil for proximity effect minimization
KR900001825B1 (ko) * 1984-11-14 1990-03-24 가부시끼가이샤 히다찌세이사꾸쇼 성막 지향성을 고려한 스퍼터링장치
JPH0697693B2 (ja) * 1984-12-05 1994-11-30 株式会社東芝 Ｍｏｓ型ｆｅｔのゲート構造の製造方法
JPS61137367A (ja) * 1984-12-10 1986-06-25 Hitachi Ltd 半導体集積回路装置の製造方法
US4659427A (en) * 1984-12-31 1987-04-21 Gte Laboratories Incorporated Via formation for multilayered metalization
US5045916A (en) * 1985-01-22 1991-09-03 Fairchild Semiconductor Corporation Extended silicide and external contact technology
DE3650077T2 (de) * 1985-03-15 1995-02-23 Hewlett Packard Co Metallisches Verbindungssystem mit einer ebenen Fläche.
FR2583220B1 (fr) * 1985-06-11 1987-08-07 Thomson Csf Procede de realisation d'au moins deux metallisations d'un composant semi-conducteur, recouvertes d'une couche de dielectrique et composant obtenu par ce dielectrique
US4617087A (en) * 1985-09-27 1986-10-14 International Business Machines Corporation Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US4702792A (en) * 1985-10-28 1987-10-27 International Business Machines Corporation Method of forming fine conductive lines, patterns and connectors
US4824802A (en) * 1986-02-28 1989-04-25 General Electric Company Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures
US4746219A (en) * 1986-03-07 1988-05-24 Texas Instruments Incorporated Local interconnect
US4689113A (en) * 1986-03-21 1987-08-25 International Business Machines Corporation Process for forming planar chip-level wiring
US4849079A (en) * 1986-05-23 1989-07-18 International Business Machines Corp. Process for preparing low electrical contact resistance composition
US4756927A (en) * 1986-05-29 1988-07-12 Massachusetts Institute Of Technology Method and apparatus for refractory metal deposition
DE3772659D1 (de) * 1986-06-28 1991-10-10 Ulvac Corp Verfahren und vorrichtung zum beschichten unter anwendung einer cvd-beschichtungstechnik.
DE3783405T2 (de) * 1986-08-19 1993-08-05 Fujitsu Ltd Halbleiteranordnung mit einer duennschicht-verdrahtung und verfahren zum herstellen derselben.
EP0261846B1 (en) * 1986-09-17 1992-12-02 Fujitsu Limited Method of forming a metallization film containing copper on the surface of a semiconductor device
US4924295A (en) * 1986-11-28 1990-05-08 Siemens Aktiengesellschaft Integrated semi-conductor circuit comprising at least two metallization levels composed of aluminum or aluminum compounds and a method for the manufacture of same
US4732658A (en) * 1986-12-03 1988-03-22 Honeywell Inc. Planarization of silicon semiconductor devices
US4756810A (en) * 1986-12-04 1988-07-12 Machine Technology, Inc. Deposition and planarizing methods and apparatus
US4855798A (en) * 1986-12-19 1989-08-08 Texas Instruments Incorporated Semiconductor and process of fabrication thereof
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device
US4783248A (en) * 1987-02-10 1988-11-08 Siemens Aktiengesellschaft Method for the production of a titanium/titanium nitride double layer
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPS63269546A (ja) * 1987-04-27 1988-11-07 Nec Corp 半導体装置の製造方法
JPS63299251A (ja) * 1987-05-29 1988-12-06 Toshiba Corp 半導体装置の製造方法
JPH0660391B2 (ja) * 1987-06-11 1994-08-10 日電アネルバ株式会社 スパッタリング装置
US4956313A (en) * 1987-08-17 1990-09-11 International Business Machines Corporation Via-filling and planarization technique
US4902645A (en) * 1987-08-24 1990-02-20 Fujitsu Limited Method of selectively forming a silicon-containing metal layer
JPS6460011A (en) * 1987-08-31 1989-03-07 Nec Corp High frequency transistor amplifier
EP0312986A1 (de) * 1987-10-22 1989-04-26 Siemens Aktiengesellschaft Verfahren zum Rückätzen von Wolfram mit Titannitrid als Unterlage in Kontaktlöchern von höchstintegrierten Halbleiterschaltungen
US4824544A (en) * 1987-10-29 1989-04-25 International Business Machines Corporation Large area cathode lift-off sputter deposition device
US4873565A (en) * 1987-11-02 1989-10-10 Texas Instruments Incorporated Method and apparatus for providing interconnection between metallization layers on semiconductor devices
JPH0654774B2 (ja) * 1987-11-30 1994-07-20 株式会社東芝 半導体装置及びその製造方法
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US4926237A (en) * 1988-04-04 1990-05-15 Motorola, Inc. Device metallization, device and method
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
FR2630587A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour etablir des contacts electriques de petites dimensions sur un dispositif semiconducteur
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
DE3881032T2 (de) * 1988-05-26 1993-11-25 Fairchild Semiconductor Verbindungssystem von hoher Leistungsfähigkeit für eine integrierte Schaltung.
US5027185A (en) * 1988-06-06 1991-06-25 Industrial Technology Research Institute Polycide gate FET with salicide
US4847111A (en) * 1988-06-30 1989-07-11 Hughes Aircraft Company Plasma-nitridated self-aligned tungsten system for VLSI interconnections
US5008730A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Contact stud structure for semiconductor devices
US5112693A (en) * 1988-10-03 1992-05-12 Ppg Industries, Inc. Low reflectance, highly saturated colored coating for monolithic glazing
JPH02170424A (ja) * 1988-12-22 1990-07-02 Nec Corp 半導体装置の製造方法
US5084417A (en) * 1989-01-06 1992-01-28 International Business Machines Corporation Method for selective deposition of refractory metals on silicon substrates and device formed thereby
JP2537413B2 (ja) * 1989-03-14 1996-09-25 三菱電機株式会社 半導体装置およびその製造方法
US4920073A (en) * 1989-05-11 1990-04-24 Texas Instruments, Incorporated Selective silicidation process using a titanium nitride protective layer
US5169685A (en) * 1989-06-12 1992-12-08 General Electric Company Method for forming non-columnar deposits by chemical vapor deposition
US4994162A (en) * 1989-09-29 1991-02-19 Materials Research Corporation Planarization method
JP2732539B2 (ja) * 1989-10-06 1998-03-30 日本電気株式会社 真空成膜装置
US5070391A (en) * 1989-11-30 1991-12-03 Sgs-Thomson Microelectronics, Inc. Semiconductor contact via structure and method
US5026470A (en) * 1989-12-19 1991-06-25 International Business Machines Sputtering apparatus
DE69129081T2 (de) * 1990-01-29 1998-07-02 Varian Associates Gerät und Verfahren zur Niederschlagung durch einen Kollimator
US5008217A (en) * 1990-06-08 1991-04-16 At&T Bell Laboratories Process for fabricating integrated circuits having shallow junctions
US4992135A (en) * 1990-07-24 1991-02-12 Micron Technology, Inc. Method of etching back of tungsten layers on semiconductor wafers, and solution therefore
US5138432A (en) * 1990-08-30 1992-08-11 Cornell Research Foundation, Inc. Selective deposition of tungsten on TiSi2
KR100228259B1 (ko) * 1990-10-24 1999-11-01 고지마 마따오 박막의 형성방법 및 반도체장치
JP2841976B2 (ja) * 1990-11-28 1998-12-24 日本電気株式会社 半導体装置およびその製造方法
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
US5187119A (en) * 1991-02-11 1993-02-16 The Boeing Company Multichip module and integrated circuit substrates having planarized patterned surfaces
US5143867A (en) * 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
US5243222A (en) * 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
CA2061119C (en) * 1991-04-19 1998-02-03 Pei-Ing P. Lee Method of depositing conductors in high aspect ratio apertures
JPH05160070A (ja) * 1991-05-31 1993-06-25 Texas Instr Inc <Ti> 半導体装置の接点とその製法
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5244836A (en) * 1991-12-30 1993-09-14 North American Philips Corporation Method of manufacturing fusible links in semiconductor devices
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5300812A (en) * 1992-12-09 1994-04-05 General Electric Company Plasticized polyetherimide adhesive composition and usage
US5817574A (en) * 1993-12-29 1998-10-06 Intel Corporation Method of forming a high surface area interconnection structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456617A (zh) * 2010-10-27 2012-05-16 国际商业机器公司 形成自对准局部互连的方法和由此形成的结构

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