TW298674B - - Google Patents
Download PDFInfo
- Publication number
- TW298674B TW298674B TW085105748A TW85105748A TW298674B TW 298674 B TW298674 B TW 298674B TW 085105748 A TW085105748 A TW 085105748A TW 85105748 A TW85105748 A TW 85105748A TW 298674 B TW298674 B TW 298674B
- Authority
- TW
- Taiwan
- Prior art keywords
- patent application
- layer
- conductive
- item
- conductive layer
- Prior art date
Links
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 230000002079 cooperative effect Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 230000035622 drinking Effects 0.000 claims 1
- 238000009472 formulation Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 26
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 26
- 238000000151 deposition Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- -1 silicon Chemical compound 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
五 發明説明( A7 B7 經濟部中央梯準局員工消費合作社印製 妹術領域 本發明係關於半導醴積體電路及其製法。 發明背景 典型的現代積體電路都利用金屬導體來連接獨立的電晶 趙。通常,導體是由鋁作成的《許多積體電路的製程,都 需要在介電層内形成一個窗孔,有時稱之爲「通孔」。然 後會用銘填滿通孔。通孔内的鋁通常會接觸另一個鋁導體 ,或是一面半導體基板。 因爲通孔的大小隨著精進的半導禮製程不斷地縮小,要 在小通孔内沉積鋁變得非常困難。為了要解決這個問題,一 些製造商使用兩道步驟來沉積鋁。第一次沉積鋁時是在低 溫下進行,所以有很小的鋁晶粒。随後沉積鋁時在較高的 溫度下進行,所以晶粒較大。兩次沉積都使用標準的鋁濺 艘技術進行《但是’這種製程並不總是能很理想地控制晶 粒的成長。這種技術所形成的導體很可能爲因晶粒成長失 去控制’而導致電子遷移的失誤a 其他人則利用平行鋁束來濺鍍鋁。鋁束要調成平行時, 可用一個栅極,有時可在濺鍍靶和基板之間加上一個固定 的電壓。結果,可以得到一束瞄準的鋁,用來沉積在通孔 中。但疋平行的鋁沉積非常慢,對量產很不實際。此外, 許多(多至二分之一)的鋁會沉積在栅極上,浪費材料,也 提高成本,降低產出量。而且,沉積膜層抵抗電子遷移的 能力也很可疑。 因此。關心積體電路量產製程的人,仍然繼續地尋找沉
-----.—^^ — (請先閱讀背面之注意事項再填寫本頁) 订
In · 經濟部中央揉準局負工消费合作社印*. A7 B7 五、發明説明(2 ) 一 積鋁更好的技術。 發明的簡要説明 本發明之積體電路的改良製法包括: 使-平行的導電粒子束導在—面基板上,在該基板上形 成一層膜層,而成爲第—導電層,然後以不平行的方式使 導電粒子濺鍍在該基板上,而形成接觸該第一導電層的第 二導電層》 附圖之簡要説明 圖1,2和3是一個部份完成之積體電路的橫剖面圖,有 助於瞭解本發明的具體實施例。 詳細説明 圖1中,代號11代表一面基板,可以是導體,譬如鋁, 或者半導體,譬如矽、摻雜矽、或磊晶矽等。另一方面, 代號11也可代表一層矽化物、一層導電氮化物,或其他 任何導電材料。代號13代表一層介電層,舉例來説,可 以是掺雜或未摻雜的氧化矽。代號1 5代表一個窗孔,或 通孔,形成在介電層13内,而暴露出導體11。 銘薄層17是用平行儀器沉積的β換句話説,濺鍍裝置 —般都具有鋁的平行束。需注意的是,鋁層17非常保形 (c〇nformai),並且一般都具有很小、很均勻容易控制 的晶粒。舉例來説,在一個〇 25微米寬χ 〇 5微米高的通 孔中’膜層17(在平行器的範園内)的厚度可以是5〇至 5〇〇〇埃。其他通孔合適的例子是,05微米寬χ 2〇微米 间’或0.25微米寬X 2.0微米高。類似的銘厚度對這些其 (請先閲1*背面之注意事項再填寫本頁) 裝. 、1Τ
本紙張尺度通用中通圃宏後A 5 个 - - * 公 7 29 A7
經濟部中央標準局員工消費合作社印製 他的通孔也適用。 請參考圖2,第二次鋁沉積是用標準的濺鍍裝置進行的 。沉積膜層19並不需要將鋁束調成平行。因此,避免了 冗長之平行紹沉積的缺點《但是,因爲有了原始成核層 1 7 ’仍然可以得到極高的保形性。一般說來,在前述的 例子中’膜層1 9的厚度可以是2000埃至loooo埃。 一般説來,膜層1 7沉積時溫度可以在室溫到2〇〇 t之間 。沉積膜層19的溫度可以從1〇〇至575。(:。本發明的製程 可以精確地控制晶粒大小,最後制定而成的轉子對電子遷 移有很好的抵抗能力β (膜層17和19會一起制定爲導電轉 子。) 當然’在導體之前與之後也可以形成其他膜層。在圖 3中,在介電層13中具有一個窗口 15。代號11代表任何 導電材料。代號2 1可以代表氮化鈦、高熔點的金屬矽化 物、或者鈦一類的金屬》(如果代號21代表了鈦一類的金 屬,可以與底下的矽基板發生反應,如果代號U代表著 矽基板的話。)代號2 1可以代表著雙層結構,舉例來説, 可以是氮化欽形成在欽上,或者相反(棚化物可用來代 替膜層21中的氮化物。) 代號1 7,如以上的説明,代表著平行沉積所形成的鋁 層。代號1 9代表上面説明的’以傳統濺鍍沉積形成的鋁 層。代號2 1代表覆蓋的導電(或絕緣)層。如果膜層2 1是 導電層,可以是上述的任何導電材料,例如T i,TiN,高 熔點的金屬矽化物,複晶矽等。膜層2 1可以是導電的雙 -6- 本紙張尺度適用中囷國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 - I I 1 >—^1 —^1 Ϊ - · 五、發明説明(4 ) 層結構’例如T i和T i N。 熟習此項技藝的人士可能希望依照通孔15的大小和長 寬比,來修改膜層17和19的厚度。因此,平行鋁沉積對 非平行鋁沉積的比例可以視情況而改變。膜層17和19可 以制定(可能與任何其他覆在上面或位於底下之導電層— 起)形成轉子。舉例來説,如果通孔〗5填滿了鎢所作的閂 柱,覆在其上的轉子可以用非平行沉積鋁覆在平行沉積鋁 的結構來製作。 〇先閑讀背面之注意事項再填寫本頁) 装. 訂 經濟部中央標準局貝工消費合作社印製 本紙張尺度適用中國國家棣準(CNS ) A4規格(210X297公釐)
Claims (1)
- 經濟部中央梯準局負工消費合作社印裝 A8 B8 C8 -------D8 申請專利範圍 •—種積體電路之製法,其步驟係包含: 在一面基板11上形成—膜層,其方法爲: 使一導電粒子的平行束導至該基板上,而形成第—導 電層1 7 ;並且 然後在該基板上以不平行的方式濺鍍導電粒子,而形 成接觸該第一導電層17的第二導電層19。 2.根據申請專利範团第1項之方法,其中該導電材料是銘。 根據申請專利範圍第Η之方法,其步驟另外尚包含—起 制定該第一膜層17和第二膜層19,形成一個導電轉子。 4·根據申請專利範圍第1項之方法,其中該第—導電1?層, 厚度在50至5000埃。 5-根據申請專利範圍第1項之方法,其中該第二導電層19, 厚度在2000埃至10000埃。 6·根據申請專利範圍第2項之方法,其中該基板"是導電的 ,而且該基板部份由一介電層13覆蓋住,該介電層具有 通孔15,暴露出部份的該基板η,而且該第—膜層17和 第二膜層19填滿了該通孔15,而覆蓋住該介電層13。 7.根據申請專利範圍第1項之方法,其步驟另外尚包含在該 基板與該第一導電層17之間,形成一層或一層以上的導 電層2 1。 8·根據申請專利範圍第7項之方法,其中該導電層21是由下 列組合中選擇一項:氮化鈦、高熔點金屬矽化物,和飲 0 9.根據申請專利範圍第7項之方法,其步驟另外尚包含在形 本紙張尺度逋用中國國家標準(CNS > Α4規格(210Χ297公釐) (請先閲讀背面之注意事項再填寫本頁) 裝· 、π 298674 cl D8 々、申請專利範圍 成該第一導電層之前,形成一雙層結構21。 10. 根據申請專利範圍第9項之方法,其中該雙層結構2 1是氮 化鈦覆在鈦上。 11. 根據申請專利範圍第1項之方法,其步驟另外尚包含在該 第二導電層19上,形成至少一層的導電層21。 (請先閲讀背面之注意事項再填寫本頁) 裝· 、1T 經濟部中央標隼局負工消费合作社印製 本紙張尺度適用中國國家標準(CNS ) Α4規格(210 X 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49950995A | 1995-07-07 | 1995-07-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW298674B true TW298674B (zh) | 1997-02-21 |
Family
ID=23985538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085105748A TW298674B (zh) | 1995-07-07 | 1996-05-15 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5798300A (zh) |
EP (1) | EP0752718A3 (zh) |
JP (1) | JPH0936063A (zh) |
KR (1) | KR970008360A (zh) |
TW (1) | TW298674B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6162729A (en) * | 1996-12-12 | 2000-12-19 | Asahi Kasei Kogyo Kabushiki Kaisha | Method of manufacturing multiple aluminum layer in a semiconductor device |
US6365514B1 (en) * | 1997-12-23 | 2002-04-02 | Intel Corporation | Two chamber metal reflow process |
US6440082B1 (en) * | 1999-09-30 | 2002-08-27 | Medtronic Physio-Control Manufacturing Corp. | Method and apparatus for using heart sounds to determine the presence of a pulse |
US6747445B2 (en) | 2001-10-31 | 2004-06-08 | Agere Systems Inc. | Stress migration test structure and method therefor |
US20030207558A1 (en) * | 2002-05-06 | 2003-11-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method forming copper containing semiconductor features to prevent thermally induced defects |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5219788A (en) * | 1991-02-25 | 1993-06-15 | Ibm Corporation | Bilayer metallization cap for photolithography |
DE4200809C2 (de) * | 1991-03-20 | 1996-12-12 | Samsung Electronics Co Ltd | Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement |
CA2061119C (en) * | 1991-04-19 | 1998-02-03 | Pei-Ing P. Lee | Method of depositing conductors in high aspect ratio apertures |
US5171412A (en) * | 1991-08-23 | 1992-12-15 | Applied Materials, Inc. | Material deposition method for integrated circuit manufacturing |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5358616A (en) * | 1993-02-17 | 1994-10-25 | Ward Michael G | Filling of vias and contacts employing an aluminum-germanium alloy |
JP2928057B2 (ja) * | 1993-07-01 | 1999-07-28 | 日本電気株式会社 | 半導体装置の製造方法 |
US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
US5427666A (en) * | 1993-09-09 | 1995-06-27 | Applied Materials, Inc. | Method for in-situ cleaning a Ti target in a Ti + TiN coating process |
US5360995A (en) * | 1993-09-14 | 1994-11-01 | Texas Instruments Incorporated | Buffered capped interconnect for a semiconductor device |
US5470790A (en) * | 1994-10-17 | 1995-11-28 | Intel Corporation | Via hole profile and method of fabrication |
US5604157A (en) * | 1995-05-25 | 1997-02-18 | Industrial Technology Research Institute | Reduced notching of polycide gates using silicon anti reflection layer |
-
1996
- 1996-05-15 TW TW085105748A patent/TW298674B/zh not_active IP Right Cessation
- 1996-06-21 JP JP8161735A patent/JPH0936063A/ja active Pending
- 1996-06-25 EP EP96304668A patent/EP0752718A3/en not_active Withdrawn
- 1996-07-05 KR KR1019960027223A patent/KR970008360A/ko not_active Application Discontinuation
-
1997
- 1997-05-15 US US08/857,079 patent/US5798300A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5798300A (en) | 1998-08-25 |
EP0752718A3 (en) | 1997-03-05 |
KR970008360A (ko) | 1997-02-24 |
EP0752718A2 (en) | 1997-01-08 |
JPH0936063A (ja) | 1997-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0735586B1 (en) | Semi-conductor structures | |
US7262505B2 (en) | Selective electroless-plated copper metallization | |
US4339305A (en) | Planar circuit fabrication by plating and liftoff | |
US6433435B2 (en) | Aluminum contact structure for integrated circuits | |
KR100390952B1 (ko) | 커패시터 제조 방법 | |
KR19980020346A (ko) | 고유전막의 제조방법 및 그를 이용한 캐패시터의 제조방법 | |
JP2003519434A (ja) | 半導体構成素子を製造するための方法 | |
JPS626351B2 (zh) | ||
CN112789724A (zh) | 用于位线电阻降低的覆盖层 | |
WO2002056340A2 (en) | Semiconductor device with fuse, resistor, diffusion barrier or capacitor of a refractory metal-silicon-nitrogen compound | |
JP3113800B2 (ja) | 半導体装置の配線形成方法 | |
US6887353B1 (en) | Tailored barrier layer which provides improved copper interconnect electromigration resistance | |
TW298674B (zh) | ||
JP2002231723A (ja) | 集積回路の製造における銅被覆のためのバリア層 | |
US6395629B1 (en) | Interconnect method and structure for semiconductor devices | |
US5200359A (en) | Method of decreasing contact resistance between a lower elevation aluminum layer and a higher elevation electrically conductive layer | |
TW452959B (en) | A novel hole-filling technique using CVD aluminium and PVD aluminum integration | |
JP2570857B2 (ja) | 半導体装置の製造方法 | |
US5324536A (en) | Method of forming a multilayered structure | |
JPH05326511A (ja) | 半導体素子の製造方法 | |
TW387136B (en) | Method of forming a metal wire of a semiconductor device | |
JP2001319930A (ja) | 半導体装置の製造方法 | |
US4407859A (en) | Planar bubble memory circuit fabrication | |
CA1306551C (en) | Semiconductor device having tungsten plugs | |
KR20060058583A (ko) | 도전성 구조물, 이의 제조 방법, 이를 포함하는 반도체장치 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees | ||
MK4A | Expiration of patent term of an invention patent |