CN103178032A - 使用穿透硅通道的半导体封装方法 - Google Patents

使用穿透硅通道的半导体封装方法 Download PDF

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CN103178032A
CN103178032A CN2013100226268A CN201310022626A CN103178032A CN 103178032 A CN103178032 A CN 103178032A CN 2013100226268 A CN2013100226268 A CN 2013100226268A CN 201310022626 A CN201310022626 A CN 201310022626A CN 103178032 A CN103178032 A CN 103178032A
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contact site
hole
crystal grain
unit
semiconductor element
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CN103178032B (zh
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B·哈巴
G·汉普斯通
M·毛尔高丽特
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

一种微电子单元可包括半导体元件，所述半导体元件具有前表面、靠近前表面的微电子半导体器件、位于前表面的接触部和远离前表面的后表面。半导体元件可具有从后表面延伸穿过半导体元件并且穿过接触部的通孔。介电层可铺衬于通孔。导电层可层叠于通孔中的介电层上。导电层可将接触部与单元接触部导电互连。

Description

使用穿透硅通道的半导体封装方法
本申请是申请日为2008年7月31日、申请号为200880106618.9、发明名称为“使用穿透硅通道的半导体封装方法”的发明专利申请的分案申请。
相关申请的交叉引用
本申请要求2007年7月31日提交的美国临时专利申请No.60/962,752的申请日的权益，该申请的公开内容以引用方式并入本申请。
背景技术
微电子器件通常包括薄板式半导体材料，例如硅或砷化镓，通常称作晶粒或半导体芯片。在晶粒的一个面上制作出有源电路。为了便于电连接至有源电路，晶粒在同一面上设有结合垫。结合垫典型地布置成规则阵列，该阵列或者围绕着晶粒边缘，或者如在许多存储器件中那样布置在晶粒中心。结合垫通常由导电金属制成，例如金或铝，厚度为大约0.5μm。结合垫的尺寸基于器件的类型而变化，但在一侧测量通常为几十至几百微米。
引线结合和倒装贴片互连是用于在晶粒结合垫上形成接触部的两个方案。在引线结合中，晶粒以面向上方的定向附连于基底，并且精细线材通过固态结合方法例如超声焊接或热补偿扩散结合而连接到每个结合垫。在倒装贴片互连中，金属粒被安置在每个结合垫上。然后晶粒被倒置，以使金属粒提供结合垫和基底之间的电路径以及晶粒向基底的机械附连结构。倒装贴片工艺有多种改型，但一种常用配置是金属粒使用焊料并且熔化焊料，作为将其紧固至结合垫和基底的方法。当焊料熔化后，其流动形成截头球体。取决于焊料球的尺寸，可称其为球栅阵列（BGA）界面或微球栅阵列（μBGA）界面。
用作图像传感器的半导体器件通常要求采用面朝上定向，以使得感兴趣图像可以被聚焦（或投射）在有源电路上。出于商业原因，常希望利用BGA或μBGA界面将晶粒连接到基底。
使晶粒前表面的晶粒结合垫与位于晶粒后表面的BGA界面相连的一个措施是提供配线迹线，其从晶粒结合垫延伸经过晶粒的前表面，沿着晶粒的侧面向下并且到达晶粒的后表面。这种类型的引线接触部常被称作"T型接触部"，因为晶粒边缘上的配线迹线与晶粒前表面的配线迹线在它们的汇合处形成"T"形。图2a和2b示出了T型接触部的一个例子。
图2a示出了封装体的单一T型接触部的示意性前视图200，图2b示出了其剖视图250。晶粒被上下倒置，以使得前表面201/251朝向图页底侧，而后表面202/252朝向图页顶侧。前表面的结合垫203/253连接着位于晶粒边缘的配线迹线204/254。配线迹线延续到后表面的岛区205/255，在此结合到焊料球206/256。T型接触部257的形状在剖视图中清楚可见，而侧壁角度207显示在前视图中。图中并未按比例绘制。
一种替代性的图像传感器封装体的措施是使用穿透硅通道（through silicon via，TSV）来将结合垫连接到BGA界面。图3是一种典型TSV的剖视图300。TSV是延伸穿过半导体的厚度的孔（或盲通道），其终止于结合垫304的底侧。通孔的侧面或壁被涂覆金属，以在晶粒前后表面之间形成导电路径。在工程领域称作'波希法（Boschprocess）'的一种深反应离子蚀刻工艺可以用于形成示于图3的TSV。与示于图3的结合垫304相连的接触部常被称作U型的。为了完成晶粒结合垫底侧与施加在TSV的壁上的导电涂层之间的电路，要求在两种金属之间进行固态结合。
图3示出了前表面301和后表面302被倒置的半导体晶粒。孔310延伸穿过晶粒和位于结合垫304下面的介电膜303的厚度而终止于结合垫304。介电材料311和导电涂层312铺衬于孔的壁。铺衬通孔310的介电材料和导电涂层312都延伸到晶粒后表面302上的区域。延伸穿过硅的孔310具有平行的侧面并且垂直于晶粒表面301和302。
发明内容
在本发明的一个实施方式中，微电子单元可包括半导体元件，其具有前表面、靠近前表面的微电子半导体器件、位于前表面的接触部和远离前表面的后表面。半导体元件可具有通孔，其从后表面延伸穿过半导体元件并且穿过接触部。介电层可铺衬于通孔中。导电层可以层叠于通孔中的介电层上。导电层可以将所述接触部与单元接触部（单元触头）导电互连。
在本发明的另一个实施方式中，微电子单元可包括半导体元件，其具有前表面、位于前表面的多个接触部和远离前表面的后表面的。后表面可包括至少一个凹坑。多个通孔可以从凹坑延伸穿过半导体元件并且穿过接触部。通孔中的导电通道可将接触部与所述至少一个凹坑中的导体互连。
在本发明的另一个实施方式中，微电子单元可包括层叠和结合在一起的多个半导体元件。每个半导体元件可具有限定出水平面的前表面、位于前表面的接触部和远离前表面的后表面。半导体元件可沿横贯水平面的竖直方向层叠。多个通孔可以延伸穿过至少一个层叠半导体元件并且穿过所述至少一个半导体元件的接触部。所述多个层叠半导体元件的接触部可以暴露在通孔内。介电层可铺衬于通孔中，并且导电层可以层叠于通孔中的介电层上。导电层可以与微电子单元的单元接触部导电连通。
在本发明的一个实施方式中，微电子单元可包括半导体元件，其具有前表面、位于前表面的接触部、远离前表面的后表面和在前后表面之间延伸的边缘。介电元件可从半导体元件的至少一个所述边缘向外延伸。介电元件可具有前表面和远离前表面的后表面，并且可包括多个连接着接触部的导电垫。介电元件可还包括延伸在前后表面之间并且穿过所述多个导电垫的多个通孔。多个单元接触部可以暴露在微电子单元的外侧。导电特征可以从通孔中的接触部延伸，并且可以与单元接触部导电连通。
在本发明的另一个实施方式中，一种形成暴露在微电子元件后表面的单元接触部的方法可包括形成第一通孔，其从微电子元件的后表面朝向位于微电子元件前表面的元件接触部延伸。绝缘覆层可以形成为至少层叠于第一孔的壁上。第二孔可以被形成为延伸穿过元件接触部。暴露在后表面的单元接触部可以形成，其包括可以层叠于第一孔的壁并且可以层叠于第二孔的壁上并且与元件接触部导电连接的导电材料。
在本发明的另一个实施方式中，一种形成暴露在微电子元件后表面的单元接触部的方法可包括（a）形成通孔，其从微电子元件的后表面延伸穿过位于微电子元件前表面的元件接触部。绝缘层可以暴露在孔的壁上。此外，微电子元件可包括形成暴露在后表面的单元接触部，其包括层叠于绝缘层且与元件接触部导电连接的导电层。
附图说明
图1是半导体晶粒的透视图，所述半导体晶粒在其周边具有晶粒结合垫。
图2a是前（正）视图，图2b是剖视图示出了一种具有T型接触部的传统芯片级封装体。
图3是剖视图，示出了封装体具有暴露结合垫底侧（内表面）的穿透硅通道。
图4a是剖视图，示出了根据本发明一个实施方式的封装体具有穿透硅通道。
图4b是相应的俯视图，进一步示出了图4a所示的封装体。
图4c是剖视图，示出了图4a中的封装体的改型。
图4d-4h是剖视图，示出了根据本发明一个实施方式形成导电通道的过程中的各阶段。
图5a是剖视图，示出了根据本发明一个实施方式的微电子单元包括多个竖直层叠的半导体元件。
图5b是剖视图，示出了根据图5a所示实施方式的改型的微电子单元。
图6a是局部俯视图，示出了根据本发明一个实施方式的包括半导体元件和靠近半导体元件边缘的介电元件的重构晶片的一部分。
图6b是相应的剖视图，示出了根据本发明一个实施方式的延伸在示于图6a的重构晶片的半导体元件和介电元件之间的导电迹线。
图7a-7b是示于图6a-6b的重构晶片的剖视图，进一步示出了延伸穿过介电元件和其上接触部的穿透通道。
图8a-8f是剖视图，示出了根据本发明一个实施方式的形成导电通道的过程中的各阶段。
图9是俯视图，示出了微电子单元，其中与多个结合垫之间的导电互连延伸穿过公共开口。
图10a是剖视图，示出了根据本发明一个实施方式的晶片的一部分和位于两个相邻半导体元件例如晶粒之内和之间的开口。
图10b是相应的俯视图，示出了根据本发明一个实施方式的位于图10a所示晶片一部分中的若干相邻晶粒。
具体实施方式
本公开物中所描述的接触部"暴露在"介电元件的表面，可以是与该表面平齐，相对于该表面凹陷，或从该表面突出，只要接触部能被垂直于该表面的方向朝向该表面移动的理论点触及即可。如描述于例如共同未决的转让给同一受让人的美国专利申请No.10/949,674，该申请的公开内容以引用方式并入本申请，其中穿透导体可以包括元件例如固态金属球、焊料连接部或其它金属元件。此外，接触部可以布置在与穿透导体相同的位置或不同的位置。
图1是一种典型半导体晶粒100的透视图或等角视图，但未按比例绘制。晶粒100包括前表面101、晶粒边缘102和靠近晶粒周边呈阵列的结合垫103。虽然不能直接看到，但隐含的是晶粒的后表面104和埋入前表面101的面层紧邻下方的有源电路105。
下面描述如何在晶粒边缘或TSV的侧壁的配线迹线与晶粒前表面的结合垫之间形成T型接触部。该接触部可用于在晶粒结合垫和晶粒的相对表面上的BGA界面之间完成电路径。如后文所讨论，这种结构还提供了其它互连配置的可能性，包括从晶粒的前表面和两侧接触部开始制造即蚀刻的TSV。本发明的各种实施方式的一些益处包括每单位面积中的高互连密度，制造过程简单，并且穿过晶粒厚度的路径能提供低电阻。
图4a和4b示出了延伸穿过微电子元件400例如硅晶粒的TSV的一个例子。图4a是沿着完全穿过半导体晶粒的整个厚度延伸的通孔410形成的穿透硅通道TSV的剖视图。其包括晶粒的半导体材料区401、结合垫403和位于结合垫403下面的介电膜402。介电材料411例如绝缘覆层铺衬于延伸穿过半导体区401的通孔的壁420上。晶粒半导体区的厚度416可以在几十微米至几百微米的范围内。例如，一些半导体晶片的厚度为800微米。沿着晶粒表面（前表面）的典型结合垫宽度415为100微米，其典型地与结合垫沿着前表面的长度相同或相似。如示于图4b中的俯视图，结合垫403和孔410之间的交叉部可选地完全包含在结合垫403的区域内。
导体，其可以采用示于图4a的导电涂层412的形式，接触通孔410中的结合垫403的边缘并且延伸穿通道410到达后表面404。导电涂层412可以接触暴露于通孔410处的结合垫403的边缘，以形成T型接触部405。铺衬于通孔410的壁420上的介电材料411和导电涂层412或其它导体可选地延伸到晶粒的后表面404上的区域上。
具有竖直侧壁的TSV可能在加工过程中遇到困难。这样的TSV可能具有大的高宽比，其中每个TSV的高度超过TSV的直径，有时比例达到两倍或以上。当直径小时，高宽比大的TSV可能使得气相沉积过程和电沉积过程（例如，电泳涂覆和各种电镀过程）更难控制。
如示于图4c，孔410可具有锥形形状，以使得随着与前表面之间距离的增加，孔的尺寸增大。在这种情况下，随着与晶粒前表面之间距离的增加，孔的直径增大。这种形状提供了径向对称的T型接触部。形成穿过晶粒的中空孔，其具有平行的侧面并且垂直于晶粒表面，可以通过任何非材料选择型加工工艺实现。其例子包括机械钻销，激光蚀刻，和某些湿式蚀刻和活化等离子体化学工艺。在这些方法中，激光蚀刻可能相对容易用于批量制造，因为材料去除速度快，并且该工艺相关的软式工具也会带来益处。
由于用于形成孔的加工过程会穿透结合垫的厚度，因此会导致结合垫的原金属暴露出来。这意味着不需要在加工孔之前以及在孔壁上施加导电涂层之前进行细心清洁。这简化了加工过程。
参看图4d，在一个特定实施方式中，孔410可以被蚀刻在微电子元件的半导体区401中以便暴露位于元件接触部403和半导体区之间的介电层402的表面。绝缘层411（图4e）可以然后被形成，其沿着孔壁420延伸。之后，如示于图4f，孔410可以延展穿过介电层402和元件接触部403。如果绝缘层411在被形成时铺衬于的底部孔（例如显示于图4e），延展孔的过程可以引起孔穿过绝缘层411的一部分（图4f）。在孔延展穿过元件接触部403后，导电材料412可以然后被沉积成与元件接触部403和孔的绝缘层411接触，如示于图4a。
在本发明的另一个实施方式中，孔410可以在单一的步骤中被形成为穿过半导体区401、介电层402和元件接触部403，如可见于图4g。在这种情况下，孔可以利用激光蚀刻或钻销被形成。之后，绝缘层411可以被形成为刚好覆盖半导体区401，如可见于图4h。这样的绝缘层可以利用电泳沉积被形成。接下来，导电材料412可以被沉积为与元件接触部403和孔的绝缘层411接触，如示于图4a。这样的导电层可以利用化学气相沉积、溅镀或物理气相沉积被形成。
在示于图4a-4c的改型实施方式中，导体可以采用充填孔的固态导体的形式，或可以采用只沿着壁的一部分延伸的导电涂层的形式。在另一个改型中，如果晶粒的后表面已经包括了介电层，则介电层铺衬孔不需要延伸到晶粒的后表面上。
示于图4a-4c的类型的TSV的一个优点是，由此产生的互连工艺与相容晶粒的堆叠体，其中在俯视图中看每层晶粒上的结合垫相对正（图5a）。能够横贯多层晶粒的TSV技术使得能够在单一加工步骤中将所有这些结合垫并行地连接起来。所产生的微电子单元包括以叠层的形式结合在一起的竖直对正的晶粒501，每个晶粒具有T型接触部，其将每个晶粒的结合垫502与单元接触部504导电互连，如图5a所示。
图5a示出了上述结构的基本特征，该图是解释性的，而非按比例绘制的。图5a是穿过晶粒500的叠层的剖视图。在每层中，TSV510延伸完全穿过晶粒501和结合垫502，从而与结合垫之间的每个连接部是通过截锥状T型接触部实现的。在完成后，两个附加特征被引入到本图中。它们是密封剂503其包围每个晶粒并将叠层保持在一起，以及BGA界面504，其位于晶粒叠层顶部上。
尽管图5a示出了TSV具有竖直的无锥度壁，但备选实施方式可以是不严格竖直无锥度的，不论其穿过单一晶粒还是晶粒叠层。TSV可以是锥形的以及相对于竖直方向偏斜的。唯一的约束是TSV必须在直径上小于其穿过的结合垫，如示于图4b。这最大化了T型接触部的长度。此外，局部形成在结合垫外侧的TSV有损坏晶粒上的电路的危险。根据现有技术，TSV可以被充填也可以不被充填介电或导电材料，取决于路径期望的电学特性，而对于高功率应用和高频应用来说，电学特性是不同的。
由于TSV横贯硅和结合垫的厚度，因此显然上述结构可以通过从晶粒的前表面和后表面之一加工而制成。实际中，如果其它因素允许，还可以从两侧加工TSV，其中彼此对正的TSV在晶粒的深度范围内会合。在完成TSV后，显然晶粒现在具有位于前表面上的结合垫，其与位于后表面上的一个相同位置的岛区连接。从实现电连接至晶粒的角度看，现在获得的是有效的双面元件，其可以以面向上方或面向下方的定向被安装。此外，假如结合垫是空置特征而没有与晶粒电路相连，则如果其它电学或电子部件被附装于晶粒的一个面上，这种新型的TSV可以用于从晶粒一面向另一面传输电信号，而不会干扰晶粒上的电路。
如前面所指出，TSV的导电元件必须与其穿过的半导体电隔离，否则的话各电路径之间会彼此短路。这是由例如示于图4的介电层411实现的。该介电层需要在加工孔之后施加，但其施加不能延伸至结合垫的将用于形成T型接触部的暴露金属。有多种用于形成介电膜的工艺满足这一要求。其中之一是通过氧化暴露的半导体产生介电层。这适用于半导体是硅的情况，因为硅石（氧化硅）是绝缘体。可以采用这样的化学过程，其能够氧化硅，但留下结合垫的金属保持金属状态。
在上述实施方式的一种改型中，图5b示出了一种层叠微电子单元，其中TSV520延伸穿过第一半导体晶粒511和第一晶粒的结合垫522，TSV将结合垫524暴露于第二晶粒512的前表面。介电材料516可以被暴露在这两个晶粒的对置表面之间。导电层528将第一晶粒的结合垫522、第二晶粒512的垫524和微电子单元的单元接触部544导电互连。在示于图5b的改型实施方式中，不是采用单一第一晶粒511，而是多个第一晶粒可以层叠并且通过TSV中的导电层与第二晶粒512互连。
图6a示出了根据本发明一个实施方式的构建于重构晶片中的晶粒。硅晶粒601至少在四个面（五个面，如果晶粒底侧被覆盖的话）被介电材料602包围。晶粒601上的结合垫603通过配线迹线604连接至介电材料602上的新的结合垫605。沿着一个配线迹线所作的局部剖视图在图6b中以650表示。在该图中，可以看到，配线迹线654通过介电膜652与半导体隔离，作为晶粒制造过程的一个步骤，该介电膜被施加至晶粒。介电膜652不延伸超出晶粒周边，这是因为用于构成重构晶片并且围绕着晶粒的材料本质上也是介电的。
在重构晶片中，每个晶粒的边缘通常由介电材料围绕，该介电材料可以是固化的液体聚合物，例如，介电包覆成型成分，如示于图6a。介电材料可以还覆盖每个晶粒的后表面。介电材料602通常不覆盖晶粒601的前表面，而是与之平齐。制造重构晶片的过程中的一个步骤是施加图案化金属覆层至前表面。该配线迹线的功能是将晶粒结合垫连接至晶粒区域外侧的类似垫。这些新的结合垫是由导电材料形成的，例如层叠于介电材料的金属。对于示于图6a和6b的实施方式，穿透通道将被形成，其延伸穿过包围晶粒的介电材料602。这样，穿透通道将不需要附加的介电膜来将通道上的导电涂层与其穿透的介电材料隔离。当穿透通道全都相对于一个或以上重构晶片或叠层重构晶片形成时，可以特别实现更简单的经济型加工过程。重构晶片可以用于单一晶粒应用以及晶粒叠层。
图7a和7b示出了穿过根据本发明一个实施方式的形成在重构晶片700上的晶粒所作的剖视图。重构晶片更详细描述于2008年7月25日提交的美国专利申请"RECONSTITUTED WAFER STACKPACKAGING WITH AFTER-APPLIED PAD EXTENSIONS"，该申请要求2007年7月27日提交的美国临时申请No.60/962,200的优先权，该美国专利申请的公开内容也以引用方式并入本申请。此外，附加的细节提供于2008年6月20日提交的美国专利申请12/143,743中，其名称为"RECONSTITUTED WAFER LEVEL STACKING"，要求2007年6月20日提交的美国临时申请No.60/936,617的优先权，该美国专利申请也以引用方式并入本申请。
层叠于晶粒面701上的是晶粒结合垫702及其在晶粒上的相关的介电覆层703。晶粒在其侧面和后表面704被重构晶片的介电填充物705包围。穿透通道710（图7b）是台阶式的，并且具有第一通孔711和第二通孔713。第一通孔711具有锥形轮廓以有助于沉积导电涂层712于第一通孔711的壁上。第二结合垫714形成在介电填充层705的下表面715上，第二结合垫714导电连接着晶粒结合垫702。导电涂层712沿着第二结合垫714中第二通孔713的壁延伸。以这种方式，第二通孔713中的通道延伸段实现与第二结合垫714的导电接触。在施加导电涂层至该区域后，在第二结合垫714和通道延伸段713之间产生了截锥T型接触部。
加工穿过半导体晶粒的TSV和加工穿透介电层的穿透通道可以通过各式各样的工艺实现。在一些情况下，组合的工艺可以提供制造益处，例如，等离子体蚀刻可用于加工穿透硅的厚度以产生锥形通道，并且通过激光蚀刻产生延伸穿过结合垫的孔。所产生的结构具有这样的优点，即穿过硅的锥角有助于施加覆层至TSV的壁，而激光蚀刻可以用于产生穿过结合垫的小直径孔。互连可以因此而具有阶变直径结构，如图7中所示的由重构晶片形成的晶粒。这增大了定位许用公差，并且还允许接触到比主孔基部面积小的结合垫。一个附加优点是，同纯竖直通道相比，具有锥角的TSV可以大体上制作成具有低电阻，这时因为同具有平行侧面的通道相比，在给定沉积时间内施加的金属既具有更大表面面积又具有加大的厚度。
使用这样的两步式工艺（图7）来形成TSV，对于这种结构的某些实施方式来说具有益处。如前所述，当TSV延伸穿过半导体晶粒时，通常要求TSV的壁上的金属与半导体基底和其所穿过的任何其它导电结构电隔离，当然，除了其需要连接的结合垫以外。电泳介电膜，例如，通过电泳沉积，是一种有效且可靠的措施来向某个零件的所有表面施加连续且均匀厚度的介电膜，而不论它们是暴露表面还是因为具有大的高宽比而受到阻碍。共同拥有的美国专利申请No.11/590,616（2006年10月31日提交）和11/789,694（2007年4月25日提交）描述了电泳沉积介电层的方法，然后在介电层上形成导电层，例如迹线或其它导电互连。上述申请的公开内容以引用方式并入本申请。
图8a至8f示出了根据本发明一个实施方式的用于形成TSV的工艺。图8f示出了根据本发明一个实施方式的延伸穿过半导体晶粒的TSV的剖视图。
图8a示出了穿过半导体晶粒801的局部剖视图。晶粒的前表面802背对即远离其后表面803，并且包括通过介电膜805与半导体晶粒801隔离的结合垫804。晶粒被显示为具有覆盖其全部特征的保护介电膜806。该膜806是可以存在于某些类型的晶粒封装件中的结构的代表例，例如，可以是任何类型的柔顺层、晶粒贴附膜、晶粒层叠粘合剂或它们之间的组合。
图8b示出了形成从晶粒801的后表面802至晶粒的有源表面延伸的第一孔。对于一种实施方式，第一孔807的底表面安置在介电膜805上。根据一个实施方式，等离子体蚀刻工艺可以用于形成穿透硅厚度的第一孔807。由于等离子体工艺是材料选择型的，第一孔807终止于其上置有结合垫804的介电膜805。第一孔807可具有锥形轮廓，在晶粒后表面803具有最大面积。这样的锥形轮廓可以有助于随后涂覆其表面。作为备选实施方式，第一孔807可以通过湿式蚀刻或机械磨销被形成。
图8c示出了根据一个实施方式在晶粒后表面803上形成绝缘覆层808。绝缘覆层808在第一孔807中形成绝缘层。在一个实施方式中，介电膜例如电泳材料可以施加至晶粒的后表面，例如通过电泳沉积。由于电泳材料的性质，该介电膜将是随形的并且因此而涂覆于第一孔807的壁以及结合垫804下面的介电膜805。作为备选实施方式，其它介电膜例如阻焊剂或光阻剂可以使用。
图8d示出了根据一个实施方式形成延伸穿过绝缘层808、介电膜805和结合垫804的第二孔809。如可见于图8d，第二孔809的直径限定在结合垫804内。
作为一个实施方式，激光蚀刻可以用于穿透绝缘材料808、介电膜805和结合垫804的厚度形成第二孔809。如果结合垫上没有任何东西，则会产生通孔。然而，在这种条件下，晶粒的前表面被介电材料816覆盖。在这种情况下，可以激光烧蚀穿过介电膜和结合垫并且终止于晶粒罩层816的第二孔，从而有效地形成封闭孔或盲孔。作为一个实施方式，晶粒罩层816可以由阻焊剂形成。此外，晶粒罩层816可以用于形成晶粒和玻璃层（未示出）之间的空腔的侧壁。穿透晶粒801和结合垫804的台阶式通孔815由第一孔807和第二孔809形成并且从晶粒后表面803延伸穿过结合垫804。
图8e示出了根据一个实施方式形成导电层810，其可包括金属。导电层810然后被施加至由第一和第二孔形成的通孔815的内侧表面。由于台阶式通孔815穿过结合垫804，因此将形成径向对称的T型接触部811。通过用金属涂覆孔或用金属充填孔，TSV可以被形成。
一种可以用于施加金属覆层的工艺是气相沉积，其例子包括蒸镀和溅镀。这些过程还能将金属沉积到晶粒的后表面。通过将膜图案化，可以产生BGA界面812，其中每个用于焊料球的部位连接着通道和晶粒结合垫，如可见于图8f。通过附加工艺例如电镀，所施加的金属的厚度可以增加大约一个数量级。在另一个实施方式中，通道可以完全由导电材料充填。
之后，介电材料层813可以被沉积而层叠于孔中的导电层810上，如示于图8f。配线迹线的暴露金属可以被覆盖上有机保护介电覆层。常用的材料是阻焊剂。完成了的结构可以然后呈现为图8f中的形态。
图8a至8f示出了根据本发明一个实施方式形成通道，以提供形成于晶粒上的结合垫与BGA界面之间的电接触。孔从晶粒后表面延伸穿过结合垫。此外，第二孔的直径不延伸超出结合垫的周边。作为备选实施方式，第一和第二孔不需要是圆形的。第一孔可以显著加长以形成跨越若干结合垫的刻槽或沟槽。第二孔然后以单体的形式在刻槽或沟槽的基部穿过结合垫。这种实施方式要求涂覆于刻槽或沟槽的侧壁上的金属被图案化，除非希望一排结合垫被并联连接。后面这种情况有时出现于利用结合垫向半导体供应电能时。
晶粒结合垫或重构晶片的介电区上的结合垫的典型尺寸为一侧100μm的范围内。如果是平行侧面的，典型的TSV的直径为大约50μm；如果是锥形的，则基部直径为大约50μm，开口处直径为大约80μm。穿过结合垫的TSV延伸段略小，具有大约20μm的直径。
所有前述例子涉及一个TSV与单一结合垫或结合垫的叠层相交的情况。其中一个原因是通道上的导电涂层是单一金属片材并且因此而提供出一个电路径。现有对通道内部的金属进行图案化的技术。因此，单一通道可以用于与多个结合垫相交和连接。在这种条件下，每个T型接触部将不是完整圆或椭圆，而是弧。这种实施方式显示于图9。
图9提供了根据本发明一个实施方式的安置在四个结合垫上的一个TSV的俯视图。该TSV在其侧壁具有图案化金属，这允许单独的路径形成在每个结合垫上。四个结合垫901、902、903和904暴露于晶粒的前表面。锥形通道905穿过全部四个结合垫的一部分。TSV上的金属在部位906、907、908和909被图案化，以提供通向结合垫的彼此独立的弧形T型接触部。
TSV的形成优选以晶片级工艺实现，因为这允许所有结构被并行加工，从而加工成本被所有产出部件分担。在这种工艺完成后，晶片必须被分离以形成自由的单个晶粒。这可以通过机械锯切实现。备选地，其可以被有机化，从而当半导体被加工以形成TSV的孔时，材料还从切分构造去除，如示于图10a。然后，分离涉及去除或切断晶片前部切分沟槽中的任何材料，或简单地锯断。同切断半导体加上这些层的全部厚度相比，所有上述过程都能更快地完成。尽管用于电连接的TSV优选为圆形的，但显然，为了分离出晶片上的晶粒，沟槽中制作的TSV可以采用各晶粒之间沟槽（切分线）中的凹槽的形式，如示于图10b。晶粒可以在每个角部由半导体材料的小韧带维持连接，因为这样可以维持晶片整个后表面相对于单一电接接触部的电连续性。这种配置可能有助于后面的加工步骤，即施加电泳介电膜。
图10a和10b显示了根据一个实施方式本发明的用于形成TSV的工艺如何能够用于同时从切分沟槽（切分线）去除半导体材料，这有助于随后从晶片分离出单个晶粒。示于图10a的是晶片的两个相邻晶粒1010和1020之间的切分沟槽1001。每个晶粒具有TSV1011/1021孔，其形成为穿过硅到达结合垫1013/1023下面的介电膜1012/1022。通过用于形成将被用于电连接的TSV的同一加工过程，另一TSV1002在切分沟槽中制作出来。通过去除晶片材料的这一部分，晶粒被有效地分离，而不需要随后的切分步骤。图10b是晶片上若干相邻晶粒的后表面的俯视图1050。圆形TSV1051被形成为接触每个结合垫，而作为分离过程的一个步骤，凹槽形TSV1052被同时加工于切分沟槽中。半导体材料韧带1054保留在四个晶粒角部的每个交叉部，以提供晶片表面的电连续性，以便用于后续的电泳工艺。
这里描述的各种实施方式的特征可以相互组合以形成微电子单元，其中微电子单元具有一个所述实施方式中的一些或全部特征和另一所述实施方式中的一个或以上特征。申请人旨在通过这里的公开内容涵盖所有这样的特征组合，即使这种组合并未专门描述。

Claims (14)

1.一种微电子单元，包括：
半导体元件，其具有前表面、与前表面相反的后表面、靠近前表面的微电子半导体器件以及位于前表面的接触部，所述半导体元件具有从所述后表面延伸穿过半导体元件并且穿过接触部的通孔，所述接触部具有背对半导体元件的外表面以及与外表面相反的内表面，所述通孔限定出在接触部中从所述内表面朝向所述外表面延伸的壁表面；
单块式介电层，其铺衬于所述通孔的一些部分且至少部分地层叠于所述内表面；以及
导电元件，其层叠于位于通孔中的介电层，所述导电元件至少接触所述接触部中的所述壁表面，从而将所述接触部与单元接触部导电互连。
2.如权利要求1所述的微电子单元，其中，半导体元件还包括层叠于所述后表面的接触部。
3.如权利要求2所述的微电子单元，其中，所述孔是锥形的，所述孔随着与所述后表面之间距离的增大而缩小。
4.如权利要求3所述的微电子单元，其中，所述孔的壁相对于所述后表面的法线以大约5度或以上的角度定向。
5.如权利要求4所述的微电子单元，其中，所述壁相对于所述后表面的法线以小于或等于大约40度的角度定向。
6.如权利要求1所述的微电子单元，其中，每个孔的总面积被包围在一个所述接触部的面积内。
7.如权利要求1所述的微电子单元，还包括层叠于接触部内表面的介电膜，其中，所述单块式介电层部分地覆盖所述介电膜。
8.一种微电子单元，包括：
层叠和结合在一起的多个半导体元件，每个半导体元件具有限定出水平面的前表面以及与前表面相反的后表面，并且具有位于所述前表面的接触部，所述半导体元件沿横贯所述水平面的竖直方向层叠；
延伸穿过层叠着的至少一个半导体元件并且穿过所述至少一个半导体元件的接触部的多个通孔，所述接触部具有背对半导体元件的外表面以及与外表面相反的内表面，所述通孔限定出在接触部中从所述内表面朝向所述外表面延伸的壁表面，所述多个层叠半导体元件的接触部暴露于所述通孔中；
单块式介电层，其铺衬于所述通孔的一些部分且至少部分地层叠于所述内表面；以及
导电层，其层叠于位于通孔中的介电层，所述导电层至少接触所述接触部中的所述壁表面，从而与微电子单元的单元接触部导电连通。
9.如权利要求8所述的微电子单元，其中，所述单元接触部暴露于微电子单元的外侧。
10.如权利要求8所述的微电子单元，其中，所述通孔延伸穿过多个层叠半导体元件的接触部。
11.如权利要求8所述的微电子单元，其中，所述通孔不完全延伸穿过全部层叠半导体元件。
12.如权利要求8所述的微电子单元，其中，至少一个层叠半导体元件的前表面面向下方，并且所述单元接触部暴露于单元的面向上方的顶表面。
13.如权利要求8所述的微电子单元，其中，至少一个层叠半导体元件的前表面面向上方，并且所述单元接触部暴露于单元的面向上方的顶表面。
14.如权利要求8所述的微电子单元，还包括层叠于接触部内表面的介电膜，其中，所述单块式介电层部分地覆盖所述介电膜。
CN201310022626.8A 2007-07-31 2008-07-31 使用穿透硅通道的半导体封装方法 Active CN103178032B (zh)

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Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1515364B1 (en) 2003-09-15 2016-04-13 Nuvotronics, LLC Device package and methods for the fabrication and testing thereof
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
EP1962344B1 (en) * 2007-02-25 2012-03-28 Samsung Electronics Co., Ltd Electronic device packages and methods of formation
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
EP2186134A2 (en) 2007-07-27 2010-05-19 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
KR101538648B1 (ko) * 2007-07-31 2015-07-22 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
JP2009181981A (ja) * 2008-01-29 2009-08-13 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
EP2308087B1 (en) 2008-06-16 2020-08-12 Tessera, Inc. Stacking of wafer-level chip scale packages having edge contacts
SG10201505279RA (en) * 2008-07-18 2015-10-29 Utac Headquarters Pte Ltd Packaging structural member
WO2010104610A2 (en) * 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
WO2011044393A1 (en) 2009-10-07 2011-04-14 Tessera North America, Inc. Wafer-scale emitter package including thermal vias
US8455356B2 (en) * 2010-01-21 2013-06-04 International Business Machines Corporation Integrated void fill for through silicon via
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
CN102376629B (zh) * 2010-08-17 2013-07-03 中国科学院上海微系统与信息技术研究所 一种借助悬架光刻胶实现硅通孔互连的方法
US8685793B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Chip assembly having via interconnects joined by plating
US8686565B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Stacked chip assembly having vertical vias
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8748206B2 (en) 2010-11-23 2014-06-10 Honeywell International Inc. Systems and methods for a four-layer chip-scale MEMS device
US9171964B2 (en) 2010-11-23 2015-10-27 Honeywell International Inc. Systems and methods for a three-layer chip-scale MEMS device
CN102479765B (zh) * 2010-11-24 2016-08-24 日月光半导体制造股份有限公司 具有半导体组件的封装结构
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8975751B2 (en) * 2011-04-22 2015-03-10 Tessera, Inc. Vias in porous substrates
US8987140B2 (en) 2011-04-25 2015-03-24 Applied Materials, Inc. Methods for etching through-silicon vias with tunable profile angles
CN102774805B (zh) * 2011-05-13 2015-10-28 精材科技股份有限公司 晶片封装体及其形成方法
JP5598420B2 (ja) * 2011-05-24 2014-10-01 株式会社デンソー 電子デバイスの製造方法
US8692118B2 (en) 2011-06-24 2014-04-08 Tessera, Inc. Reliable wire structure and method
US8728934B2 (en) 2011-06-24 2014-05-20 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US9125333B2 (en) 2011-07-15 2015-09-01 Tessera, Inc. Electrical barrier layers
CN102509718B (zh) * 2011-12-15 2014-02-12 中国科学院上海微系统与信息技术研究所 GaAs CCD图形传感器圆片级芯片尺寸封装工艺
US8928114B2 (en) * 2012-01-17 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-assembly via modules and methods for forming the same
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US8865544B2 (en) 2012-07-11 2014-10-21 Micron Technology, Inc. Methods of forming capacitors
US9646899B2 (en) 2012-09-13 2017-05-09 Micron Technology, Inc. Interconnect assemblies with probed bond pads
US9343497B2 (en) * 2012-09-20 2016-05-17 Semiconductor Components Industries, Llc Imagers with stacked integrated circuit dies
US9312226B2 (en) * 2012-12-14 2016-04-12 Infineon Technologies Ag Semiconductor device having an identification mark
US9070741B2 (en) * 2012-12-17 2015-06-30 Infineon Technologies Austria Ag Method of manufacturing a semiconductor device and a semiconductor workpiece
US9070667B2 (en) * 2013-02-27 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Peripheral electrical connection of package on package
JP6337419B2 (ja) * 2013-04-18 2018-06-06 大日本印刷株式会社 レジストパターンの形成方法及びラミネート構造体
US9735134B2 (en) * 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
JP6436738B2 (ja) * 2014-11-19 2018-12-12 キヤノン株式会社 プリント配線板、半導体装置及びプリント回路板
US10773049B2 (en) 2016-06-21 2020-09-15 Ventec Life Systems, Inc. Cough-assist systems with humidifier bypass
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
US10957626B2 (en) 2017-12-19 2021-03-23 Thermo Electron Scientific Instruments Llc Sensor device with carbon nanotube sensor positioned on first and second substrates
US11171117B2 (en) * 2018-06-12 2021-11-09 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US10923397B2 (en) 2018-11-29 2021-02-16 Globalfoundries Inc. Through-substrate via structures in semiconductor devices
WO2020108603A1 (en) 2018-11-30 2020-06-04 Changxin Memory Technologies, Inc. Method for fabricating semiconductor interconnect structure and semiconductor structure thereof
EP3671823A1 (en) * 2018-12-21 2020-06-24 ams AG Semiconductor device with through-substrate via and method of manufacturing a semiconductor device with through-substrate via
CN117153780B (zh) * 2023-10-26 2024-01-30 甬矽电子(宁波)股份有限公司 硅穿孔结构的制备方法和硅穿孔结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481133A (en) * 1994-03-21 1996-01-02 United Microelectronics Corporation Three-dimensional multichip package
US20020127839A1 (en) * 2001-03-07 2002-09-12 Seiko Epson Corporation Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
US20040016942A1 (en) * 2002-04-24 2004-01-29 Seiko Epson Corporation Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus

Family Cites Families (238)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
JPS60160645A (ja) 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
NL8403613A (nl) 1984-11-28 1986-06-16 Philips Nv Elektronenbundelinrichting en halfgeleiderinrichting voor een dergelijke inrichting.
US4765864A (en) 1987-07-15 1988-08-23 Sri International Etching method for producing an electrochemical cell in a crystalline substrate
EP0316799B1 (en) 1987-11-13 1994-07-27 Nissan Motor Co., Ltd. Semiconductor device
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5322816A (en) 1993-01-19 1994-06-21 Hughes Aircraft Company Method for forming deep conductive feedthroughs
IL110261A0 (en) 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
GB2292015B (en) 1994-07-29 1998-07-22 Plessey Semiconductors Ltd Trimmable inductor structure
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US5703408A (en) 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US6284563B1 (en) 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5686762A (en) 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
TW343210B (en) 1996-01-12 1998-10-21 Matsushita Electric Works Ltd Process for impregnating a substrate, impregnated substrate and products thereof
US5808874A (en) 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US5700735A (en) 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
JP3620936B2 (ja) 1996-10-11 2005-02-16 浜松ホトニクス株式会社 裏面照射型受光デバイスおよびその製造方法
EP2270845A3 (en) * 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6143396A (en) 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6573609B2 (en) 1997-11-25 2003-06-03 Tessera, Inc. Microelectronic component with rigid interposer
EP0926723B1 (en) 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
WO1999038204A1 (fr) 1998-01-23 1999-07-29 Rohm Co., Ltd. Interconnexion damasquinee et dispositif a semi-conducteur
US6982475B1 (en) 1998-03-20 2006-01-03 Mcsp, Llc Hermetic wafer scale integrated circuit structure
US5986343A (en) 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US6492201B1 (en) 1998-07-10 2002-12-10 Tessera, Inc. Forming microelectronic connection components by electrophoretic deposition
US6103552A (en) 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6037668A (en) 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
JP2000195896A (ja) 1998-12-25 2000-07-14 Nec Corp 半導体装置
US6181016B1 (en) 1999-06-08 2001-01-30 Winbond Electronics Corp Bond-pad with a single anchoring structure
US6368410B1 (en) 1999-06-28 2002-04-09 General Electric Company Semiconductor processing article
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
JP4139533B2 (ja) 1999-09-10 2008-08-27 大日本印刷株式会社 半導体装置とその製造方法
US6277669B1 (en) 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
JP2001127243A (ja) 1999-10-26 2001-05-11 Sharp Corp 積層半導体装置
JP3399456B2 (ja) 1999-10-29 2003-04-21 株式会社日立製作所 半導体装置およびその製造方法
US6507113B1 (en) 1999-11-19 2003-01-14 General Electric Company Electronic interface structures and methods of fabrication
JP3626058B2 (ja) 2000-01-25 2005-03-02 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP3684978B2 (ja) 2000-02-03 2005-08-17 セイコーエプソン株式会社 半導体装置およびその製造方法ならびに電子機器
US6498387B1 (en) 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same
US6586955B2 (en) 2000-03-13 2003-07-01 Tessera, Inc. Methods and structures for electronic probing arrays
JP3879816B2 (ja) 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
US6472247B1 (en) 2000-06-26 2002-10-29 Ricoh Company, Ltd. Solid-state imaging device and method of production of the same
US6399892B1 (en) 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
JP3433193B2 (ja) 2000-10-23 2003-08-04 松下電器産業株式会社 半導体チップおよびその製造方法
US6693358B2 (en) 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
EP1207015A3 (en) 2000-11-17 2003-07-30 Keltech Engineering, Inc. Raised island abrasive, method of use and lapping apparatus
JP2002162212A (ja) * 2000-11-24 2002-06-07 Foundation Of River & Basin Integrated Communications Japan 堤体ひずみ計測センサ
US20020070443A1 (en) * 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US20020098620A1 (en) 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
KR100352236B1 (ko) 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
KR100869013B1 (ko) 2001-02-08 2008-11-17 가부시키가이샤 히타치세이사쿠쇼 반도체 집적회로장치 및 그 제조방법
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6498381B2 (en) 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
JP2002359347A (ja) 2001-03-28 2002-12-13 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2002373957A (ja) * 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003020404A (ja) 2001-07-10 2003-01-24 Hitachi Ltd 耐熱性低弾性率材およびそれを用いた装置
US6531384B1 (en) 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
US20030059976A1 (en) 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
JP2003124393A (ja) 2001-10-17 2003-04-25 Hitachi Ltd 半導体装置およびその製造方法
US6727576B2 (en) 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
US20040051173A1 (en) 2001-12-10 2004-03-18 Koh Philip Joseph High frequency interconnect system using micromachined plugs and sockets
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW517361B (en) 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6743660B2 (en) 2002-01-12 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Method of making a wafer level chip scale package
US6908784B1 (en) 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
TW200304227A (en) 2002-03-11 2003-09-16 Sanyo Electric Co Top gate type thin film transistor
JP2003282791A (ja) 2002-03-20 2003-10-03 Fujitsu Ltd 接触型センサ内蔵半導体装置及びその製造方法
ATE493760T1 (de) 2002-05-20 2011-01-15 Imagerlabs Inc Bilden einer integrierten mehrsegmentschaltung mit isolierten substraten
JP2004014657A (ja) * 2002-06-05 2004-01-15 Toshiba Corp 半導体チップおよびその製造方法、ならびに三次元積層半導体装置
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US6716737B2 (en) 2002-07-29 2004-04-06 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
US7030010B2 (en) * 2002-08-29 2006-04-18 Micron Technology, Inc. Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US7329563B2 (en) 2002-09-03 2008-02-12 Industrial Technology Research Institute Method for fabrication of wafer level package incorporating dual compliant layers
KR20040025123A (ko) * 2002-09-18 2004-03-24 현대자동차주식회사 자동차용 리어 스포일러
AU2003268667A1 (en) * 2002-09-24 2004-04-19 Hamamatsu Photonics K.K. Photodiode array and method for manufacturing same
JP4440554B2 (ja) * 2002-09-24 2010-03-24 浜松ホトニクス株式会社 半導体装置
JP2004128063A (ja) 2002-09-30 2004-04-22 Toshiba Corp 半導体装置及びその製造方法
US20040104454A1 (en) 2002-10-10 2004-06-03 Rohm Co., Ltd. Semiconductor device and method of producing the same
TW569395B (en) 2002-10-30 2004-01-01 Intelligent Sources Dev Corp Method of forming a stacked-gate cell structure and its NAND-type flash memory array
US20050012225A1 (en) 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
JP3918935B2 (ja) 2002-12-20 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP2004356618A (ja) 2003-03-19 2004-12-16 Ngk Spark Plug Co Ltd 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体、中継基板の製造方法
SG137651A1 (en) 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP3680839B2 (ja) 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
EP1519410A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
JP4373695B2 (ja) 2003-04-16 2009-11-25 浜松ホトニクス株式会社 裏面照射型光検出装置の製造方法
DE10319538B4 (de) 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
EP1482553A3 (en) 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
US6927156B2 (en) 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
JP3646720B2 (ja) 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
EP1639634B1 (en) 2003-06-20 2009-04-01 Nxp B.V. Electronic device, assembly and methods of manufacturing an electronic device
JP2005026405A (ja) 2003-07-01 2005-01-27 Sharp Corp 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置
JP2005045073A (ja) 2003-07-23 2005-02-17 Hamamatsu Photonics Kk 裏面入射型光検出素子
JP4499386B2 (ja) 2003-07-29 2010-07-07 浜松ホトニクス株式会社 裏面入射型光検出素子の製造方法
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2005101268A (ja) 2003-09-25 2005-04-14 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050095835A1 (en) 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
GB2406720B (en) 2003-09-30 2006-09-13 Agere Systems Inc An inductor formed in an integrated circuit
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
TWI259564B (en) 2003-10-15 2006-08-01 Infineon Technologies Ag Wafer level packages for chips with sawn edge protection
TWI234244B (en) 2003-12-26 2005-06-11 Intelligent Sources Dev Corp Paired stack-gate flash cell structure and its contactless NAND-type flash memory arrays
US20050156330A1 (en) 2004-01-21 2005-07-21 Harris James M. Through-wafer contact to bonding pad
JP4198072B2 (ja) 2004-01-23 2008-12-17 シャープ株式会社 半導体装置、光学装置用モジュール及び半導体装置の製造方法
JP2005216921A (ja) 2004-01-27 2005-08-11 Hitachi Maxell Ltd 半導体装置製造用のメタルマスク及び半導体装置の製造方法
US7026175B2 (en) 2004-03-29 2006-04-11 Applied Materials, Inc. High throughput measurement of via defects in interconnects
US7368695B2 (en) 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
US20050248002A1 (en) 2004-05-07 2005-11-10 Michael Newman Fill for large volume vias
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
JP4343044B2 (ja) 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP2006019455A (ja) 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
KR100605314B1 (ko) 2004-07-22 2006-07-28 삼성전자주식회사 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법
US7750487B2 (en) 2004-08-11 2010-07-06 Intel Corporation Metal-metal bonding of compliant interconnect
US7598167B2 (en) 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
US7378342B2 (en) 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
KR100604049B1 (ko) 2004-09-01 2006-07-24 동부일렉트로닉스 주식회사 반도체 칩 패키지 및 그 제조방법
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
CN100481402C (zh) 2004-09-10 2009-04-22 株式会社东芝 半导体器件和半导体器件的制造方法
TWI288448B (en) 2004-09-10 2007-10-11 Toshiba Corp Semiconductor device and method of manufacturing the same
JP4139803B2 (ja) 2004-09-28 2008-08-27 シャープ株式会社 半導体装置の製造方法
JP4246132B2 (ja) 2004-10-04 2009-04-02 シャープ株式会社 半導体装置およびその製造方法
TWI273682B (en) 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
US7819119B2 (en) 2004-10-08 2010-10-26 Ric Investments, Llc User interface having a pivotable coupling
US7081408B2 (en) 2004-10-28 2006-07-25 Intel Corporation Method of creating a tapered via using a receding mask and resulting structure
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US20060278997A1 (en) 2004-12-01 2006-12-14 Tessera, Inc. Soldered assemblies and methods of making the same
JP4795677B2 (ja) 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
JP4290158B2 (ja) 2004-12-20 2009-07-01 三洋電機株式会社 半導体装置
KR20060087273A (ko) 2005-01-28 2006-08-02 삼성전기주식회사 반도체 패키지및 그 제조방법
US7675153B2 (en) 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7538032B2 (en) 2005-06-23 2009-05-26 Teledyne Scientific & Imaging, Llc Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI267181B (en) * 2005-03-18 2006-11-21 Silicon Integrated Sys Corp Structure and assembly method of IC packaging
US20060264029A1 (en) 2005-05-23 2006-11-23 Intel Corporation Low inductance via structures
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
JP4694305B2 (ja) * 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
US20070049470A1 (en) 2005-08-29 2007-03-01 Johnson Health Tech Co., Ltd. Rapid circuit training machine with dual resistance
US7772115B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
US20070052050A1 (en) 2005-09-07 2007-03-08 Bart Dierickx Backside thinned image sensor with integrated lens stack
JP2007157844A (ja) * 2005-12-01 2007-06-21 Sharp Corp 半導体装置、および半導体装置の製造方法
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US7456479B2 (en) 2005-12-15 2008-11-25 United Microelectronics Corp. Method for fabricating a probing pad of an integrated circuit chip
JP4826248B2 (ja) 2005-12-19 2011-11-30 Ｔｄｋ株式会社 Ｉｃ内蔵基板の製造方法
KR20070081661A (ko) 2006-02-13 2007-08-17 삼성전자주식회사 액정 표시 장치의 제조 방법 및 그에 의해 제조된 액정표시 장치
KR100714310B1 (ko) 2006-02-23 2007-05-02 삼성전자주식회사 변압기 또는 안테나를 구비하는 반도체 패키지들
US20080029879A1 (en) 2006-03-01 2008-02-07 Tessera, Inc. Structure and method of making lidded chips
JP4659660B2 (ja) 2006-03-31 2011-03-30 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2007311676A (ja) 2006-05-22 2007-11-29 Sony Corp 半導体装置とその製造方法
KR100837269B1 (ko) * 2006-05-22 2008-06-11 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조 방법
JP4950559B2 (ja) 2006-05-25 2012-06-13 パナソニック株式会社 スルーホール電極の形成方法
US7605019B2 (en) 2006-07-07 2009-10-20 Qimonda Ag Semiconductor device with stacked chips and method for manufacturing thereof
KR100750741B1 (ko) 2006-09-15 2007-08-22 삼성전기주식회사 캡 웨이퍼, 이를 구비한 반도체 칩, 및 그 제조방법
US7531445B2 (en) 2006-09-26 2009-05-12 Hymite A/S Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US20080079779A1 (en) 2006-09-28 2008-04-03 Robert Lee Cornell Method for Improving Thermal Conductivity in Micro-Fluid Ejection Heads
JP2008091632A (ja) 2006-10-02 2008-04-17 Manabu Bonshihara 半導体装置の外部回路接続部の構造及びその形成方法
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7719121B2 (en) 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7935568B2 (en) 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7807508B2 (en) 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
KR100830581B1 (ko) 2006-11-06 2008-05-22 삼성전자주식회사 관통전극을 구비한 반도체 소자 및 그 형성방법
US7781781B2 (en) 2006-11-17 2010-08-24 International Business Machines Corporation CMOS imager array with recessed dielectric
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US20080136038A1 (en) 2006-12-06 2008-06-12 Sergey Savastiouk Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate
FR2911006A1 (fr) 2007-01-03 2008-07-04 St Microelectronics Sa Puce de circuit electronique integre comprenant une inductance
JP2008177249A (ja) 2007-01-16 2008-07-31 Sharp Corp 半導体集積回路のボンディングパッド、その製造方法、半導体集積回路、並びに電子機器
US7518226B2 (en) 2007-02-06 2009-04-14 Stats Chippac Ltd. Integrated circuit packaging system with interposer
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
JP4380718B2 (ja) * 2007-03-15 2009-12-09 ソニー株式会社 半導体装置の製造方法
KR100845006B1 (ko) 2007-03-19 2008-07-09 삼성전자주식회사 적층 칩 패키지 및 그 제조 방법
JP2008258258A (ja) 2007-04-02 2008-10-23 Sanyo Electric Co Ltd 半導体装置
US7977155B2 (en) 2007-05-04 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level flip-chip assembly methods
US20080284041A1 (en) 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5302522B2 (ja) 2007-07-02 2013-10-02 スパンション エルエルシー 半導体装置及びその製造方法
US7767497B2 (en) 2007-07-12 2010-08-03 Tessera, Inc. Microelectronic package element and method of fabricating thereof
EP2186134A2 (en) 2007-07-27 2010-05-19 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US7932179B2 (en) 2007-07-27 2011-04-26 Micron Technology, Inc. Method for fabricating semiconductor device having backside redistribution layers
KR101538648B1 (ko) 2007-07-31 2015-07-22 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
KR101387701B1 (ko) 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US7902069B2 (en) 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
WO2009023462A1 (en) 2007-08-10 2009-02-19 Spansion Llc Semiconductor device and method for manufacturing thereof
KR100905784B1 (ko) 2007-08-16 2009-07-02 주식회사 하이닉스반도체 반도체 패키지용 관통 전극 및 이를 갖는 반도체 패키지
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
JP2009088201A (ja) 2007-09-28 2009-04-23 Nec Electronics Corp 半導体装置
JP2009129953A (ja) 2007-11-20 2009-06-11 Hitachi Ltd 半導体装置
US20090127667A1 (en) 2007-11-21 2009-05-21 Powertech Technology Inc. Semiconductor chip device having through-silicon-via (TSV) and its fabrication method
US7446036B1 (en) 2007-12-18 2008-11-04 International Business Machines Corporation Gap free anchored conductor and dielectric structure and method for fabrication thereof
WO2009104668A1 (ja) 2008-02-21 2009-08-27 日本電気株式会社 配線基板及び半導体装置
US20090212381A1 (en) 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US7791174B2 (en) 2008-03-07 2010-09-07 Advanced Inquiry Systems, Inc. Wafer translator having a silicon core isolated from signal paths by a ground plane
US8049310B2 (en) 2008-04-01 2011-11-01 Qimonda Ag Semiconductor device with an interconnect element and method for manufacture
US7842548B2 (en) 2008-04-22 2010-11-30 Taiwan Semconductor Manufacturing Co., Ltd. Fixture for P-through silicon via assembly
US7838967B2 (en) 2008-04-24 2010-11-23 Powertech Technology Inc. Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
US20090267183A1 (en) 2008-04-28 2009-10-29 Research Triangle Institute Through-substrate power-conducting via with embedded capacitance
CN101582434B (zh) 2008-05-13 2011-02-02 鸿富锦精密工业（深圳）有限公司 影像感测器封装结构及其制造方法及相机模组
US7939449B2 (en) 2008-06-03 2011-05-10 Micron Technology, Inc. Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension back side ends
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
JP5183340B2 (ja) 2008-07-23 2013-04-17 日本電波工業株式会社 表面実装型の発振器およびこの発振器を搭載した電子機器
KR20100020718A (ko) 2008-08-13 2010-02-23 삼성전자주식회사 반도체 칩, 그 스택 구조 및 이들의 제조 방법
US20100117242A1 (en) 2008-11-10 2010-05-13 Miller Gary L Technique for packaging multiple integrated circuits
US7906404B2 (en) 2008-11-21 2011-03-15 Teledyne Scientific & Imaging, Llc Power distribution for CMOS circuits using in-substrate decoupling capacitors and back side metal layers
US7939926B2 (en) 2008-12-12 2011-05-10 Qualcomm Incorporated Via first plus via last technique for IC interconnects
US20100159699A1 (en) 2008-12-19 2010-06-24 Yoshimi Takahashi Sandblast etching for through semiconductor vias
JP5308145B2 (ja) 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
TWI366890B (en) 2008-12-31 2012-06-21 Ind Tech Res Inst Method of manufacturing through-silicon-via and through-silicon-via structure
KR20100087566A (ko) 2009-01-28 2010-08-05 삼성전자주식회사 반도체 소자 패키지의 형성방법
US8158515B2 (en) 2009-02-03 2012-04-17 International Business Machines Corporation Method of making 3D integrated circuits
US7998860B2 (en) 2009-03-12 2011-08-16 Micron Technology, Inc. Method for fabricating semiconductor components using maskless back side alignment to conductive vias
WO2010104610A2 (en) 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
TWI466258B (zh) 2009-04-10 2014-12-21 Nanya Technology Corp 電性通透連接及其形成方法
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
JP5715334B2 (ja) 2009-10-15 2015-05-07 ルネサスエレクトロニクス株式会社 半導体装置
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8299608B2 (en) 2010-07-08 2012-10-30 International Business Machines Corporation Enhanced thermal management of 3-D stacked die packaging
US8697569B2 (en) 2010-07-23 2014-04-15 Tessera, Inc. Non-lithographic formation of three-dimensional conductive elements
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8686565B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Stacked chip assembly having vertical vias
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8421193B2 (en) 2010-11-18 2013-04-16 Nanya Technology Corporation Integrated circuit device having through via and method for preparing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481133A (en) * 1994-03-21 1996-01-02 United Microelectronics Corporation Three-dimensional multichip package
US20020127839A1 (en) * 2001-03-07 2002-09-12 Seiko Epson Corporation Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
US20040016942A1 (en) * 2002-04-24 2004-01-29 Seiko Epson Corporation Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus

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