CN101802990B - 使用穿透硅通道的半导体封装方法 - Google Patents

使用穿透硅通道的半导体封装方法 Download PDF

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CN101802990B
CN101802990B CN2008801066189A CN200880106618A CN101802990B CN 101802990 B CN101802990 B CN 101802990B CN 2008801066189 A CN2008801066189 A CN 2008801066189A CN 200880106618 A CN200880106618 A CN 200880106618A CN 101802990 B CN101802990 B CN 101802990B
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contact site
hole
microelectronic
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rear surface
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CN101802990A (zh
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B·哈巴
G·汉普斯通
M·毛尔高丽特
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Tessera LLC
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DigitalOptics Corp Europe Ltd
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Abstract

一种微电子单元(400)可包括半导体元件(401),所述半导体元件具有前表面、靠近前表面的微电子半导体器件、位于前表面的接触部(403)和远离前表面的后表面。半导体元件(401)可具有从后表面延伸穿过半导体元件(401)并且穿过接触部(403)的通孔(410)。介电层(411)可铺衬于通孔(410)。导电层(412)可层叠于通孔(410)中的介电层(411)上。导电层(412)可将接触部(403)与单元接触部导电互连。

Description

使用穿透硅通道的半导体封装方法
相关申请的交叉引用
本申请要求2007年7月31日提交的美国临时专利申请No.60/962,752的申请日的权益,该申请的公开内容以引用方式并入本申请。
背景技术
微电子器件通常包括薄板式半导体材料,例如硅或砷化镓,通常称作晶粒或半导体芯片。在晶粒的一个面上制作出有源电路。为了便于电连接至有源电路,晶粒在同一面上设有结合垫。结合垫典型地布置成规则阵列,该阵列或者围绕着晶粒边缘,或者如在许多存储器件中那样布置在晶粒中心。结合垫通常由导电金属制成,例如金或铝,厚度为大约0.5μm。结合垫的尺寸基于器件的类型而变化,但在一侧测量通常为几十至几百微米。
引线结合和倒装贴片互连是用于在晶粒结合垫上形成接触部的两个方案。在引线结合中,晶粒以面向上方的定向附连于基底,并且精细线材通过固态结合方法例如超声焊接或热补偿扩散结合而连接到每个结合垫。在倒装贴片互连中,金属粒被安置在每个结合垫上。然后晶粒被倒置,以使金属粒提供结合垫和基底之间的电路径以及晶粒向基底的机械附连结构。倒装贴片工艺有多种改型,但一种常用配置是金属粒使用焊料并且熔化焊料,作为将其紧固至结合垫和基底的方法。当焊料熔化后,其流动形成截头球体。取决于焊料球的尺寸,可称其为球栅阵列(BGA)界面或微球栅阵列(μBGA)界面。
用作图像传感器的半导体器件通常要求采用面朝上定向,以使得感兴趣图像可以被聚焦(或投射)在有源电路上。出于商业原因,常希望利用BGA或μBGA界面将晶粒连接到基底。
使晶粒前表面的晶粒结合垫与位于晶粒后表面的BGA界面相连的一个措施是提供配线迹线,其从晶粒结合垫延伸经过晶粒的前表面,沿着晶粒的侧面向下并且到达晶粒的后表面。这种类型的引线接触部常被称作″T型接触部″,因为晶粒边缘上的配线迹线与晶粒前表面的配线迹线在它们的汇合处形成″T″形。图2a和2b示出了T型接触部的一个例子。
图2a示出了封装体的单一T型接触部的示意性前视图200,图2b示出了其剖视图250。晶粒被上下倒置,以使得前表面201/251朝向图页底侧,而后表面202/252朝向图页顶侧。前表面的结合垫203/253连接着位于晶粒边缘的配线迹线204/254。配线迹线延续到后表面的岛区205/255,在此结合到焊料球206/256。T型接触部257的形状在剖视图中清楚可见,而侧壁角度207显示在前视图中。图中并未按比例绘制。
一种替代性的图像传感器封装体的措施是使用穿透硅通道(through silicon via,TSV)来将结合垫连接到BGA界面。图3是一种典型TSV的剖视图300。TSV是延伸穿过半导体的厚度的孔(或盲通道),其终止于结合垫304的底侧。通孔的侧面或壁被涂覆金属,以在晶粒前后表面之间形成导电路径。在工程领域称作′波希法(Boschprocess)′的一种深反应离子蚀刻工艺可以用于形成示于图3的TSV。与示于图3的结合垫304相连的接触部常被称作U型的。为了完成晶粒结合垫底侧与施加在TSV的壁上的导电涂层之间的电路,要求在两种金属之间进行固态结合。
图3示出了前表面301和后表面302被倒置的半导体晶粒。孔310延伸穿过晶粒和位于结合垫304下面的介电膜303的厚度而终止于结合垫304。介电材料311和导电涂层312铺衬于孔的壁。铺衬通孔310的介电材料和导电涂层312都延伸到晶粒后表面302上的区域。延伸穿过硅的孔310具有平行的侧面并且垂直于晶粒表面301和302。
发明内容
在本发明的一个实施方式中,微电子单元可包括半导体元件,其具有前表面、靠近前表面的微电子半导体器件、位于前表面的接触部和远离前表面的后表面。半导体元件可具有通孔,其从后表面延伸穿过半导体元件并且穿过接触部。介电层可铺衬于通孔中。导电层可以层叠于通孔中的介电层上。导电层可以将所述接触部与单元接触部(单元触头)导电互连。
在本发明的另一个实施方式中,微电子单元可包括半导体元件,其具有前表面、位于前表面的多个接触部和远离前表面的后表面的。后表面可包括至少一个凹坑。多个通孔可以从凹坑延伸穿过半导体元件并且穿过接触部。通孔中的导电通道可将接触部与所述至少一个凹坑中的导体互连。
在本发明的另一个实施方式中,微电子单元可包括层叠和结合在一起的多个半导体元件。每个半导体元件可具有限定出水平面的前表面、位于前表面的接触部和远离前表面的后表面。半导体元件可沿横贯水平面的竖直方向层叠。多个通孔可以延伸穿过至少一个层叠半导体元件并且穿过所述至少一个半导体元件的接触部。所述多个层叠半导体元件的接触部可以暴露在通孔内。介电层可铺衬于通孔中,并且导电层可以层叠于通孔中的介电层上。导电层可以与微电子单元的单元接触部导电连通。
在本发明的一个实施方式中,微电子单元可包括半导体元件,其具有前表面、位于前表面的接触部、远离前表面的后表面和在前后表面之间延伸的边缘。介电元件可从半导体元件的至少一个所述边缘向外延伸。介电元件可具有前表面和远离前表面的后表面,并且可包括多个连接着接触部的导电垫。介电元件可还包括延伸在前后表面之间并且穿过所述多个导电垫的多个通孔。多个单元接触部可以暴露在微电子单元的外侧。导电特征可以从通孔中的接触部延伸,并且可以与单元接触部导电连通。
在本发明的另一个实施方式中,一种形成暴露在微电子元件后表面的单元接触部的方法可包括形成第一通孔,其从微电子元件的后表面朝向位于微电子元件前表面的元件接触部延伸。绝缘覆层可以形成为至少层叠于第一孔的壁上。第二孔可以被形成为延伸穿过元件接触部。暴露在后表面的单元接触部可以形成,其包括可以层叠于第一孔的壁并且可以层叠于第二孔的壁上并且与元件接触部导电连接的导电材料。
在本发明的另一个实施方式中,一种形成暴露在微电子元件后表面的单元接触部的方法可包括(a)形成通孔,其从微电子元件的后表面延伸穿过位于微电子元件前表面的元件接触部。绝缘层可以暴露在孔的壁上。此外,微电子元件可包括形成暴露在后表面的单元接触部,其包括层叠于绝缘层且与元件接触部导电连接的导电层。
附图说明
图1是半导体晶粒的透视图,所述半导体晶粒在其周边具有晶粒结合垫。
图2a是前(正)视图,图2b是剖视图示出了一种具有T型接触部的传统芯片级封装体。
图3是剖视图,示出了封装体具有暴露结合垫底侧(内表面)的穿透硅通道。
图4a是剖视图,示出了根据本发明一个实施方式的封装体具有穿透硅通道。
图4b是相应的俯视图,进一步示出了图4a所示的封装体。
图4c是剖视图,示出了图4a中的封装体的改型。
图4d-4h是剖视图,示出了根据本发明一个实施方式形成导电通道的过程中的各阶段。
图5a是剖视图,示出了根据本发明一个实施方式的微电子单元包括多个竖直层叠的半导体元件。
图5b是剖视图,示出了根据图5a所示实施方式的改型的微电子单元。
图6a是局部俯视图,示出了根据本发明一个实施方式的包括半导体元件和靠近半导体元件边缘的介电元件的重构晶片的一部分。
图6b是相应的剖视图,示出了根据本发明一个实施方式的延伸在示于图6a的重构晶片的半导体元件和介电元件之间的导电迹线。
图7a-7b是示于图6a-6b的重构晶片的剖视图,进一步示出了延伸穿过介电元件和其上接触部的穿透通道。
图8a-8f是剖视图,示出了根据本发明一个实施方式的形成导电通道的过程中的各阶段。
图9是俯视图,示出了微电子单元,其中与多个结合垫之间的导电互连延伸穿过公共开口。
图10a是剖视图,示出了根据本发明一个实施方式的晶片的一部分和位于两个相邻半导体元件例如晶粒之内和之间的开口。
图10b是相应的俯视图,示出了根据本发明一个实施方式的位于图10a所示晶片一部分中的若干相邻晶粒。
具体实施方式
本公开物中所描述的接触部″暴露在″介电元件的表面,可以是与该表面平齐,相对于该表面凹陷,或从该表面突出,只要接触部能被垂直于该表面的方向朝向该表面移动的理论点触及即可。如描述于例如共同未决的转让给同一受让人的美国专利申请No.10/949,674,该申请的公开内容以引用方式并入本申请,其中穿透导体可以包括元件例如固态金属球、焊料连接部或其它金属元件。此外,接触部可以布置在与穿透导体相同的位置或不同的位置。
图1是一种典型半导体晶粒100的透视图或等角视图,但未按比例绘制。晶粒100包括前表面101、晶粒边缘102和靠近晶粒周边呈阵列的结合垫103。虽然不能直接看到,但隐含的是晶粒的后表面104和埋入前表面101的面层紧邻下方的有源电路105。
下面描述如何在晶粒边缘或TSV的侧壁的配线迹线与晶粒前表面的结合垫之间形成T型接触部。该接触部可用于在晶粒结合垫和晶粒的相对表面上的BGA界面之间完成电路径。如后文所讨论,这种结构还提供了其它互连配置的可能性,包括从晶粒的前表面和两侧接触部开始制造即蚀刻的TSV。本发明的各种实施方式的一些益处包括每单位面积中的高互连密度,制造过程简单,并且穿过晶粒厚度的路径能提供低电阻。
图4a和4b示出了延伸穿过微电子元件400例如硅晶粒的TSV的一个例子。图4a是沿着完全穿过半导体晶粒的整个厚度延伸的通孔410形成的穿透硅通道TSV的剖视图。其包括晶粒的半导体材料区401、结合垫403和位于结合垫403下面的介电膜402。介电材料411例如绝缘覆层铺衬于延伸穿过半导体区401的通孔的壁420上。晶粒半导体区的厚度416可以在几十微米至几百微米的范围内。例如,一些半导体晶片的厚度为800微米。沿着晶粒表面(前表面)的典型结合垫宽度415为100微米,其典型地与结合垫沿着前表面的长度相同或相似。如示于图4b中的俯视图,结合垫403和孔410之间的交叉部可选地完全包含在结合垫403的区域内。
导体,其可以采用示于图4a的导电涂层412的形式,接触通孔410中的结合垫403的边缘并且延伸穿通道410到达后表面404。导电涂层412可以接触暴露于通孔410处的结合垫403的边缘,以形成T型接触部405。铺衬于通孔410的壁420上的介电材料411和导电涂层412或其它导体可选地延伸到晶粒的后表面404上的区域上。
具有竖直侧壁的TSV可能在加工过程中遇到困难。这样的TSV可能具有大的高宽比,其中每个TSV的高度超过TSV的直径,有时比例达到两倍或以上。当直径小时,高宽比大的TSV可能使得气相沉积过程和电沉积过程(例如,电泳涂覆和各种电镀过程)更难控制。
如示于图4c,孔410可具有锥形形状,以使得随着与前表面之间距离的增加,孔的尺寸增大。在这种情况下,随着与晶粒前表面之间距离的增加,孔的直径增大。这种形状提供了径向对称的T型接触部。形成穿过晶粒的中空孔,其具有平行的侧面并且垂直于晶粒表面,可以通过任何非材料选择型加工工艺实现。其例子包括机械钻销,激光蚀刻,和某些湿式蚀刻和活化等离子体化学工艺。在这些方法中,激光蚀刻可能相对容易用于批量制造,因为材料去除速度快,并且该工艺相关的软式工具也会带来益处。
由于用于形成孔的加工过程会穿透结合垫的厚度,因此会导致结合垫的原金属暴露出来。这意味着不需要在加工孔之前以及在孔壁上施加导电涂层之前进行细心清洁。这简化了加工过程。
参看图4d,在一个特定实施方式中,孔410可以被蚀刻在微电子元件的半导体区401中以便暴露位于元件接触部403和半导体区之间的介电层402的表面。绝缘层411(图4e)可以然后被形成,其沿着孔壁420延伸。之后,如示于图4f,孔410可以延展穿过介电层402和元件接触部403。如果绝缘层411在被形成时铺衬于的底部孔(例如显示于图4e),延展孔的过程可以引起孔穿过绝缘层411的一部分(图4f)。在孔延展穿过元件接触部403后,导电材料412可以然后被沉积成与元件接触部403和孔的绝缘层411接触,如示于图4a。
在本发明的另一个实施方式中,孔410可以在单一的步骤中被形成为穿过半导体区401、介电层402和元件接触部403,如可见于图4g。在这种情况下,孔可以利用激光蚀刻或钻销被形成。之后,绝缘层411可以被形成为刚好覆盖半导体区401,如可见于图4h。这样的绝缘层可以利用电泳沉积被形成。接下来,导电材料412可以被沉积为与元件接触部403和孔的绝缘层411接触,如示于图4a。这样的导电层可以利用化学气相沉积、溅镀或物理气相沉积被形成。
在示于图4a-4c的改型实施方式中,导体可以采用充填孔的固态导体的形式,或可以采用只沿着壁的一部分延伸的导电涂层的形式。在另一个改型中,如果晶粒的后表面已经包括了介电层,则介电层铺衬孔不需要延伸到晶粒的后表面上。
示于图4a-4c的类型的TSV的一个优点是,由此产生的互连工艺与相容晶粒的堆叠体,其中在俯视图中看每层晶粒上的结合垫相对正(图5a)。能够横贯多层晶粒的TSV技术使得能够在单一加工步骤中将所有这些结合垫并行地连接起来。所产生的微电子单元包括以叠层的形式结合在一起的竖直对正的晶粒501,每个晶粒具有T型接触部,其将每个晶粒的结合垫502与单元接触部504导电互连,如图5a所示。
图5a示出了上述结构的基本特征,该图是解释性的,而非按比例绘制的。图5a是穿过晶粒500的叠层的剖视图。在每层中,TSV 510延伸完全穿过晶粒501和结合垫502,从而与结合垫之间的每个连接部是通过截锥状T型接触部实现的。在完成后,两个附加特征被引入到本图中。它们是密封剂503其包围每个晶粒并将叠层保持在一起,以及BGA界面504,其位于晶粒叠层顶部上。
尽管图5a示出了TSV具有竖直的无锥度壁,但备选实施方式可以是不严格竖直无锥度的,不论其穿过单一晶粒还是晶粒叠层。TSV可以是锥形的以及相对于竖直方向偏斜的。唯一的约束是TSV必须在直径上小于其穿过的结合垫,如示于图4b。这最大化了T型接触部的长度。此外,局部形成在结合垫外侧的TSV有损坏晶粒上的电路的危险。根据现有技术,TSV可以被充填也可以不被充填介电或导电材料,取决于路径期望的电学特性,而对于高功率应用和高频应用来说,电学特性是不同的。
由于TSV横贯硅和结合垫的厚度,因此显然上述结构可以通过从晶粒的前表面和后表面之一加工而制成。实际中,如果其它因素允许,还可以从两侧加工TSV,其中彼此对正的TSV在晶粒的深度范围内会合。在完成TSV后,显然晶粒现在具有位于前表面上的结合垫,其与位于后表面上的一个相同位置的岛区连接。从实现电连接至晶粒的角度看,现在获得的是有效的双面元件,其可以以面向上方或面向下方的定向被安装。此外,假如结合垫是空置特征而没有与晶粒电路相连,则如果其它电学或电子部件被附装于晶粒的一个面上,这种新型的TSV可以用于从晶粒一面向另一面传输电信号,而不会干扰晶粒上的电路。
如前面所指出,TSV的导电元件必须与其穿过的半导体电隔离,否则的话各电路径之间会彼此短路。这是由例如示于图4的介电层411实现的。该介电层需要在加工孔之后施加,但其施加不能延伸至结合垫的将用于形成T型接触部的暴露金属。有多种用于形成介电膜的工艺满足这一要求。其中之一是通过氧化暴露的半导体产生介电层。这适用于半导体是硅的情况,因为硅石(氧化硅)是绝缘体。可以采用这样的化学过程,其能够氧化硅,但留下结合垫的金属保持金属状态。
在上述实施方式的一种改型中,图5b示出了一种层叠微电子单元,其中TSV 520延伸穿过第一半导体晶粒511和第一晶粒的结合垫522,TSV将结合垫524暴露于第二晶粒512的前表面。介电材料516可以被暴露在这两个晶粒的对置表面之间。导电层528将第一晶粒的结合垫522、第二晶粒512的垫524和微电子单元的单元接触部544导电互连。在示于图5b的改型实施方式中,不是采用单一第一晶粒511,而是多个第一晶粒可以层叠并且通过TSV中的导电层与第二晶粒512互连。
图6a示出了根据本发明一个实施方式的构建于重构晶片中的晶粒。硅晶粒601至少在四个面(五个面,如果晶粒底侧被覆盖的话)被介电材料602包围。晶粒601上的结合垫603通过配线迹线604连接至介电材料602上的新的结合垫605。沿着一个配线迹线所作的局部剖视图在图6b中以650表示。在该图中,可以看到,配线迹线654通过介电膜652与半导体隔离,作为晶粒制造过程的一个步骤,该介电膜被施加至晶粒。介电膜652不延伸超出晶粒周边,这是因为用于构成重构晶片并且围绕着晶粒的材料本质上也是介电的。
在重构晶片中,每个晶粒的边缘通常由介电材料围绕,该介电材料可以是固化的液体聚合物,例如,介电包覆成型成分,如示于图6a。介电材料可以还覆盖每个晶粒的后表面。介电材料602通常不覆盖晶粒601的前表面,而是与之平齐。制造重构晶片的过程中的一个步骤是施加图案化金属覆层至前表面。该配线迹线的功能是将晶粒结合垫连接至晶粒区域外侧的类似垫。这些新的结合垫是由导电材料形成的,例如层叠于介电材料的金属。对于示于图6a和6b的实施方式,穿透通道将被形成,其延伸穿过包围晶粒的介电材料602。这样,穿透通道将不需要附加的介电膜来将通道上的导电涂层与其穿透的介电材料隔离。当穿透通道全都相对于一个或以上重构晶片或叠层重构晶片形成时,可以特别实现更简单的经济型加工过程。重构晶片可以用于单一晶粒应用以及晶粒叠层。
图7a和7b示出了穿过根据本发明一个实施方式的形成在重构晶片700上的晶粒所作的剖视图。重构晶片更详细描述于2008年7月25日提交的美国专利申请″RECONSTITUTED WAFER STACKPACKAGING WITH AFTER-APPLIED PAD EXTENSIONS″,该申请要求2007年7月27日提交的美国临时申请No.60/962,200的优先权,该美国专利申请的公开内容也以引用方式并入本申请。此外,附加的细节提供于2008年6月20日提交的美国专利申请12/143,743中,其名称为″RECONSTITUTED WAFER LEVEL STACKING″,要求2007年6月20日提交的美国临时申请No.60/936,617的优先权,该美国专利申请也以引用方式并入本申请。
层叠于晶粒面701上的是晶粒结合垫702及其在晶粒上的相关的介电覆层703。晶粒在其侧面和后表面704被重构晶片的介电填充物705包围。穿透通道710(图7b)是台阶式的,并且具有第一通孔711和第二通孔713。第一通孔711具有锥形轮廓以有助于沉积导电涂层712于第一通孔711的壁上。第二结合垫714形成在介电填充层705的下表面715上,第二结合垫714导电连接着晶粒结合垫702。导电涂层712沿着第二结合垫714中第二通孔713的壁延伸。以这种方式,第二通孔713中的通道延伸段实现与第二结合垫714的导电接触。在施加导电涂层至该区域后,在第二结合垫714和通道延伸段713之间产生了截锥T型接触部。
加工穿过半导体晶粒的TSV和加工穿透介电层的穿透通道可以通过各式各样的工艺实现。在一些情况下,组合的工艺可以提供制造益处,例如,等离子体蚀刻可用于加工穿透硅的厚度以产生锥形通道,并且通过激光蚀刻产生延伸穿过结合垫的孔。所产生的结构具有这样的优点,即穿过硅的锥角有助于施加覆层至TSV的壁,而激光蚀刻可以用于产生穿过结合垫的小直径孔。互连可以因此而具有阶变直径结构,如图7中所示的由重构晶片形成的晶粒。这增大了定位许用公差,并且还允许接触到比主孔基部面积小的结合垫。一个附加优点是,同纯竖直通道相比,具有锥角的TSV可以大体上制作成具有低电阻,这时因为同具有平行侧面的通道相比,在给定沉积时间内施加的金属既具有更大表面面积又具有加大的厚度。
使用这样的两步式工艺(图7)来形成TSV,对于这种结构的某些实施方式来说具有益处。如前所述,当TSV延伸穿过半导体晶粒时,通常要求TSV的壁上的金属与半导体基底和其所穿过的任何其它导电结构电隔离,当然,除了其需要连接的结合垫以外。电泳介电膜,例如,通过电泳沉积,是一种有效且可靠的措施来向某个零件的所有表面施加连续且均匀厚度的介电膜,而不论它们是暴露表面还是因为具有大的高宽比而受到阻碍。共同拥有的美国专利申请No.11/590,616(2006年10月31日提交)和11/789,694(2007年4月25日提交)描述了电泳沉积介电层的方法,然后在介电层上形成导电层,例如迹线或其它导电互连。上述申请的公开内容以引用方式并入本申请。
图8a至8f示出了根据本发明一个实施方式的用于形成TSV的工艺。图8f示出了根据本发明一个实施方式的延伸穿过半导体晶粒的TSV的剖视图。
图8a示出了穿过半导体晶粒801的局部剖视图。晶粒的前表面802背对即远离其后表面803,并且包括通过介电膜805与半导体晶粒801隔离的结合垫804。晶粒被显示为具有覆盖其全部特征的保护介电膜806。该膜806是可以存在于某些类型的晶粒封装件中的结构的代表例,例如,可以是任何类型的柔顺层、晶粒贴附膜、晶粒层叠粘合剂或它们之间的组合。
图8b示出了形成从晶粒801的后表面802至晶粒的有源表面延伸的第一孔。对于一种实施方式,第一孔807的底表面安置在介电膜805上。根据一个实施方式,等离子体蚀刻工艺可以用于形成穿透硅厚度的第一孔807。由于等离子体工艺是材料选择型的,第一孔807终止于其上置有结合垫804的介电膜805。第一孔807可具有锥形轮廓,在晶粒后表面803具有最大面积。这样的锥形轮廓可以有助于随后涂覆其表面。作为备选实施方式,第一孔807可以通过湿式蚀刻或机械磨销被形成。
图8c示出了根据一个实施方式在晶粒后表面803上形成绝缘覆层808。绝缘覆层808在第一孔807中形成绝缘层。在一个实施方式中,介电膜例如电泳材料可以施加至晶粒的后表面,例如通过电泳沉积。由于电泳材料的性质,该介电膜将是随形的并且因此而涂覆于第一孔807的壁以及结合垫804下面的介电膜805。作为备选实施方式,其它介电膜例如阻焊剂或光阻剂可以使用。
图8d示出了根据一个实施方式形成延伸穿过绝缘层808、介电膜805和结合垫804的第二孔809。如可见于图8d,第二孔809的直径限定在结合垫804内。
作为一个实施方式,激光蚀刻可以用于穿透绝缘材料808、介电膜805和结合垫804的厚度形成第二孔809。如果结合垫上没有任何东西,则会产生通孔。然而,在这种条件下,晶粒的前表面被介电材料816覆盖。在这种情况下,可以激光烧蚀穿过介电膜和结合垫并且终止于晶粒罩层816的第二孔,从而有效地形成封闭孔或盲孔。作为一个实施方式,晶粒罩层816可以由阻焊剂形成。此外,晶粒罩层816可以用于形成晶粒和玻璃层(未示出)之间的空腔的侧壁。穿透晶粒801和结合垫804的台阶式通孔815由第一孔807和第二孔809形成并且从晶粒后表面803延伸穿过结合垫804。
图8e示出了根据一个实施方式形成导电层810,其可包括金属。导电层810然后被施加至由第一和第二孔形成的通孔815的内侧表面。由于台阶式通孔815穿过结合垫804,因此将形成径向对称的T型接触部811。通过用金属涂覆孔或用金属充填孔,TSV可以被形成。
一种可以用于施加金属覆层的工艺是气相沉积,其例子包括蒸镀和溅镀。这些过程还能将金属沉积到晶粒的后表面。通过将膜图案化,可以产生BGA界面812,其中每个用于焊料球的部位连接着通道和晶粒结合垫,如可见于图8f。通过附加工艺例如电镀,所施加的金属的厚度可以增加大约一个数量级。在另一个实施方式中,通道可以完全由导电材料充填。
之后,介电材料层813可以被沉积而层叠于孔中的导电层810上,如示于图8f。配线迹线的暴露金属可以被覆盖上有机保护介电覆层。常用的材料是阻焊剂。完成了的结构可以然后呈现为图8f中的形态。
图8a至8f示出了根据本发明一个实施方式形成通道,以提供形成于晶粒上的结合垫与BGA界面之间的电接触。孔从晶粒后表面延伸穿过结合垫。此外,第二孔的直径不延伸超出结合垫的周边。作为备选实施方式,第一和第二孔不需要是圆形的。第一孔可以显著加长以形成跨越若干结合垫的刻槽或沟槽。第二孔然后以单体的形式在刻槽或沟槽的基部穿过结合垫。这种实施方式要求涂覆于刻槽或沟槽的侧壁上的金属被图案化,除非希望一排结合垫被并联连接。后面这种情况有时出现于利用结合垫向半导体供应电能时。
晶粒结合垫或重构晶片的介电区上的结合垫的典型尺寸为一侧100μm的范围内。如果是平行侧面的,典型的TSV的直径为大约50μm;如果是锥形的,则基部直径为大约50μm,开口处直径为大约80μm。穿过结合垫的TSV延伸段略小,具有大约20μm的直径。
所有前述例子涉及一个TSV与单一结合垫或结合垫的叠层相交的情况。其中一个原因是通道上的导电涂层是单一金属片材并且因此而提供出一个电路径。现有对通道内部的金属进行图案化的技术。因此,单一通道可以用于与多个结合垫相交和连接。在这种条件下,每个T型接触部将不是完整圆或椭圆,而是弧。这种实施方式显示于图9。
图9提供了根据本发明一个实施方式的安置在四个结合垫上的一个TSV的俯视图。该TSV在其侧壁具有图案化金属,这允许单独的路径形成在每个结合垫上。四个结合垫901、902、903和904暴露于晶粒的前表面。锥形通道905穿过全部四个结合垫的一部分。TSV上的金属在部位906、907、908和909被图案化,以提供通向结合垫的彼此独立的弧形T型接触部。
TSV的形成优选以晶片级工艺实现,因为这允许所有结构被并行加工,从而加工成本被所有产出部件分担。在这种工艺完成后,晶片必须被分离以形成自由的单个晶粒。这可以通过机械锯切实现。备选地,其可以被有机化,从而当半导体被加工以形成TSV的孔时,材料还从切分构造去除,如示于图10a。然后,分离涉及去除或切断晶片前部切分沟槽中的任何材料,或简单地锯断。同切断半导体加上这些层的全部厚度相比,所有上述过程都能更快地完成。尽管用于电连接的TSV优选为圆形的,但显然,为了分离出晶片上的晶粒,沟槽中制作的TSV可以采用各晶粒之间沟槽(切分线)中的凹槽的形式,如示于图10b。晶粒可以在每个角部由半导体材料的小韧带维持连接,因为这样可以维持晶片整个后表面相对于单一电接接触部的电连续性。这种配置可能有助于后面的加工步骤,即施加电泳介电膜。
图10a和10b显示了根据一个实施方式本发明的用于形成TSV的工艺如何能够用于同时从切分沟槽(切分线)去除半导体材料,这有助于随后从晶片分离出单个晶粒。示于图10a的是晶片的两个相邻晶粒1010和1020之间的切分沟槽1001。每个晶粒具有TSV 1011/1021孔,其形成为穿过硅到达结合垫1013/1023下面的介电膜1012/1022。通过用于形成将被用于电连接的TSV的同一加工过程,另一TSV 1002在切分沟槽中制作出来。通过去除晶片材料的这一部分,晶粒被有效地分离,而不需要随后的切分步骤。图10b是晶片上若干相邻晶粒的后表面的俯视图1050。圆形TSV 1051被形成为接触每个结合垫,而作为分离过程的一个步骤,凹槽形TSV 1052被同时加工于切分沟槽中。半导体材料韧带1054保留在四个晶粒角部的每个交叉部,以提供晶片表面的电连续性,以便用于后续的电泳工艺。
这里描述的各种实施方式的特征可以相互组合以形成微电子单元,其中微电子单元具有一个所述实施方式中的一些或全部特征和另一所述实施方式中的一个或以上特征。申请人旨在通过这里的公开内容涵盖所有这样的特征组合,即使这种组合并未专门描述。

Claims (29)

1.一种微电子单元,包括:
半导体元件,其具有前表面、位于前表面的多个接触部和远离前表面的后表面;
多个通孔,每个通孔从所述后表面延伸穿过所述多个接触部中相应的一个接触部;所述多个接触部分别具有背对所述半导体元件的外表面和与所述外表面相反的内表面,所述多个通孔分别至少部分地铺衬有介电层,所述多个通孔限定出在所述多个接触部中从所述内表面朝向所述外表面延伸的壁;和
位于通孔中的导电通道,所述导电通道至少接触所述接触部中的壁,从而将所述接触部与层叠于所述后表面上的导体互连。
2.根据权利要求1的微电子单元,还包括单元接触部,所述单元接触部层叠于后表面上并且连接着所述导体。
3.根据权利要求2的微电子单元,其中,所述孔是锥形的,所述孔随着与后表面之间距离的增大而缩小。
4.根据权利要求3的微电子单元,其中,孔的壁相对于后表面的法线以5度或以上的角度定向。
5.根据权利要求4的微电子单元,其中,所述壁相对于的法线后表面以小于或等于40度的角度定向。
6.根据权利要求1的微电子单元,其中,每个通孔的总面积被包围在一个所述接触部的面积内。
7.根据权利要求1的微电子单元,其中,所述导体与暴露在后表面上的位置上的单元接触部互连。
8.根据权利要求1的微电子单元,其中,所述导电通道通过所述介电层与通孔的壁分隔。
9.根据权利要求1的微电子单元,进一步包括靠近前表面的微电子器件,所述接触部连接着微电子器件。
10.根据权利要求1的微电子单元,其中,所述后表面包括多个盲孔,每个盲孔与至少一个所述通孔对正。
11.根据权利要求10的微电子单元,其中,每个盲孔与单一的通孔对正。
12.根据权利要求10或11的微电子单元,其中,每个盲孔的壁相对于后表面的法线以5度或以上的角度定向。
13.根据权利要求1的微电子单元,其中,还包括细长沟槽,所述沟槽与多个通孔对正。
14.根据权利要求13的微电子单元,其中,每个细长沟槽的壁相对于后表面的法线以5度或以上的角度定向。
15.根据权利要求1的微电子单元,进一步包括将接触部与半导体元件的前表面分隔的介电层,其中,所述通孔延伸穿过介电层,并且导电通道直接接触通孔中的介电层的壁。
16.一种微电子单元,包括:
半导体元件,其具有前表面、位于前表面的接触部、远离前表面的后表面和延伸在前后表面之间的边缘,所述接触部具有背对所述半导体元件的外表面和与所述外表面相反的内表面;
从半导体元件的至少一个所述边缘向外延伸的介电元件,所述介电元件具有前表面和远离前表面的后表面,所述介电元件承载着连接至接触部的多个导电垫,所述介电元件具有延伸在前后表面之间并且穿过所述多个导电垫的多个通孔;
暴露在微电子单元外侧的多个单元接触部;和
从通孔中的接触部延伸的导电特征,所述导电特征与所述单元接触部导电连通。
17.一种形成暴露在微电子元件后表面的单元接触部的方法,包括:
(a)形成第一通孔,其从微电子元件的后表面朝向位于微电子元件前表面的元件接触部延伸,所述元件接触部具有背对所述微电子元件的外表面和与所述外表面相反的内表面;
(b)形成绝缘覆层,其至少层叠于第一通孔的壁上;
(c)形成第二孔,其延伸穿过所述元件接触部并且限定出在所述元件接触部中从所述内表面朝向所述外表面延伸的壁;和
(d)形成暴露在后表面的单元接触部,其包括至少部分地层叠于在第一通孔的壁和第二孔的壁上铺衬的介电材料上的导电材料,所述导电材料至少接触所述元件接触部中的壁,从而导电连接到元件接触部。
18.根据权利要求17的形成单元接触部的方法,其中,所述元件接触部通过介电层与前表面分隔。
19.根据权利要求17的形成单元接触部的方法,其中,所述绝缘覆层被形成为层叠于介电层上,并且第二孔延伸穿过介电层。
20.根据权利要求17的方法,其中,绝缘覆层通过电泳沉积形成。
21.根据权利要求17的方法,其中,绝缘覆层可选自下面一组:电泳材料,阻焊剂,光阻剂。
22.根据权利要求17的方法,其中,第二孔通过激光蚀刻形成。
23.根据权利要求17的方法,其中,步骤(d)包括用导电材料充填第一通孔和第二孔。
24.根据权利要求17的方法,其中,步骤(d)包括沿着第一通孔和第二孔的壁形成导电材料层,并沉积绝缘材料以便层叠于导电材料上。
25.根据权利要求17的方法,其中,步骤(d)包括通过气相沉积、蒸镀、溅镀中的至少一种沉积导电材料。
26.根据权利要求17的方法,其中,所述单元接触部包括靠近微电子元件后表面的球栅阵列形式的导电球。
27.根据权利要求17的方法,其中,绝缘材料包括阻焊剂。
28.一种形成暴露在微电子元件后表面的单元接触部的方法,包括:
(a)形成通孔,其从微电子元件的后表面延伸穿过位于微电子元件前表面的元件接触部,所述元件接触部具有背对着所述微电子元件的外表面、与所述外表面相反的内表面以及在所述内表面与外表面之间延伸的壁表面,所述通孔至少部分地铺衬有绝缘层,其中所述绝缘层暴露在孔的壁处;和
(b)形成暴露在后表面的单元接触部,其包括层叠于绝缘层上并且层叠于所述元件接触部的壁表面上的导电层,从而与元件接触部导电连接。
29.根据权利要求28的方法,其中,步骤(a)包括在微电子元件中包含的半导体材料中蚀刻出孔,以暴露出位于元件接触部和半导体材料之间的介电层的表面,然后沿着孔的壁形成绝缘层,然后形成延伸穿过绝缘层和元件接触部的孔。
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JP2013175764A (ja) 2013-09-05
KR20150045953A (ko) 2015-04-29
CN103178032A (zh) 2013-06-26
CN101802990A (zh) 2010-08-11
WO2009017835A3 (en) 2009-04-16
KR101588723B1 (ko) 2016-01-26
WO2009017835A2 (en) 2009-02-05
CN103178032B (zh) 2017-06-20
US8193615B2 (en) 2012-06-05
KR101538648B1 (ko) 2015-07-22
US8735287B2 (en) 2014-05-27
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US20120241976A1 (en) 2012-09-27
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