JP6436738B2 - プリント配線板、半導体装置及びプリント回路板 - Google Patents
プリント配線板、半導体装置及びプリント回路板 Download PDFInfo
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- JP6436738B2 JP6436738B2 JP2014234445A JP2014234445A JP6436738B2 JP 6436738 B2 JP6436738 B2 JP 6436738B2 JP 2014234445 A JP2014234445 A JP 2014234445A JP 2014234445 A JP2014234445 A JP 2014234445A JP 6436738 B2 JP6436738 B2 JP 6436738B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
実施例のプリント配線板100は、4層とした。ランド111の間隔及びヴィア120の間隔は0.5[mm]とした。ここでは、ヴィア120はビルドヴィアとした。
比較例のプリント配線板は4層とした。図7(a)は比較例のプリント配線板の導体層(第1導体層)101Xを示す平面図である。図7(b)は比較例のプリント配線板の導体層(第2導体層)102Xを示す平面図である。図7(c)は比較例のプリント配線板の導体層(第3導体層)103Xを示す平面図である。図7(d)は比較例のプリント配線板の導体層(第4導体層)104Xを示す平面図である。
Claims (6)
- 絶縁体層を介して積層された複数の導体層を有し、
前記複数の導体層のうち表層には、前記表層に対して直交する方向から見て互いに間隔をあけて三角格子状に配置された複数のランドからなるランド群が形成され、
前記ランド群を囲む仮想的な長方形の領域のうち最小面積の長方形の領域の1辺と前記三角格子の3辺のそれぞれとの間で成す角度のうち最小となる角度が、7度以上23度以下となるように前記ランド群が配置されていることを特徴とするプリント配線板。 - 前記最小となる角度が15度であることを特徴とする請求項1に記載のプリント配線板。
- 前記ランド群のうち最外周に位置するランドからは、前記表層にて前記長方形の領域の外側に配線が引き出され、
前記最外周に位置するランド以外のランドからは、ヴィアを介して前記表層以外の導体層にて前記長方形の領域の外側に配線が引き出されていることを特徴とする請求項1又は2に記載のプリント配線板。 - 半導体素子と、
前記半導体素子が実装された配線基板と、を備え、
前記配線基板の表層には、前記表層に対して直交する方向から見て互いに間隔をあけて三角格子状に配置された複数の端子からなる端子群が形成され、
前記端子群を囲む仮想的な長方形の領域のうち最小面積の長方形の領域の1辺と前記三角格子の3辺のそれぞれとの間で成す角度のうち最小となる角度が、7度以上23度以下となるように前記端子群が配置されていることを特徴とする半導体装置。 - 前記最小となる角度が15度であることを特徴とする請求項4に記載の半導体装置。
- 請求項1乃至3のいずれか1項に記載のプリント配線板と、
請求項4又は5に記載の半導体装置と、を備え、
前記半導体装置の端子が、前記プリント配線板のランドに接合されていることを特徴とするプリント回路板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014234445A JP6436738B2 (ja) | 2014-11-19 | 2014-11-19 | プリント配線板、半導体装置及びプリント回路板 |
US14/944,051 US9693450B2 (en) | 2014-11-19 | 2015-11-17 | Printed wiring board, semiconductor device and printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014234445A JP6436738B2 (ja) | 2014-11-19 | 2014-11-19 | プリント配線板、半導体装置及びプリント回路板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016100392A JP2016100392A (ja) | 2016-05-30 |
JP6436738B2 true JP6436738B2 (ja) | 2018-12-12 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014234445A Active JP6436738B2 (ja) | 2014-11-19 | 2014-11-19 | プリント配線板、半導体装置及びプリント回路板 |
Country Status (2)
Country | Link |
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US (1) | US9693450B2 (ja) |
JP (1) | JP6436738B2 (ja) |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0669371A (ja) * | 1992-08-18 | 1994-03-11 | Toshiba Corp | Pgaパッケージ |
US5784262A (en) * | 1995-11-06 | 1998-07-21 | Symbios, Inc. | Arrangement of pads and through-holes for semiconductor packages |
US6404460B1 (en) * | 1999-02-19 | 2002-06-11 | Omnivision Technologies, Inc. | Edge enhancement with background noise reduction in video image processing |
JP2001053437A (ja) * | 1999-08-06 | 2001-02-23 | Shinko Electric Ind Co Ltd | 多層回路基板 |
US6373139B1 (en) * | 1999-10-06 | 2002-04-16 | Motorola, Inc. | Layout for a ball grid array |
JP2004140079A (ja) * | 2002-10-16 | 2004-05-13 | Canon Inc | エリアアレイ型半導体装置とそれを用いた電子回路基板 |
US6992374B1 (en) * | 2004-06-14 | 2006-01-31 | Cisco Technology, Inc. | Techniques for manufacturing a circuit board with an improved layout for decoupling capacitors |
JP2006210851A (ja) * | 2005-01-31 | 2006-08-10 | Toshiba Corp | 回路基板 |
US9545009B2 (en) * | 2007-05-23 | 2017-01-10 | Spectra Logic, Corporation | Passive alterable electrical component |
EP2183770B1 (en) * | 2007-07-31 | 2020-05-13 | Invensas Corporation | Method of forming through-substrate vias and corresponding decvice |
JP5213034B2 (ja) * | 2008-07-09 | 2013-06-19 | Necインフロンティア株式会社 | Bgaパッケージ |
JP2011124382A (ja) * | 2009-12-10 | 2011-06-23 | Fujitsu Ltd | プリント配線基板、プリント配線基板ユニット、および電子装置 |
US8273994B2 (en) * | 2009-12-28 | 2012-09-25 | Juniper Networks, Inc. | BGA footprint pattern for increasing number of routing channels per PCB layer |
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2014
- 2014-11-19 JP JP2014234445A patent/JP6436738B2/ja active Active
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2015
- 2015-11-17 US US14/944,051 patent/US9693450B2/en active Active
Also Published As
Publication number | Publication date |
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JP2016100392A (ja) | 2016-05-30 |
US20160143133A1 (en) | 2016-05-19 |
US9693450B2 (en) | 2017-06-27 |
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