JP5211396B2 - 3d電子モジュールを集積的に製造する方法 - Google Patents
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- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Description
製造が集積的なものであり、
ウェーハi毎に、
A1)厚さeiの薄い電気的絶縁層によって一方の面が被覆され、この面に幅L1でありeiよりも深くep+eiよりも浅い深さの溝部を有する基板を形成する、シリコンを含む厚さepの同一の平らな薄いシートに、1組のn枚のウェーハiを製造する工程であって、これらの溝部が少なくともn個の幾何学的パターンを画定し、各パターンに前記面に配置された電気的接続要素に接続された少なくとも1つの電子素子が設けられ、端子が少なくとも溝部まで延長した電気的接続要素に連結され、溝部および電気的接続要素の交点にホール開口領域が設けられ、この領域の横断寸法がL1よりも小さく、素子が溝部をも埋める絶縁樹脂により被覆された工程と、
B1)溝部の樹脂を露出するようにシートの他方の面を平面研削することにより薄膜化する工程とを含む第1の工程と、
A2)第1の工程を完了した際に得られたK個の組を、開口領域を実質的に上下に重ね合わせるように、積層し組み立て、
B2)シリコンがホールの側壁から樹脂によって絶縁されるように、樹脂に、横断寸法がL1よりも小さいホールを、開口領域に垂直な積層体の全体の厚さにかけてシートの面に垂直に開け、
C2)ホールの側壁を金属被覆し、
D2)n個の電子モジュールを得るために積層体を溝部に沿って切断する第2の工程とを含むことを特徴とする方法である。
Claims (17)
- n個の電子モジュールを製造する方法であって、nが1よりも大きい整数であり、モジュールがK枚の電子ウェーハの積層体を備え、ウェーハi(iは1〜Kの範囲である)が絶縁基板に少なくとも1つの電子素子を備え、前記K枚のウェーハが前記積層体の側面に配置された導体によって電気的に相互に連結された方法において、
前記製造が集積的なものであり、
ウェーハi毎に、
A1)厚さeiの薄い電気的絶縁層によって一方の面が被覆され、この面に幅L1でありeiよりも深くep+eiよりも浅い深さの溝部を有する基板を形成するシリコンを含む厚さepの同一の平らな薄いシートに、1組のn枚のウェーハiを製造する工程であって、これらの溝部が少なくともn個の幾何学的パターンを画定し、溝部が絶縁樹脂で埋められ、各パターンには前記面に配置された電気的接続端子に接続された少なくとも1つのシリコン電子素子が設けられ、前記端子が少なくとも溝部を埋める絶縁樹脂の表面まで延長した電気的接続要素に連結され、前記溝部および前記接続要素の交点にホール開口領域が設けられ、この領域の横断寸法がL1よりも小さく、前記素子が前記溝部をも埋める絶縁樹脂により被覆された工程と、
B1)前記溝部の前記樹脂を露出するように前記シートの他方の面を平面研削することにより薄膜化する工程とを含む第1の工程と、
A2)前記第1の工程を完了した際に得られたK個の組を、前記開口領域を実質的に上下に重ね合わせるように、積層し組み立て、
B2)前記シリコンが前記ホールの側壁から前記樹脂によって絶縁されるように、前記樹脂に、横断寸法がL1よりも小さく、かつ、溝部を埋める絶縁樹脂の全ての層と、電気的接続要素の全てのホール開口領域を貫通するホールを、前記開口領域に垂直な積層体の全体の厚さにかけてシートの面に垂直に開け、
C2)前記ホールの前記側壁を金属被覆し、
D2)前記n個の電子モジュールを得るために前記積層体を前記溝部に沿って切断する第2の工程とを含むことを特徴とする方法。 - 前記第2の工程の前に、前記素子を備える前記シートの面を平面研削することにより前記シートを薄膜化する工程も含むことを特徴とする請求項1に記載の方法。
- 前記工程D2の前に、前記シートに平行な前記積層体の一方の面に電気的絶縁層を堆積する工程を含み、この層が、各パターンの平面に、前記ウェーハの前記開口領域の中央に開口領域をもたらし、かつこれらの領域まで延長した、前記モジュールを電気的に相互接続する要素を備えることを特徴とする請求項1または2に記載の方法。
- 前記第2の工程が、前記ホールの前記側壁を金属被覆する工程の後に、次の前記積層体の切断を容易にするために前記ホールを樹脂により再び埋める工程も含むことを特徴とする請求項1〜3のいずれか一項に記載の方法。
- 前記電子素子が、能動素子または受動素子またはMEMSであることを特徴とする請求項1〜4のいずれか一項に記載の方法。
- 前記能動素子がベアチップである請求項5に記載の方法。
- 少なくとも1つの受動素子が、前記シート内または前記シートの上に配置されることを特徴とする請求項1〜6のいずれか一項に記載の方法。
- 前記薄い絶縁層が絶縁樹脂で作製されていることを特徴とする請求項1〜7のいずれか一項に記載の方法。
- 前記電気的接続要素が前記溝部をまたいでいることを特徴とする請求項1〜8のいずれか一項に記載の方法。
- 前記電気的接続要素が溝部の両側に配置された2つの端子を連結していることを特徴とする請求項1〜9のいずれか一項に記載の方法。
- 前記工程D2の切断の前に、前記結果として得られた積層体を電気的に検査する工程も含むことを特徴とする請求項1〜10のいずれか一項に記載の方法。
- 前記電気的接続要素がエッチングされたブリッジであることを特徴とする請求項1〜11のいずれか一項に記載の方法。
- 前記溝部を樹脂により埋めた後、前記素子を樹脂により被覆する前に、前記ブリッジをエッチングすることを特徴とする請求項12に記載の方法。
- 前記ホールがドライエッチングによって開けられることを特徴とする請求項1〜13のいずれか一項に記載の方法。
- 前記電気的接続要素が配線されたフィラメントであることを特徴とする請求項1〜11のいずれか一項に記載の方法。
- 前記フィラメントが前記溝部に沿って切り取られることを特徴とする請求項15に記載の方法。
- 前記ホールが液体エッチングによって開けられることを特徴とする請求項15または16に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0513217A FR2895568B1 (fr) | 2005-12-23 | 2005-12-23 | Procede de fabrication collective de modules electroniques 3d |
FR0513217 | 2005-12-23 | ||
PCT/EP2006/069948 WO2007071696A1 (fr) | 2005-12-23 | 2006-12-19 | Procede de fabrication collective de modules electroniques 3d |
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JP2009521116A JP2009521116A (ja) | 2009-05-28 |
JP5211396B2 true JP5211396B2 (ja) | 2013-06-12 |
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US (1) | US7877874B2 (ja) |
EP (1) | EP1966825B1 (ja) |
JP (1) | JP5211396B2 (ja) |
DE (1) | DE602006009967D1 (ja) |
FR (1) | FR2895568B1 (ja) |
WO (1) | WO2007071696A1 (ja) |
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FR2911995B1 (fr) * | 2007-01-30 | 2009-03-06 | 3D Plus Sa Sa | Procede d'interconnexion de tranches electroniques |
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FR2940521B1 (fr) | 2008-12-19 | 2011-11-11 | 3D Plus | Procede de fabrication collective de modules electroniques pour montage en surface |
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FR3048123B1 (fr) | 2016-02-19 | 2018-11-16 | 3D Plus | Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d |
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-
2005
- 2005-12-23 FR FR0513217A patent/FR2895568B1/fr active Active
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2006
- 2006-12-19 US US12/158,125 patent/US7877874B2/en active Active
- 2006-12-19 WO PCT/EP2006/069948 patent/WO2007071696A1/fr active Application Filing
- 2006-12-19 JP JP2008546434A patent/JP5211396B2/ja active Active
- 2006-12-19 DE DE602006009967T patent/DE602006009967D1/de active Active
- 2006-12-19 EP EP06841479A patent/EP1966825B1/fr active Active
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EP1966825B1 (fr) | 2009-10-21 |
JP2009521116A (ja) | 2009-05-28 |
US7877874B2 (en) | 2011-02-01 |
US20080289174A1 (en) | 2008-11-27 |
EP1966825A1 (fr) | 2008-09-10 |
FR2895568B1 (fr) | 2008-02-08 |
DE602006009967D1 (de) | 2009-12-03 |
WO2007071696A1 (fr) | 2007-06-28 |
FR2895568A1 (fr) | 2007-06-29 |
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