DE602006009967D1 - Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen - Google Patents

Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen

Info

Publication number
DE602006009967D1
DE602006009967D1 DE602006009967T DE602006009967T DE602006009967D1 DE 602006009967 D1 DE602006009967 D1 DE 602006009967D1 DE 602006009967 T DE602006009967 T DE 602006009967T DE 602006009967 T DE602006009967 T DE 602006009967T DE 602006009967 D1 DE602006009967 D1 DE 602006009967D1
Authority
DE
Germany
Prior art keywords
modules
electronic
joint manufacture
joint
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009967T
Other languages
English (en)
Inventor
Christian Val
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3D Plus SA
Original Assignee
3D Plus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3D Plus SA filed Critical 3D Plus SA
Publication of DE602006009967D1 publication Critical patent/DE602006009967D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Micromachines (AREA)
DE602006009967T 2005-12-23 2006-12-19 Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen Active DE602006009967D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0513217A FR2895568B1 (fr) 2005-12-23 2005-12-23 Procede de fabrication collective de modules electroniques 3d
PCT/EP2006/069948 WO2007071696A1 (fr) 2005-12-23 2006-12-19 Procede de fabrication collective de modules electroniques 3d

Publications (1)

Publication Number Publication Date
DE602006009967D1 true DE602006009967D1 (de) 2009-12-03

Family

ID=36764718

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009967T Active DE602006009967D1 (de) 2005-12-23 2006-12-19 Verfahren zur gemeinsamen herstellung von elektronischen 3d-modulen

Country Status (6)

Country Link
US (1) US7877874B2 (de)
EP (1) EP1966825B1 (de)
JP (1) JP5211396B2 (de)
DE (1) DE602006009967D1 (de)
FR (1) FR2895568B1 (de)
WO (1) WO2007071696A1 (de)

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FR2905198B1 (fr) * 2006-08-22 2008-10-17 3D Plus Sa Sa Procede de fabrication collective de modules electroniques 3d
FR2911995B1 (fr) * 2007-01-30 2009-03-06 3D Plus Sa Sa Procede d'interconnexion de tranches electroniques
US7846772B2 (en) * 2008-06-23 2010-12-07 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US7745259B2 (en) * 2008-06-30 2010-06-29 Headway Technologies, Inc. Layered chip package and method of manufacturing same
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
EP2207200A1 (de) * 2008-12-24 2010-07-14 Nxp B.V. Stapel von verkapselten IC-Chips mit seitlichen Leiterbahnen
EP2202789A1 (de) * 2008-12-24 2010-06-30 Nxp B.V. Stapel von verkapselten IC-Chips mit seitlichen Leiterbahnen
US8274165B2 (en) * 2009-02-10 2012-09-25 Headway Technologies, Inc. Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same
JP4956567B2 (ja) 2009-02-17 2012-06-20 本田技研工業株式会社 燃料電池システムおよび燃料電池システムの制御方法
FR2943176B1 (fr) 2009-03-10 2011-08-05 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
US8569878B2 (en) * 2009-10-22 2013-10-29 Headway Technologies, Inc. Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same
US7902677B1 (en) * 2009-10-28 2011-03-08 Headway Technologies, Inc. Composite layered chip package and method of manufacturing same
US8263876B2 (en) * 2009-12-30 2012-09-11 Harvatek Corporation Conductive substrate structure with conductive channels formed by using a two-sided cut approach and a method for manufacturing the same
US8587125B2 (en) 2010-01-22 2013-11-19 Headway Technologies, Inc. Method of manufacturing layered chip package
US8298862B2 (en) * 2010-02-04 2012-10-30 Headway Technologies, Inc. Method of manufacturing layered chip package
US8426946B2 (en) 2010-06-28 2013-04-23 Headway Technologies, Inc. Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
US8426948B2 (en) * 2010-08-02 2013-04-23 Headway Technologies, Inc. Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
US8541887B2 (en) 2010-09-03 2013-09-24 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8441112B2 (en) * 2010-10-01 2013-05-14 Headway Technologies, Inc. Method of manufacturing layered chip package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8652877B2 (en) 2010-12-06 2014-02-18 Headway Technologies, Inc. Method of manufacturing layered chip package
US8824161B2 (en) 2012-06-15 2014-09-02 Medtronic, Inc. Integrated circuit packaging for implantable medical devices
US9252415B2 (en) 2012-06-15 2016-02-02 Medtronic, Inc. Power sources suitable for use in implantable medical devices and corresponding fabrication methods
US11213690B2 (en) 2012-06-15 2022-01-04 Medtronic, Inc. Wafer level packages of high voltage units for implantable medical devices
KR20150141440A (ko) * 2014-06-10 2015-12-18 삼성전자주식회사 반도체 칩, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
FR3048123B1 (fr) 2016-02-19 2018-11-16 3D Plus Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d

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FR2805082B1 (fr) 2000-02-11 2003-01-31 3D Plus Sa Procede d'interconnexion en trois dimensions et dispositif electronique obtenu par ce procede
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FR2832136B1 (fr) 2001-11-09 2005-02-18 3D Plus Sa Dispositif d'encapsulation hermetique de composant devant etre protege de toute contrainte
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FR2875672B1 (fr) 2004-09-21 2007-05-11 3D Plus Sa Sa Dispositif electronique avec repartiteur de chaleur integre

Also Published As

Publication number Publication date
EP1966825B1 (de) 2009-10-21
EP1966825A1 (de) 2008-09-10
FR2895568B1 (fr) 2008-02-08
FR2895568A1 (fr) 2007-06-29
WO2007071696A1 (fr) 2007-06-28
US7877874B2 (en) 2011-02-01
JP5211396B2 (ja) 2013-06-12
US20080289174A1 (en) 2008-11-27
JP2009521116A (ja) 2009-05-28

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