TWI392054B - 用於三維電子模組之集體式製造的製程 - Google Patents

用於三維電子模組之集體式製造的製程 Download PDF

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TWI392054B
TWI392054B TW096130739A TW96130739A TWI392054B TW I392054 B TWI392054 B TW I392054B TW 096130739 A TW096130739 A TW 096130739A TW 96130739 A TW96130739 A TW 96130739A TW I392054 B TWI392054 B TW I392054B
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wafer
trenches
components
component
stack
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TW200826229A (en
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Christian Val
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3D Plus
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Description

用於三維電子模組之集體式製造的製程
本發明的領域為三維電子模組之製造的領域。
三維電子模組包含電子晶粒之堆疊，其利用堆疊的表面在三維中彼此互連，以製造晶粒間的連接。展示於圖1中的一實例，一晶粒50通常包含具有電性連接單元2的一或多個主動或被動元件11，該些元件被封裝於電性絕緣樹脂6中。該些元件的連接單元2連接於電性絕緣基板4上的連接墊2’。在絕緣基板4上的一或多個電性導電軌3將這些元件連接在一起，或將該些元件連接於將晶粒電性連接在一起的單元。該些晶粒係經由位於該堆疊之側表面上的導體而電性連接在一起，也就是在該些晶粒之邊緣7上。
已存在幾種方法用於將元件的連接墊2連接於基板的連接墊2’。
一方法在於藉由傳送超音波而將元件的連接墊直接連接於絕緣基板的連接墊。該傳送的能量與欲連接之連接墊數目成比例。針對具有大量數目之連接墊的元件，用於連接所需要的能量有時會造成元件的破裂。用於降低此能量的一解決方法在於加熱該基板，接著該基板軟化並吸附一些傳送的超音波能量，藉此使得連接變得非常的困難。此外，在該些元件封裝的期間，藉由在大約150℃實行的硬化步驟，使得該基板傾向於變成彎曲，因為元件的膨脹係數不同於基板的膨脹係數，典型地小於四倍。
由此，將所獲得的該些晶粒一個個地電性測試，以便在該些晶粒被堆疊之前移除具有缺陷元件的該些晶粒，以獲得三維電子模組。
本發明的目的係減少這些缺點，以製造無缺陷元件的三維模組。
本發明的原理係於製造期間保持元件與基板之間良好的材料連續性，以避免在連接步驟及/或硬化步驟期間有不同的膨脹，同時允許實行集體式電性測試。於此方式，用於製造三維電子模組之堆疊步驟係僅利用具有合格元件之晶粒來實行。
更精確地，本發明的目的係一種用於n個電子模組之製造的製程，n係大於1的一整數，一模組包含K個電子晶粒的堆疊，一晶粒i，i係從1至K改變，包含在絕緣基板上的至少一電子元件，該K個晶粒係藉由位於該堆疊之側表面上的導體而電性連接一起，其特徵在於該製造是集體式的並且包含：針對每個晶粒i，第一步驟係由下列組成：A1)在一個以及厚度es 之相同薄平面的包含矽之晶圓(10)上製造一批次n個晶粒i的步驟，以稱為測試墊的電性連接墊(20)覆蓋在一表面上，並接著以厚度ei 的薄電性絕緣層(4)覆蓋，該絕緣層形成該絕緣基板並且設置有至少一矽電子元件(11)，該矽電子元件包含通過該絕緣層連接於該些測試墊(20)之連接墊(2)，該些元件被封裝於厚度er 之絕緣樹脂(6)中，該絕緣樹脂充填該些元件間的空間，接著藉由具有一寬度L1及一深度P1之第一溝槽(30)彼此互相分隔使得ei ＋er <P1<ei ＋er ＋es ，該些元件的該些連接墊(2)連接於與該些溝槽(30)齊平的軌(3)；B1)沉積一黏著支撐(40)於該元件側表面上的步驟；C1)移除該矽晶圓(10)以使露出該些測試墊(20)的步驟；D1)經由該些測試墊(20)來電性測試該晶圓的該些元件以及標示該些合格元件(11’)及/或缺陷元件的步驟；以及E1)將該些晶粒(50)接合至一黏著膜(41)上的步驟，每個晶粒包含連接於測試墊(20)以及連接於至少一軌(3)、絕緣樹脂(6)、和一絕緣層(4)的一合格元件(11’)，該些晶粒藉由寬度L2之第二溝槽(31)而被分隔，該些合格元件(11’)之連接軌(3)與該些第二溝槽齊平；以及第二步驟係由下列組成：A2)堆疊及裝配在該第一步驟之後所獲得的該些K批次，以便實質上一個在另一個上來疊置該些第二溝槽(31)；B2)在該些第二溝槽上在該些堆疊中形成具有一寬度L3≧L2的第三溝槽(32)；以及C2)將該些第三溝槽(32)之壁上的該些晶粒互連。
此製程使得隔開該些晶粒以便在晶圓上集體式測試該些晶粒變成可能，以重建具有該些合格元件的另一晶圓並使得這些第三溝槽具有足夠寬度，以便在這些溝槽獲得更清晰的導電軌域區段。
此製程因此使得集體式製造具有無缺陷元件之三維電子模組變成可能。
較佳地，在沉積一黏著支撐於該元件側表面上的步驟之前，該製程包括藉由表面化將包含該些元件之該晶圓的表面薄化的一步驟。
有助益地，L2<L1。
根據本發明之一特徵，步驟A2的堆疊係在一支撐上實行並且該製程包括，在金屬化步驟C2之後，沿著第三溝槽切割此支撐的步驟，以獲得n個三維電子模組。
該電子元件係一主動元件或被動元件或一MEMS(微機電系統)。
三維電子模組包含K個電子晶粒50的堆疊。一晶粒i，i係從1至K改變，包含在絕緣基板4上的至少一電子元件11。一元件典型地具有一厚度介於50微米與500微米之間。該元件可為一主動元件，例如一晶片(二極體、電晶體、積體電路等)，或一傳統被動元件，例如一電容。該元件也可為蝕刻於矽中的被動元件，以術語MEMS(微機電系統)已知，其提供下列類型的功能：感測器、驅動器、開關等。MEMS係設置於藉由一遮罩所保護的孔穴中。
該K個晶粒係經由位於該堆疊之側表面上的導體而電性連接一起。K係例如等於4，但是典型地係在2與100之間改變。
本發明係關於僅具有該些合格元件之n模組的製造(n係根據該些元件尺寸而介於2及100之間)，此製造係集體式。
該製程包含在一個以及相同的晶圓上製造一批次n個晶粒i的步驟，此步驟被重覆K次，並接著為堆疊該K個晶圓以及在該堆疊的厚度中形成溝槽的步驟，其係意欲將該晶粒連接在一起，以獲得該n個三維模組。
一批次n晶粒i係在關於圖2至8所描述的幾個次步驟之後而獲得。
厚度es 之薄平面的包含矽之晶圓10以稱為測試墊的電性連接墊20覆蓋在一表面上，並接著以幾微米厚度ei 的薄電性絕緣層覆蓋，形成該絕緣基板4，該絕緣層設置有至少n個矽電子元件11，連接於連接墊2’之連接墊2或凸塊通過該絕緣層(圖2及3)而連接於該些測試墊。薄絕緣層4例如由可光蝕刻絕緣樹脂所製成。該些元件11係以主動面朝向基板而接合於絕緣基板上，該接合係利用熔化其凸塊或金柱植球的浮動晶片法。此金柱植球製程在於利用熟知為金線接合之熱音波法接合金球。
該些元件被封裝於厚度er 之絕緣樹脂6中，該絕緣樹脂充填該些元件11間及該些元件與絕緣層4之間的空間(圖3)。
該厚度ei 係典型地介於5與20微米之間，並且er 係介於50至500微米之間。
晶圓10的厚度為幾百微米。該些被動元件已視需要地在晶圓中的上部分中，其深度大約10－20微米。該晶圓10提供用於製造該批次n個晶粒i的連續性支撐。此係例如具有直徑大約25公分的圓形晶圓。
為了對每個元件做電性測試，接著該些元件係藉由具有一寬度L1及一深度P1之第一溝槽30彼此互相分隔，使得ei ＋er <P1<ei ＋er ＋es 。這些切割深入絕緣樹脂6中的溝槽係例如藉由鋸開而獲得(圖4)。典型地，L1係在25及75微米之範圍內。該些元件的連接墊2被連接於元件的電性互連單元，如與這些溝槽30齊平的該些軌3。於該些圖中，該些軌道係與測試墊20等高，但是彼等也可與連接墊2’等高。
較佳地，製程因此包括將設置有元件之晶圓薄化的步驟，該薄化係藉由將元件側面上的晶圓非均質表面化，也就是說藉由非選擇性地施加表面化於該些元件11及視需要地施加於封裝該些元件的絕緣樹脂6二者。例如藉由抛光來實行的此表面化作業係由圖5中的箭號指出。通常，術語〝晶圓〞表示由製造製程進行所獲得的整體結構。該集體式表面化可在第一溝槽產生之前實行。該表面化係藉由機械或化學磨蝕來實行。接著具有晶圓元件的晶圓厚度被減低。
一黏著支撐40沉積於具有該元元件11的側面上，於視需要表面化之表面上，並移除該起始的矽晶圓10，例如藉由化學蝕刻，以便露出該些測試墊20(圖6)。該黏著支撐可為黏著片，如例聚氯乙烯薄片，一般稱為鼓皮，其可被去接合而不用任何特殊的處理，例如藉由剝離。該薄片使得免除需要加熱處理以固化黏著劑及酸化學處理以移除之元件的黏著接合變成可能。在此步驟之後，晶圓具有大約100微米的厚度，通常更介於50微米與200微米之間。
晶圓的該些元件接著以該些測試墊20方式電性測試，並且根據彼等是否合格或有缺陷而做記號。該測試係由圖7中的箭號指出。此記號可僅在於設定撤銷有缺陷的晶粒。該術語〝合格晶粒〞代表包含連接於該些測試墊20及連接於至少一導電軌3、絕緣樹脂6及一絕緣層4的一合格元件11’之單元。於此方式，該測試係集體式實行，而不是個別在每個模組上所獲得。
該合格的測試晶粒自晶圓的黏著支撐40分離，並接合於另一基板41上，如上述的另一黏著薄膜類型，以便重建僅具有合格元件11’的第二晶圓，其被稱為〝已知的良品晶圓〞(圖8)。將該些晶粒與基板41接合，以便留下最少的晶粒間的空間而便於在每單位面積放置最多數目的晶粒。這些分隔空間形成寬度L2之溝槽31，其中較佳地L2<L1，該溝槽與連接於該些元件之連接墊2的軌3齊平。沒有任何樹脂沉積於這些溝槽31中。
以獲得K個已知的良品晶圓為目的，將此批次n個晶粒50之集體式製造重覆k次。
第二步驟包含關於圖9至12所描述的次步驟，該步驟在於堆疊於第一步驟之後所獲得的K批次已知的良品晶圓，如在圖9中以K＝4說明，以便實質上一個在另一個上來疊置每一批次的該些第二溝槽31。該些晶圓係藉由例如黏著劑方式以一個在另一個上來堆疊。較佳地，該堆疊係產生於黏著支撐42或鼓皮上，具有大約25微米厚度。第二溝槽較佳地但非必須地具有相同的維度。該些第三溝槽32接著形成於與溝槽31垂直之堆疊的整個厚度，具有大於L2，小於L1之寬度L3(圖10)，使得軌3與這些第三溝槽之壁齊平。這些溝槽係例如藉由鋸開而獲得。
該些溝槽32之橫向維度L3大於L2且較佳地大於L1，一方面彌補當堆疊K批次已知的良品晶圓時之失準值，並且另一方面使得連接於該些元件之連接墊的該些軌3與該些溝槽齊平。L3係例如介於50微米與100微米之間。
接著該些溝槽32之壁係藉由化學及/或電氣化學沉積或藉由真空濺鍍而以一金屬層33金屬化(圖11)，所有軌道的短路終止於孔洞之壁上。該視需要之黏著支撐42於孔洞32之延伸中被切除，以便獲得n個電子模組。例如，此切口係藉由鋸開來實行。
例如藉由雷射來蝕刻n個模組之步驟適用於隔開該軌道組，以形成晶粒互連結構(圖12)。在此步驟之後，獲得該些n三維模組100，其中的一實例顯示於圖12。此蝕刻有利於集體式實行。就該目的而言，在此蝕刻之前，模組係對照著藉由三角板所形成的兩個參考邊緣來堆疊(例如大約100個模組)。
2．．．連接單元
2’．．．連接墊
3．．．軌
4．．．絕緣基板
6．．．絕緣樹脂
7．．．晶粒之邊緣
10．．．矽晶圓
11．．．主動或被動元件
20．．．測試墊
30．．．第一溝槽
31．．．第二溝槽
32．．．第三溝槽
33．．．金屬層
40．．．黏著支撐
41．．．黏著膜
42．．．支撐
50．．．晶粒
100．．．電子模組
本發明的其他特徵及益處將在閱讀下列以非侷限之實施例方式所提供的詳細敘述及參照所附圖形而更加明白，其中：圖1，已如上敘述，係以圖式顯示根據先前技藝的一三維電子模組之電子晶粒的剖面視圖；圖2係以圖式顯示用於根據本發明的三維電子模組之集體式製造的製程的第一步驟的剖面視圖；圖3係以圖式顯示根據本發明之製程的第二步驟的剖面視圖，也就是裝置該些元件的步驟；圖4係以圖式顯示根據本發明之製程的第三步驟的剖面視圖，也就是切割第一溝槽的步驟；圖5係以圖式顯示根據本發明之製程的第四步驟的剖面視圖，也就是表面化的步驟；圖6係以圖式顯示根據本發明之製程的第五步驟的剖面視圖，也就是化學蝕刻矽晶圓的步驟；圖7係以圖式顯示根據本發明之製程的第六步驟的剖面視圖，也就是電性測試該些元件的步驟；圖8係以圖式顯示根據本發明之製程的第七步驟的剖面視圖，也就是重建僅具有合格元件的新晶圓的步驟；圖9係以圖式顯示根據本發明之製程的第八步驟的剖面視圖，也就是堆疊該已重建之晶圓的步驟；圖10係以圖式顯示根據本發明之製程的第九步驟的剖面視圖，也就是切割第二溝槽的步驟；圖11係以圖式顯示根據本發明之製程的第十步驟的剖面視圖，也就是金屬化第二溝槽的步驟；以及圖12係以圖式顯示根據本發明之製程的第十一步驟的剖面視圖，也就是蝕刻該些n模組之側表面的步驟。
從一圖式至另一圖式，相同的元件係由相同的參考編號辨別。

Claims (8)

  1. 一種用於n個電子模組(100)之製造的製程，n係大於1的一整數，一模組包含K個電子晶粒(50)的堆疊，一晶粒i，i係從1至K改變，包含在一絕緣基板(4)上的至少一電子元件(11)，該K個晶粒係藉由位於該堆疊之側表面上的導體而電性連接一起，其特徵在於該製造是集體式的並且包含：針對每個晶粒i，第一步驟係由下列組成：A1)在一個以及厚度es 之相同薄平面的包含矽之晶圓(10)上製造一批次n個晶粒i的步驟，以稱為測試墊的電性連接墊(20)覆蓋在一表面上，並接著以厚度ei 的薄電性絕緣層(4)覆蓋，該絕緣層形成該絕緣基板並且設置有至少一矽電子元件(11)，該矽電子元件包含通過該絕緣層連接於該些測試墊(20)之連接墊(2)，該些元件被封裝於厚度er 之絕緣樹脂(6)中，該絕緣樹脂充填該些元件間的空間，接著藉由具有一寬度L1及一深度P1之第一溝槽(30)彼此互相分隔使得ei ＋er <P1<ei ＋er ＋es ，該些元件的該些連接墊(2)連接於與該些溝槽(30)齊平的軌(3)；B1)沉積一黏著支撐(40)於該元件側表面上的步驟；C1)移除該矽晶圓(10)以便露出該些測試墊(20)的步驟；D1)經由該些測試墊(20)來電性測試該晶圓的該些元件以及標示該些合格元件(11’)及/或缺陷元件的步驟；以及E1)將該些晶粒(50)接合至一黏著膜(41)上的步驟，每個晶粒包含連接於測試墊(20)以及連接於至少一軌(3)、絕緣樹脂(6)、和一絕緣層(4)的一合格元件(11’)，該些晶粒藉由寬度L2之第二溝槽(31)而被分隔，該些合格元件(11’)之連接軌(3)與該些第二溝槽齊平；以及第二步驟係由下列組成：A2)堆疊及裝配在該第一步驟之後所獲得的該些K批次，以便實質上一個在另一個上來疊置該些第二溝槽(31)；B2)在該些第二溝槽上，在該些堆疊中形成具有一寬度L3≧L2的第三溝槽(32)；以及C2)將該些第三溝槽(32)之壁上的該些晶粒互連。
  2. 如申請專利範圍第1項之製程，其中L2<L1。
  3. 如申請專利範圍第1或第2項之製程，其中該製程包括：在沉積一黏著支撐於該元件側表面上的步驟之前，藉由表面化將包含該些元件之該晶圓的表面薄化的步驟。
  4. 如申請專利範圍第1或第2項之製程，其中步驟C2包含由下列所組成的步驟：－藉由一金屬層(33)將該些第三溝槽之壁金屬化；以及－在該金屬層中形成一晶粒互連結構。
  5. 如申請專利範圍第1或第2項之製程，其中步驟A2之該堆疊係在一支撐(42)上實行。
  6. 如申請專利範圍第1或第2項之製程，其中該電子元件(11)係一主動或被動元件或一微機電系統(MEMS)。
  7. 如申請專利範圍第6項之製程，其中該主動元件為一晶片。
  8. 如申請專利範圍第1或第2項之製程，其中至少一被動元件係位於該晶圓(10)中或該晶圓上。
TW096130739A 2006-08-22 2007-08-20 用於三維電子模組之集體式製造的製程 TWI392054B (zh)

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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2923081B1 (fr) * 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
FR2943176B1 (fr) 2009-03-10 2011-08-05 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
CN102023236A (zh) * 2009-09-11 2011-04-20 中芯国际集成电路制造(上海)有限公司 测试结构及测试方法
US8012802B2 (en) * 2010-02-04 2011-09-06 Headway Technologies, Inc. Method of manufacturing layered chip package
US9093457B2 (en) 2012-08-22 2015-07-28 Freescale Semiconductor Inc. Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
US9064977B2 (en) 2012-08-22 2015-06-23 Freescale Semiconductor Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9190390B2 (en) 2012-08-22 2015-11-17 Freescale Semiconductor Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US8518741B1 (en) 2012-11-07 2013-08-27 International Business Machines Corporation Wafer-to-wafer process for manufacturing a stacked structure
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9524950B2 (en) 2013-05-31 2016-12-20 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
WO2015044523A1 (en) * 2013-09-27 2015-04-02 Tactotek Oy Method for manufacturing an electromechanical structure and an arrangement for carrying out the method
US9036363B2 (en) 2013-09-30 2015-05-19 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication
US9025340B2 (en) 2013-09-30 2015-05-05 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication
US9263420B2 (en) 2013-12-05 2016-02-16 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication
US9305911B2 (en) 2013-12-05 2016-04-05 Freescale Semiconductor, Inc. Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication
US10388607B2 (en) 2014-12-17 2019-08-20 Nxp Usa, Inc. Microelectronic devices with multi-layer package surface conductors and methods of their fabrication
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
FR3048123B1 (fr) 2016-02-19 2018-11-16 3D Plus Procede d'interconnexion chip on chip miniaturisee d'un module electronique 3d
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
FR3053158B1 (fr) * 2016-06-22 2018-11-16 3D Plus Procede de fabrication collective de modules electroniques 3d configures pour fonctionner a plus d'1 ghz
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
IT201800001092A1 (it) 2018-01-16 2019-07-16 St Microelectronics Srl Sensore di pressione piezoresistivo microelettromeccanico con capacita' di auto-diagnosi e relativo procedimento di fabbricazione
JP7258906B2 (ja) * 2018-03-15 2023-04-17 アプライド マテリアルズ インコーポレイテッド 半導体素子パッケージ製造プロセスための平坦化
RU2745338C1 (ru) * 2020-08-05 2021-03-24 Общество с ограниченной ответственностью "Маппер" Способ соединения кремниевых пластин микроэлектромеханических систем с изоляционным слоем диоксида кремния между ними
CN113793811B (zh) * 2021-11-16 2022-02-15 湖北三维半导体集成创新中心有限责任公司 芯片堆叠结构的连接方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809367B2 (en) * 1999-12-15 2004-10-26 3D Plus Device for interconnecting, in three dimensions, electronic components

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2403688A1 (fr) 1977-09-16 1979-04-13 Thomson Csf Dispositif attenuateur reglable
FR2456388A1 (fr) 1979-05-10 1980-12-05 Thomson Brandt Microboitier de circuit electronique, et circuit hybride comportant un tel microboitier
FR2485262A1 (fr) 1980-06-19 1981-12-24 Thomson Csf Boitier d'encapsulation resistant a de fortes pressions externes
FR2485796A1 (fr) 1980-06-24 1981-12-31 Thomson Csf Resistance electrique chauffante et tete d'imprimante thermique comportant de telles resistances chauffantes
FR2525815B1 (fr) 1982-04-27 1985-08-30 Inf Milit Spatiale Aeronaut Substrat composite a haute conduction thermique et application aux boitiers de dispositifs semi-conducteurs
FR2527039A1 (fr) 1982-05-14 1983-11-18 Inf Milit Spatiale Aeronaut Dispositif de protection d'un dispositif electronique contre les tensions engendrees par un champ electromagnetique
FR2538618B1 (fr) 1982-12-28 1986-03-07 Inf Milit Spatiale Aeronaut Boitier pour composant electronique comportant un element fixant l'humidite
FR2547113B1 (fr) 1983-06-03 1986-11-07 Inf Milit Spatiale Aeronaut Boitier d'encapsulation de composant electronique, durci vis-a-vis des radiations
FR2550009B1 (fr) 1983-07-29 1986-01-24 Inf Milit Spatiale Aeronaut Boitier de composant electronique muni d'un condensateur
US5237204A (en) 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
FR2591801B1 (fr) 1985-12-17 1988-10-14 Inf Milit Spatiale Aeronaut Boitier d'encapsulation d'un circuit electronique
FR2614134B1 (fr) 1987-04-17 1990-01-26 Cimsa Sintra Procede de connexion d'un composant electronique pour son test et son montage, et dispositif de mise en oeuvre de ce procede
FR2666190B1 (fr) 1990-08-24 1996-07-12 Thomson Csf Procede et dispositif d'encapsulation hermetique de composants electroniques.
US5847448A (en) 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
FR2674680B1 (fr) 1991-03-26 1993-12-03 Thomson Csf Procede de realisation de connexions coaxiales pour composant electronique, et boitier de composant comportant de telles connexions.
FR2688629A1 (fr) 1992-03-10 1993-09-17 Thomson Csf Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices.
FR2688630B1 (fr) 1992-03-13 2001-08-10 Thomson Csf Procede et dispositif d'interconnexion en trois dimensions de boitiers de composants electroniques.
FR2691836B1 (fr) 1992-05-27 1997-04-30 Ela Medical Sa Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant.
KR100310220B1 (ko) * 1992-09-14 2001-12-17 엘란 티본 집적회로장치를제조하기위한장치및그제조방법
FR2696871B1 (fr) 1992-10-13 1994-11-18 Thomson Csf Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant.
FR2709020B1 (fr) 1993-08-13 1995-09-08 Thomson Csf Procédé d'interconnexion de pastilles semi-conductrices en trois dimensions, et composant en résultant.
FR2719967B1 (fr) 1994-05-10 1996-06-07 Thomson Csf Interconnexion en trois dimensions de boîtiers de composants électroniques utilisant des circuits imprimés.
JP2000252411A (ja) 1999-03-03 2000-09-14 Mitsui High Tec Inc スタックド半導体装置及びその製造方法
EP1041620A3 (en) * 1999-04-02 2005-01-05 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultrathin substrates and application of the method to the manufacture of a multi-layer thin film device
JP3879351B2 (ja) * 2000-01-27 2007-02-14 セイコーエプソン株式会社 半導体チップの製造方法
FR2805082B1 (fr) 2000-02-11 2003-01-31 3D Plus Sa Procede d'interconnexion en trois dimensions et dispositif electronique obtenu par ce procede
JP3651362B2 (ja) * 2000-05-24 2005-05-25 松下電器産業株式会社 半導体装置の製造方法
FR2812453B1 (fr) 2000-07-25 2004-08-20 3D Plus Sa Procede de blindage et/ou de decouplage repartis pour un dispositif electronique a interconnexion en trois dimensions , dispositif ainsi obtenu et procede d'obtention de celui- ci
JP4361670B2 (ja) * 2000-08-02 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置
FR2832136B1 (fr) 2001-11-09 2005-02-18 3D Plus Sa Dispositif d'encapsulation hermetique de composant devant etre protege de toute contrainte
FR2857157B1 (fr) 2003-07-01 2005-09-23 3D Plus Sa Procede d'interconnexion de composants actif et passif et composant heterogene a faible epaisseur en resultant
FR2875672B1 (fr) 2004-09-21 2007-05-11 3D Plus Sa Sa Dispositif electronique avec repartiteur de chaleur integre
FR2884049B1 (fr) 2005-04-01 2007-06-22 3D Plus Sa Sa Module electronique de faible epaisseur comprenant un empilement de boitiers electroniques a billes de connexion
FR2894070B1 (fr) 2005-11-30 2008-04-11 3D Plus Sa Sa Module electronique 3d
FR2895568B1 (fr) 2005-12-23 2008-02-08 3D Plus Sa Sa Procede de fabrication collective de modules electroniques 3d

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809367B2 (en) * 1999-12-15 2004-10-26 3D Plus Device for interconnecting, in three dimensions, electronic components

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US7951649B2 (en) 2011-05-31
TW200826229A (en) 2008-06-16
EP2054929B1 (fr) 2016-03-16
FR2905198A1 (fr) 2008-02-29
JP5433899B2 (ja) 2014-03-05
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