1294260 九、發明說明： 【發明所屬之技術領域】 ,發明係有關於一種半導體元件埋入承載板之結構 „ ’尤指一種半導體元件之非主動面形成凹部再埋 入承載板之結構及其製法。 【先前技術】 ，見代各式電子產品輕薄短小化之發展趨勢，半導體 t 阿么度之封叙電路板中以因應此 一％勢。 〜閱第1圖’係為習知—半導體元件埋人電路板之 結構之剖視圖，係和括·坐 朴區飞 係包括·+導體兀件11、承載板12及黏 :二t其中，該承載板12係為一電路板或絕緣板，且 : :秦表面i2a及第二表面12b，並形成有至少一貫 第〜表面12a及第二表面12b之開口 12〇，於該承載 第表面12b形成該黏著層13，而該半導體元件 11具有^動面山及相對於該主動面lla之非主動面 jib’於該主動面Ua上形成有複數電性連接墊HQ，並使 该半導體元件11之非 <非主動面lib接置於該黏著層13表 面’且該黏著層13係填充於該承載板12與半導體元件u 1隙中俾以將5亥半導體元件工】目著於該承載板12之 開口 120中。 、> :、、;、而對於4述之結構而言，埋設於該承載板12之 半導體元件11係藉由黏著層13結合在該開口 120中，由 於與遠黏著層13黏接之半導體元件u之非主動面…係 19407 5 1294260 爲平滑的表面，導致該半導體元件u與該黏著層13之結 合強度不尚，使得後續製程中，該半導體元件u與該黏著 層 1,3 易因膨脹係數（Coefficient 〇f thermal expansi〇n，CTE厂 之差異因而產生分層的現象，同時亦降低該半導體元件丨丨-/、承載板12之 '纟σ合強度’而此種分層現象及結合強度的降 低會直接影響半導體產品的良率及可靠度，因此限制半導 體元件埋入承載板以形成構裝件之發展。 因此，如何降低半導體元件與黏著層之分層可能性， 進而提昇半導體元件與電路板之結合性，已成為目前半導 體業界之重要課題。 【發明内容】 鑑於前述習知技術之缺失，本發明之主要目的係在提 供-種半導體元件埋人承載板之結構及其製法，得降低半 導體元件與黏著層之分層可能性，進而提昇半導體元件與 承載板之結合性。 本發明之另一目的，係在提供一種半導體元件埋 ，板之結構及其製法’得利於後續之半導體製程，進而 昇產品良率及可靠度。 為達上述目的及其他相關之目的，本發明係 半導體元件埋人承載板之結構之製法，係包括：提供:承^ 反及至少一半導體元件，該承載板具有相對之第— 表面’以及至少一貫穿該第一與第二表面之開口，而、： 導體元件具有主動面及相對該主動面之非主動面，於：： 動面上設有複數電極墊，且於該非主動面上形成有複數凹 19407 6 !294260 、:口載板:第二表面形成-黏著層以封住該承载板 中，並传Γ 該半導體元件容置於該承载板之開口 上，且=形成有複數凹部之非主動面接置於該黏著層 與半導體元件之間隙中。 狀凹。卩以承载板 成二=1"復可將一例如金屬層之保護層形 黏者層之外表面；且該半導體元件之凹部 2具所切割或經由蘭而形成之溝槽，传為刀 者槽，:::槽、斜向溝槽及交又溝槽所組群組之= 者，该+導體元件係為主動元件 甲 介電層或黏著材料。 ο者k係為一 又t發明之製法，復包括於該承载板之 …件之主動面形成一線路增 !:形成有複數個導電結構以電性連接至該; 表㈣成有電性連接塾+ ::線路增層結構表面形成—防焊層，且該防焊 且 而該線路增層結構包括有;::==連她 路層，以及形成於該介電層中之導介電層上之線 ~括本1=提供—種半導體元件埋人承载板之結構，# 板:係具有相對之第-表面與第二表面以:、 /貝牙5亥乐一與第二表面之開口；至少一半導辦— 件，係置於該開口中，該半導體元件具有相對之主動:及 19407 7 1294260 1主動面’於該主動面上設有複數電極墊，且於該非 =上設有複數凹部；以及—黏著層，係形成於該承裁板之 弟:表面及該半導體元件之非主動面，且填充於 ;件之凹部及該承載板之貫穿開口與半導體元件之間Γ 該半導體it件之非主動面的凹部係為由㈣刀 切割或經由姓刻而形成之溝槽，且該溝槽 意 _縱向溝槽、斜向溝槽、交叉溝槽所組成群組之、 因此，透過本發明之半導體元件埋入承载及 製^中，係先於半導體元件之非主動面形成複數凹:= 错由黏者層填充於該半導體元件之凹部，及該承 口與半導體元件之間隙中，以將該半導體元件固著 板之中。由於該半導體元件之非主動面具有凹部，此： 加了半導體元件與黏著層之結合面積，亦即，提曰 體=件與黏著層間之結合力，因而於後續之半導體气= 可：度驗證中’埋入承載板之半導體元件即不易因二: 層膨脹係數（CTE)差異過大（即應力過大）而 、厚 離的現象。 ♦双刀層剝 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之 ^ 暸解本發明之其他優點與功效。 輕易地 元 請參閱第2A圖至第2E圖詳細説明本發明之 件埋入承載板之結構之製法。 、豆 19407 8 1294260 · 首先，睛芩閱第2A及圖，其顯示本發明所提供之 -承，板21及半導體元件22;其中，該承載板21具有相 對之第一表面21a與第二表面21b，以及至少一貫穿該第 一表面21a與第二表面2lb之開口 21〇，而該半導體元件 22>具有主動面22&及相對該主動面22a之非主動面22b， 且及主動面22a上设有複數電極墊22〇;該半導體元件 係為主動το件或被動疋件，而該承載板21係為一絕緣 板、金屬板或是具有線路之電路板。 另於該半導體元件22之非主動面22b形成複數凹部 22卜且於該承載板21之第二表面m形成一係如介電声 或黏著材料之黏著層23以封住該承載板開n21G之一端。 前述形成於該半導體元件22之非主動面咖之 =係經由機械式或雷射光之切割刀具切割或經由蝕刻而 =成之溝槽’該溝槽可以為橫向溝槽、縱向溝槽、斜向溝 槽、交叉溝槽、亦或為前述溝槽所組群組，但盆 非 ,以前述爲限，且該溝槽之大小及位 ;1並非 性變換。 置力』依只際需求而彈 請參閲第2C圖，將該半導體元件22 2!之開口 210中，並使該半導體元件22 、、义承载板 221之非主動面22b接置於該黏著層u +稷文凹部 件22具有主動面22a復可形成有保護層㈤半：體= 合製程使該黏著層23填充於該半導體"不’猎由壓 及該承載板21之開口21〇與半導體元件=部如 將該半導體元件22固定於該 /中’俾 丄之開口 210中，移 19407 9 1294260 除保護層以露出該半導體元件22之主動面22a。 由於該半導體元件22之非主動面22b具有凹部221 使該半導體元件22藉由該凹部221以增加與該黏著層u 之結合性，以避免膨脹係數（CTE)差異過大導致分層 的現象。 此外，請參閱第2D圖，另於該黏著 形成一例如金屬層之保護層24 接著，請參閲第2E圖，復於該承載板21之第一表 21a及該半導體元件22之主動面22&形成一線路增層結 25，δ亥線路增層結構25包括有介電層⑸、疊置於該介電 运51上之線路層252，以及形成於該介電層251中之 2電2=^執且該導電結構253電性連接至該半導體元件 連接墊2Μ 22G’亚於該線路增層結構25表面形成有電性 連接墊乃4,又於該線路增層結構25表面形成一防焊層 ，且邊防焊層26表面具有複數個開孔 路增層結構25之電性遠拯執评以顯路線 電性連接千 亥電性連接墊254係供 以電性1二：：^件(圖式中未表示)，藉由該導電元件 Μ冤性其它電子裝置。 承载板之:ί ’本發明亦揭示一種半導體元件埋入 :板之、，、。構，如第2D圖所示， 承载板21，係如絕鏠妃人斤 受你匕括· 且u 、、板、孟屬板或是具有線路之電路板， 且该承载板21具有相對之第一表面 . 以及至少一貫穿該第 表面加’ 加；至少-係如 表面21b之開口 動兀件或被動元件之半導體元件22， 19407 10 1294260 · 及半V體元件22具有相對之主動面22a及非主動面22b， 於忒主動面22a設複數電極墊22〇，且於該非主動面22b 设有複數凹部221，而該半導體元件22係以其非主動面22b 容置於該承載板21之開口 210中；以及一黏著層23係形 成於該承載板21之第二表面21b及該半導體元件22之非 主動面22b ’且填充於該半導體元件22之凹部221及該承 載板21之開口 210與半導體元件22之間隙中，俾以將該 丨半導體元件22固定於該承載板21之開口 21〇中。 •因此，透過本發明之半導體元件埋入承載板之結構及 製法，係先於半導體元件之非主動面形成複數凹部，再藉 由填充於該半導體元件之凹部，及該承載板開口與半導體 元件之間隙中的黏著層以將該半導體元件固著於承載板 中。由於該半導體元件之非主動面具有凹部，而可增加了 半導體元件與黏著層之結合面積，提高半導體元件與黏著 層之間的結合性，進而提升半導體元件與承載板間之結合 (力。因而於後續之線路增層等半導體製程及可靠度檢測口 中，埋入該承載板中之半導體元件即不易因與黏著層膨脹 係數（CTE)差異過大導致分層現象，以利於半導體元件埋 入承載板結構以形成構裝件之發展。 上述貫施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟悉此項技藝之人士均可在不違 月本發明之精神及範嚀下，對上述實施例進行修飾與改 變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 19407 11 Ϊ294260 【圖式簡單說明】 第1圖係為習知一半導體元件埋入承載板之結構之剖 視圖；以及 第2A至2E圖係為本發明之半導體元件埋入承載板之 結構及其製法之製造流程剖視圖。 【主要元件符號說明】 11、22 半導體元件 11a、22a 主動面 11b 、 22b 非主動面 110 、 254 電性連接墊 12、21 承载板 12a、21a 第一表面 12b 、 21b 第二表面 120 、 210 開〇 13、23 黏著層 220 電極塾 221 凹咅[5 24 保護層 25 線路增層結構 251 介電層 252 線路層 253 導電結構 26 防焊層 260 開孔 12 194071294260 IX. Description of the invention: [Technical field to which the invention pertains] The invention relates to a structure in which a semiconductor element is embedded in a carrier plate „', particularly a structure in which a non-active surface of a semiconductor element is formed into a recess and then embedded in a carrier plate, and a method of manufacturing the same [Prior Art], see the development trend of light and thin electronic products on various generations, the semiconductor t-how of the circuit board to respond to this one potential. ~ Read Figure 1 'is a well-known semiconductor components A cross-sectional view of the structure of the buried circuit board, the system and the cover of the flying area include: + conductor member 11, the carrier plate 12 and the adhesive: two, wherein the carrier 12 is a circuit board or an insulating board, and : : Qin surface i2a and second surface 12b, and formed with at least a first surface 12a and an opening 12 of the second surface 12b, the adhesive layer 13 is formed on the carrying surface 12b, and the semiconductor element 11 has a moving A plurality of electrical connection pads HQ are formed on the active surface Ua with respect to the inactive surface jib' of the active surface 11a, and the non-active surface lib of the semiconductor component 11 is placed on the adhesive layer. 13 surface 'and this The adhesive layer 13 is filled in the gap between the carrier 12 and the semiconductor device u 1 to view the opening of the carrier board 12 in the opening 120 of the carrier board 12, > In the structure, the semiconductor device 11 embedded in the carrier 12 is bonded to the opening 120 by the adhesive layer 13. The inactive surface of the semiconductor component u bonded to the far adhesive layer 13 is 19407 5 1294260. The smooth surface causes the bonding strength between the semiconductor element u and the adhesive layer 13 to be insufficient, so that the semiconductor element u and the adhesive layer 1, 3 are susceptible to expansion coefficient (Coefficient 〇f thermal expansi〇n, CTE) in the subsequent process. The difference in the factory thus causes delamination, and at the same time reduces the '纟σ combination strength' of the semiconductor device 丨丨-/, the carrier plate 12, and the delamination phenomenon and the reduction of the bonding strength directly affect the yield of the semiconductor product. And reliability, thus limiting the development of the semiconductor component buried in the carrier plate to form the structure. Therefore, how to reduce the possibility of delamination of the semiconductor component and the adhesive layer, thereby improving the combination of the semiconductor component and the circuit board The invention has become an important subject in the semiconductor industry. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a structure of a buried semiconductor carrier and a method for manufacturing the same, which can reduce the semiconductor component and adhesion. The layering possibility of the layer further enhances the bonding between the semiconductor component and the carrier board. Another object of the present invention is to provide a semiconductor component buried, the structure of the board and the method of manufacturing the same, which is beneficial to the subsequent semiconductor process, and further enhances the product. The invention relates to a method for fabricating a semiconductor component buried carrier board for the above purposes and other related purposes, comprising: providing: a semiconductor component, the carrier board having a relative a first surface and at least one opening extending through the first and second surfaces, wherein: the conductor element has an active surface and an inactive surface opposite to the active surface, and: a plurality of electrode pads are disposed on the movable surface, and The inactive surface is formed with a plurality of recesses 19407 6 ! 294260, the carrier plate: the second surface forms an adhesive layer to seal the carrier plate, And transmitting the semiconductor component to the opening of the carrier, and the inactive surface formed with the plurality of recesses is placed in the gap between the adhesive layer and the semiconductor component. Concave.卩 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载The groove, the ::: groove, the oblique groove, and the group of the intersecting groove are the active element A dielectric layer or the adhesive material. o is a method of inventing the invention, and the active surface of the member included in the carrier plate forms a line increase!: a plurality of conductive structures are formed to be electrically connected thereto; the table (4) is electrically connected塾+::::::::========================================================= The line on the layer ~ Included 1 = provides the structure of a semiconductor component buried carrier board, #板: has a relative first surface and a second surface to: / / 贝牙5海乐一与第二表面An opening; at least half of the guiding member is placed in the opening, the semiconductor component has a relative active: and 19407 7 1294260 1 active surface 'on the active surface is provided with a plurality of electrode pads, and is provided on the non-= a plurality of recesses; and an adhesive layer formed on the surface of the panel: the surface and the inactive surface of the semiconductor component, and filled in the recess of the component and the through opening of the carrier and the semiconductor component The concave portion of the inactive surface of the it piece is formed by (4) knife cutting or by surname a trench, and the trench is composed of a group of longitudinal trenches, oblique trenches, and intersecting trenches. Therefore, the semiconductor device of the present invention is embedded in the carrier and the device, which is preceded by the semiconductor device. The active surface forms a plurality of recesses: = the recess is filled in the recess of the semiconductor element by the adhesive layer, and the gap between the socket and the semiconductor element is fixed in the semiconductor element. Since the inactive surface of the semiconductor component has a recess, the bonding area between the semiconductor component and the adhesive layer is added, that is, the bonding force between the soldering body and the adhesive layer is performed, so that the subsequent semiconductor gas can be verified. The semiconductor component embedded in the carrier plate is not easy to be due to the fact that the difference in layer expansion coefficient (CTE) is too large (ie, the stress is too large) and the thickness is too large. ♦ Double-Plate Stripping [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments, and those skilled in the art can understand the other advantages and effects of the present invention. Easily, please refer to Figs. 2A to 2E for a detailed description of the method of fabricating the structure of the embedded carrier of the present invention. Beans 19407 8 1294260. First, the second and the drawings, which show the present invention, the board 21 and the semiconductor component 22; wherein the carrier board 21 has opposite first and second surfaces 21a and 21, 21b, and at least one opening 21〇 extending through the first surface 21a and the second surface 21b, and the semiconductor element 22 has an active surface 22& and an inactive surface 22b opposite to the active surface 22a, and an active surface 22a A plurality of electrode pads 22 are provided; the semiconductor component is an active component or a passive component, and the carrier 21 is an insulating plate, a metal plate or a circuit board having a line. In addition, a plurality of recesses 22 are formed on the inactive surface 22b of the semiconductor component 22, and an adhesive layer 23 such as a dielectric acoustic or adhesive material is formed on the second surface m of the carrier board 21 to enclose the carrier board opening n21G. One end. The inactive surface formed on the semiconductor element 22 is cut by a mechanical or laser cutting tool or by etching. The groove may be a lateral groove, a longitudinal groove, or an oblique direction. The trenches, the intersecting trenches, or the group of the trenches are grouped, but the basin is not limited to the foregoing, and the size and position of the trenches are not qualitatively changed. The force is applied according to the requirement of the second embodiment. Referring to FIG. 2C, the semiconductor element 22 and the inactive surface 22b of the semiconductor carrier 22 are attached to the opening 210. The layer u + 稷 concave member 22 has an active surface 22a formed with a protective layer (five) half: the body = the process of making the adhesive layer 23 filled in the semiconductor "not hunted by the opening 21 of the carrier plate 21〇 If the semiconductor element 22 is fixed in the opening 210 of the semiconductor element 22, the 19407 9 1294260 is removed to remove the active layer 22a of the semiconductor element 22. Since the inactive surface 22b of the semiconductor element 22 has the concave portion 221, the semiconductor element 22 is increased in bonding with the adhesive layer u by the concave portion 221 to avoid delamination due to excessive difference in expansion coefficient (CTE). In addition, referring to FIG. 2D, a protective layer 24 such as a metal layer is formed on the adhesive layer. Next, referring to FIG. 2E, the first surface 21a of the carrier board 21 and the active surface 22& of the semiconductor element 22 are applied. Forming a line build-up junction 25, the δ-Hay line build-up structure 25 includes a dielectric layer (5), a wiring layer 252 stacked on the dielectric layer 51, and a second layer 2 formed in the dielectric layer 251 The conductive structure 253 is electrically connected to the semiconductor device connection pad 2 22G'. The surface of the circuit build-up structure 25 is formed with an electrical connection pad 4, and an anti-layer is formed on the surface of the circuit build-up structure 25. The solder layer, and the surface of the edge solder resist 26 has a plurality of open-hole thickening structures 25. The electrical far-reaching evaluation is to electrically connect the Qianhai electrical connection pads 254 to provide electrical properties. (Not shown in the drawings), by means of the conductive element, other electronic devices are used. The carrier board: ί ' The invention also discloses a semiconductor component embedded: a board, a,. As shown in FIG. 2D, the carrier board 21 is such as a board that has been smashed by you, and is a board, or a circuit board having a line, and the carrier board 21 has a relative a first surface. and at least one semiconductor element 22 extending through the first surface; at least - an opening or passive element such as surface 21b, 19407 10 1294260 and a half V body element 22 having opposing active faces 22a And the inactive surface 22b, the plurality of electrode pads 22A are disposed on the active surface 22a, and the plurality of recesses 221 are disposed on the inactive surface 22b, and the semiconductor element 22 is received on the carrier board 21 by the inactive surface 22b thereof. And an adhesive layer 23 is formed on the second surface 21b of the carrier board 21 and the inactive surface 22b' of the semiconductor component 22, and is filled in the recess 221 of the semiconductor component 22 and the opening 210 of the carrier board 21. In the gap with the semiconductor element 22, the germanium semiconductor element 22 is fixed in the opening 21 of the carrier board 21. Therefore, the structure and method for embedding the carrier plate by the semiconductor device of the present invention form a plurality of recesses before the inactive surface of the semiconductor device, and then filling the recess of the semiconductor device, and the opening and the semiconductor device of the carrier device An adhesive layer in the gap to fix the semiconductor component in the carrier. Since the inactive surface of the semiconductor element has a recess, the bonding area between the semiconductor element and the adhesive layer can be increased, the bonding between the semiconductor element and the adhesive layer can be improved, and the bonding between the semiconductor element and the carrier board can be improved. In the subsequent semiconductor process and reliability detection port, such as the circuit build-up layer, the semiconductor component embedded in the carrier plate is not easily separated from the adhesion layer expansion coefficient (CTE), thereby facilitating the delamination of the semiconductor component. Structures to form a development of the constructions. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can devise the spirit of the invention. Modifications and changes are made to the above-described embodiments. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application described later. 19407 11 Ϊ294260 [Simple description of the drawing] Figure 1 is a conventional one. A cross-sectional view of a structure in which a semiconductor element is buried in a carrier board; and FIGS. 2A to 2E are diagrams in which the semiconductor element of the present invention is embedded in a carrier board Cross-sectional view of the manufacturing process of the structure and its manufacturing method. [Main component symbol description] 11, 22 semiconductor elements 11a, 22a active surface 11b, 22b inactive surface 110, 254 electrical connection pads 12, 21 carrier plates 12a, 21a first surface 12b 21b second surface 120, 210 opening 13, 23 adhesive layer 220 electrode 塾 221 recess [5 24 protective layer 25 line build-up structure 251 dielectric layer 252 circuit layer 253 conductive structure 26 solder mask 260 opening 12 19407