WO2020156179A1 - 表面处理铜箔及铜箔基板 - Google Patents

表面处理铜箔及铜箔基板 Download PDF

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Publication number
WO2020156179A1
WO2020156179A1 PCT/CN2020/072282 CN2020072282W WO2020156179A1 WO 2020156179 A1 WO2020156179 A1 WO 2020156179A1 CN 2020072282 W CN2020072282 W CN 2020072282W WO 2020156179 A1 WO2020156179 A1 WO 2020156179A1
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Prior art keywords
copper foil
treated
layer
void volume
treated copper
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PCT/CN2020/072282
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English (en)
French (fr)
Inventor
赖建铭
赖耀生
周瑞昌
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长春石油化学股份有限公司
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Application filed by 长春石油化学股份有限公司 filed Critical 长春石油化学股份有限公司
Priority to JP2021500101A priority Critical patent/JP7082240B2/ja
Priority to CN202080002048.XA priority patent/CN111936670B/zh
Priority to KR1020217000028A priority patent/KR102567838B1/ko
Publication of WO2020156179A1 publication Critical patent/WO2020156179A1/zh

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/04—Wires; Strips; Foils
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/04—Electroplating: Baths therefor from solutions of chromium
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/12—Electroplating: Baths therefor from solutions of nickel or cobalt
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/22—Electroplating: Baths therefor from solutions of zinc
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C25D5/14—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium two or more layers being of nickel or chromium, e.g. duplex or triplex layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/16—Electroplating with layers of varying thickness
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
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    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D9/00—Electrolytic coating other than with metals
    • C25D9/04—Electrolytic coating other than with metals with inorganic materials
    • C25D9/08—Electrolytic coating other than with metals with inorganic materials by cathodic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/04—Processes of manufacture in general
    • H01M4/0438—Processes of manufacture in general by electrochemical processing
    • H01M4/0469—Electroforming a self-supporting electrode; Electroforming of powdered electrode material
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    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/64—Carriers or collectors
    • H01M4/66—Selection of materials
    • H01M4/661—Metal or alloys, e.g. alloy coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/64—Carriers or collectors
    • H01M4/70—Carriers or collectors characterised by shape or form
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/389—Improvement of the adhesion between the insulating substrate and the metal by the use of a coupling agent, e.g. silane
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2255/00—Coating on the layer surface
    • B32B2255/06—Coating on the layer surface on metal layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2255/00—Coating on the layer surface
    • B32B2255/20—Inorganic coating
    • B32B2255/205—Metallic coating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2255/00—Coating on the layer surface
    • B32B2255/28—Multiple coating on one surface
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/202—Conductive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/04—Electroplating: Baths therefor from solutions of chromium
    • C25D3/08—Deposition of black chromium, e.g. hexavalent chromium, CrVI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/05—Accumulators with non-aqueous electrolyte
    • H01M10/052—Li-accumulators
    • H01M10/0525—Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodes; Lithium-ion batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M2004/021—Physical characteristics, e.g. porosity, surface area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M2004/026—Electrodes composed of, or comprising, active material characterised by the polarity
    • H01M2004/027—Negative electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/13—Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
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    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
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    • H05K2203/03—Metal processing
    • H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12431—Foil or filament smaller than 6 mils

Definitions

  • the invention relates to the technical field of copper foil, in particular to a surface-treated copper foil and its copper foil substrate.
  • the copper conductive lines of the copper foil substrate are carried by the insulating carrier, and through the layout design of the conductive lines, the electrical signals can be transmitted to the predetermined area along the predetermined path.
  • the conductive lines of the copper foil substrate must also be further optimized to reduce the signal transmission caused by the skin effect (skin effect) Loss (signal transmission loss).
  • the so-called skin effect means that as the frequency of the electrical signal increases, the current transmission path will be more concentrated on the surface of the wire, especially on the surface of the wire next to the carrier.
  • the current practice is to flatten the surface of the wires in the copper foil substrate immediately adjacent to the carrier as much as possible.
  • reverse treated copper foil RTF
  • the reversal-treated copper foil refers to a kind of copper foil on which the drum side of the copper foil is subjected to a roughening process.
  • the above-mentioned method can effectively reduce the signal transmission loss generated by the copper foil substrate, it still has technical defects to be overcome.
  • the adhesion between the wire and the carrier board is usually lower.
  • the wires in the copper foil substrate are still easily peeled off from the surface of the carrier, resulting in that electrical signals cannot be transmitted to the predetermined area along the predetermined path.
  • the present invention provides an improved surface-treated copper foil and copper foil substrate, which solves the defects in the prior art.
  • a surface-treated copper foil includes a treated surface, wherein the void volume (Vv) of the treated surface is 0.4 to 2.2 ⁇ m 3 / ⁇ m 2 ( ⁇ m 3 / ⁇ m 2 refers to the volume of a surface having a unit area of 1 ⁇ m 2 ), and the kurtosis (Sku) of the treated surface is 1.6 to 4.0.
  • a copper foil substrate includes a carrier board and a surface-treated copper foil disposed on at least one surface of the carrier board, wherein the surface-treated copper foil includes a processing surface facing the carrier board, and the void volume (Vv) of the processing surface is 0.4 to 2.2 ⁇ m 3 / ⁇ m 2 , the kurtosis (Sku) of the treated surface is 1.6 to 4.0.
  • a surface-treated copper foil includes a main body copper foil and a surface treatment layer provided on at least one surface of the main body copper foil.
  • the outer side of the surface treatment layer is the treatment surface of the surface treatment copper foil, and the surface treatment layer includes a roughened layer.
  • the void volume (Vv) of the treated surface is 0.4 to 2.2 ⁇ m 3 / ⁇ m 2
  • the kurtosis (Sku) of the treated surface is 1.6 to 4.0.
  • a surface-treated copper foil includes an electrolytic copper foil and a surface treatment layer provided on the roller surface of the electrolytic copper foil.
  • the outer side of the surface treatment layer is the treatment surface of the surface treatment copper foil, and the surface treatment layer includes a roughened layer.
  • the void volume (Vv) of the treated surface is 0.4 to 2.2 ⁇ m 3 / ⁇ m 2
  • the kurtosis (Sku) of the treated surface is 1.6 to 4.0.
  • the adhesion between the processing surface and the carrier board will be better, and the signal transmission loss can be kept low.
  • the conductive lines formed by the subsequent etching process are not easily peeled off from the surface of the carrier board, thereby improving the yield and durability of the copper foil substrate.
  • FIG. 1 is a schematic cross-sectional view of a surface-treated copper foil according to an embodiment of the invention.
  • Fig. 2 is a graph of the relationship between the surface height and the load factor of the surface-treated copper foil of an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a strip-line according to an embodiment of the invention.
  • 100 surface treated copper foil; 100A: treated surface; 110: main copper foil; 110A: first surface; 110B: second surface; 112: surface treatment layer; 114: roughened layer; 116: passivation layer; 118: Anti-rust layer; 120: coupling layer; 202: void volume; 202A: void volume of trough; 202B: void volume of core part; 300: strip line; 302: wire; 304: resin carrier board; 306-1: ground electrode ; 306-2: ground electrode; h: thickness; t: thickness; w: width
  • FIG. 1 is a schematic cross-sectional view of a surface-treated copper foil according to an embodiment of the invention.
  • the surface-treated copper foil 100 includes at least a main body copper foil 110.
  • the main copper foil 110 may be a rolled copper foil or an electrolytic copper foil, and its thickness is usually greater than or equal to 6 ⁇ m, for example, between 7-250 ⁇ m, or between 9 ⁇ m and 210 ⁇ m.
  • the electrolytic copper foil can be formed by an electrodeposition (or called electrolysis, electrolytic deposition, or electroplating) process.
  • the main copper foil 110 has two oppositely disposed first surface 110A and second surface 110B.
  • the arithmetic average height (Ra) of at least one of the first surface 110A and the second surface 110B is 0.1 ⁇ to 0.4 ⁇ m, but it is not limited to this .
  • the drum side of the electrolytic copper foil may correspond to the first surface 110A of the main copper foil 110, and the deposition surface of the electrolytic copper foil The (deposited side) may correspond to the second side 110B of the main copper foil 110, but is not limited to this.
  • the first surface 110A and the second surface 110B of the main copper foil 110 may be respectively provided with other layers.
  • a surface treatment layer 112 may be provided on the first surface 110A, and/or on the second surface 110A.
  • the surface 110B is provided with another surface treatment layer 112.
  • the first side 110A and the second side 110B of the main copper foil 110 may be further provided with other single-layer or multi-layer structures, or surface treatment layers on the first side 110A and the second side 110B 112 can be replaced by other single-layer or multi-layer structures, or the first side 110A and the second side 110B are not provided with any layers, but it is not limited thereto.
  • the processed surface 100A of the surface-treated copper foil 100 does not correspond to the outer surface of the surface-treated layer 112, but may correspond to the outer surface of other single-layer or multi-layer structures, or may correspond to To the first surface 110A and the second surface 110B of the main body copper foil 110, but it is not limited thereto.
  • the aforementioned surface treatment layer 112 may be a single layer or a stacked layer including a plurality of sub-layers.
  • each sub-layer can be selected from the group consisting of the roughening layer 114, the passivation layer 116, the anti-rust layer 118, and the coupling layer 120.
  • the outer side surface of the surface treatment layer 112 can be regarded as the treatment surface 100A of the surface treatment copper foil 100, and the surface treatment copper foil 100 is subsequently pressed onto the carrier In the manufacturing process of the board, the processing surface 100A will contact the carrier board.
  • the main copper foil 110 is a rolled copper foil, and the surface treatment layer 112 includes at least a roughened layer 114.
  • the main copper foil 110 is an electrolytic copper foil, and the surface treatment layer 112 is disposed on the roller surface of the electrolytic copper foil and includes a roughened layer 114.
  • the main copper foil 110 is an electrolytic copper foil, and the surface treatment layer 112 is disposed on the roller surface of the electrolytic copper foil and includes a roughened layer 114 and a passivation layer 116.
  • the aforementioned roughened layer includes roughened particles (nodule).
  • the roughened particles can be used to improve the surface roughness of the main copper foil, and they can be copper roughened particles or copper alloy roughened particles. Among them, in order to prevent the roughened particles from peeling off from the main copper foil, a covering layer may be further provided on the roughened layer to cover the roughened particles.
  • the passivation layer may have the same or different composition, for example, a metal layer or a metal alloy layer.
  • the aforementioned metal layer may be selected from but not limited to nickel, zinc, chromium, cobalt, molybdenum, iron, tin, and vanadium, for example: nickel layer, nickel-zinc alloy layer, zinc layer, zinc-tin alloy layer or chromium layer.
  • the metal layer and the metal alloy layer may have a single-layer or multi-layer structure, such as a single layer containing zinc and nickel stacked on each other. In the case of a multi-layer structure, the stacking order between the layers can be adjusted according to needs, and is not limited, for example, zinc-containing layer is stacked on nickel-containing layer, or nickel-containing layer is stacked on zinc-containing layer.
  • the anti-rust layer is a coating layer applied to the metal, which can be used to prevent the metal from being corroded and degraded.
  • the anti-rust layer contains metal or organic compounds.
  • the aforementioned metal may be chromium or a chromium alloy, and the chromium alloy may further include one selected from nickel, zinc, cobalt, molybdenum, vanadium, and combinations thereof.
  • the rust-preventing layer includes an organic compound
  • the aforementioned organic compound may be selected from at least one of the group consisting of triazole, thiazole, imidazole and derivatives thereof.
  • the coupling layer can be made of silane, which can be selected from but not limited to 3-aminopropyltriethoxysilane (APTES), N-2-(aminoethyl)-3-amino Propyl trimethoxysilane (N-(2-aminoethyl)-3-aminopropyltrimethoxysilane), glycidyloxypropyl triethoxysilane ((3-glycidyloxypropyl)triethoxysilane), 8-glycidyloxypropyl triethoxysilane (8-glycidyloxyoctyl) trimethoxysilane, 3-methacryloylpropyltriethoxysilane (methacryloylpropyltriethoxysilane), 8-methacryloyloxyoctyltrimethoxysilane (methacryloyloctyltrimethoxysilane), 3- Acryloxypropyl
  • the surface roughness of the treatment surface of the surface treatment copper foil for example: void volume (Vv) , Core void volume (Vvc), trough void volume (Vvv), kurtosis (Sku), and arithmetic mean waviness (Wa), etc., are mainly affected by the coarsening layer.
  • FIG. 2 is a diagram of the relationship between the surface height of the surface-treated copper foil and the material ratio (mr) of an embodiment of the present invention.
  • the calculation of the void volume (Vv) 202 is to integrate the volume of the void enclosed above the curve and below the horizontal cutting line, where the horizontal cutting line is the height corresponding to the curve when the load rate is P1.
  • the void volume (Vv) 202 is a range surrounded by the height level line where the load factor (mr) is P1 (10%) to the upper part of the curve in the interval where the load factor (mr) is 100%.
  • the void volume (Vv) 202 is the sum of the valley void volume (Vvv) 202A and the core void volume (Vvc) 202B.
  • the calculation of the valley void volume (Vvv) 202A is to integrate the volume of the void enclosed above the curve and below another horizontal cutting line, where the position of the other horizontal cutting line is the load rate of the curve (mr) is the height corresponding to P2; and the core void volume (Vvc) 202B is calculated by integrating the curve and the volume of the void enclosed by two horizontal cutting lines, where the position of the two horizontal cutting lines is the curve The corresponding height when the load factor (mr) is P1 and P2 respectively.
  • the void volume (Vv) referred to in the present invention is the value calculated until the load rate (mr) is 10%, and the trough void volume (Vvv) is the load rate (mr) of 80 %, the core void volume (Vvc) is the value calculated when the load factor (mr) is between 10% and 80%.
  • the void volume (Vv) of the treated surface is 0.4 to 2.2 ⁇ m 3 / ⁇ m 2 , preferably 0.4 to 1.9 ⁇ m 3 / ⁇ m 2 .
  • the void volume (Vv) is the sum of the valley void volume (Vvv) and the core void volume (Vvc).
  • the core void volume (Vvc) is preferably 0.3 to 2.1 ⁇ m 3 / ⁇ m 2
  • the valley void volume (Vvv) is preferably 0.01 to 0.10 ⁇ m 3 / ⁇ m 2 .
  • the above-mentioned kurtosis (Sku) refers to an index that measures the sharpness of the height distribution of a surface.
  • the kurtosis (Sku) of the treated surface is 1.6 to 4.0, preferably 2.0 to 4.0.
  • the above-mentioned arithmetic mean waviness (Wa) refers to the periodic fluctuation of the surface caused by an interval larger than the roughness.
  • the arithmetic mean waviness (Wa) of the treatment surface is preferably 0.10 to 0.40 ⁇ m, more preferably 0.10 to 0.30 ⁇ m.
  • the surface-treated copper foil and the contacting carrier board can not only have better peel strength (for example, higher than or equal to 5.01lb/in), but also can reduce the high-frequency electrical signal generated when the high-frequency electrical signal is transmitted in the conductive pattern.
  • Signal transmission loss (the absolute value of signal transmission loss is less than or equal to 0.82dB/in).
  • the processing surface when the void volume (Vv) and kurtosis (Sku) of the processing surface are in the range of 0.4 ⁇ 2.2 ⁇ m 3 / ⁇ m 2 and 2.0 ⁇ 4.0, respectively, for the corresponding copper foil substrate and printing For the circuit board, it can further reduce the signal transmission loss (the absolute value of the signal transmission loss is less than or equal to 0.77dB/in) when high-frequency electrical signals are transmitted in the conductive pattern.
  • the signal transmission loss generated when high-frequency electrical signals are transmitted in the conductive pattern can be further reduced (the absolute value of the signal transmission loss is less than or equal to 0.77 dB/in).
  • the arithmetic mean waviness (Wa) is further less than 0.30 ⁇ m, the absolute value of the signal transmission loss will be further suppressed to be less than 0.75dB/in. Therefore, according to the various embodiments of the present invention, by controlling the surface roughness parameters of the treated surface of the surface treated copper foil, for the corresponding copper foil substrates and printed circuit boards, in addition to improving the surface treatment copper foil and the carrier board
  • the inter-adhesiveness can also reduce the signal transmission loss generated when high-frequency electrical signals are transmitted in the conductive pattern.
  • the aforementioned surface-treated copper foil can be further processed into a copper foil substrate.
  • the copper foil substrate at least includes a carrier board and a surface-treated copper foil.
  • the inner copper foil is arranged on at least one surface of the carrier board and includes a processing surface. Among them, the treated surface of the surface-treated copper foil faces and directly contacts the carrier board.
  • the above-mentioned carrier board can be bakelite, polymer board, or glass fiber board, but it is not limited thereto.
  • the polymer component of the polymer board can be, for example, epoxy resin, phenolic resin, polyester resin, polyimide resin, and acrylic resin.
  • the above-mentioned glass fiber board may be a prepreg formed by immersing glass fiber cloth fabric material in the aforementioned polymer (such as epoxy resin).
  • Step A is implemented to provide the main body copper foil.
  • the main copper foil may be rolled copper foil or electrolytic copper foil.
  • the arithmetic average height (Ra) of the rolled copper foil surface can be in a specific interval, such as 0.1 ⁇ 0.4 ⁇ m, or 0.15 ⁇ 0.25 ⁇ m; while for the main copper foil, electrolytic copper
  • the method of electrodeposition can be used to form this electrolytic copper foil.
  • the metal cathode roller will continue to rotate, and the electrolytic copper foil will be continuously formed on the surface of the metal cathode roller and peeled off from one side of the metal cathode roller.
  • the surface of the electrolytic copper foil facing the metal cathode roller can be referred to as the roller surface
  • the surface of the electrolytic copper foil away from the metal cathode roller can be referred to as the deposition surface.
  • the surface of the metal cathode roller will be slightly oxidized, resulting in an uneven surface, thereby reducing the flatness of the roller surface of the electrolytic copper foil. Therefore, a polishing buff can be further arranged adjacent to the metal cathode roller, so that there is a contact surface between the metal cathode roller and the polishing roller. By rotating the metal cathode roller and the polishing roller in opposite directions, the oxide layer on the surface of the metal cathode roller can be removed by the polishing roller, thereby maintaining the surface flatness of the metal cathode roller.
  • the manufacturing parameter range is illustrated as follows:
  • Chloride ion (from hydrochloric acid, RCI Labscan Ltd.): 20mg/L
  • This step B is to perform a surface cleaning process on the main copper foil to ensure that the surface of the main copper foil does not have contaminants (such as oil stains and oxides).
  • the manufacturing parameter ranges are illustrated as follows:
  • a roughened layer is formed on the surface of the main copper foil.
  • Electrolytic deposition can be used to form a roughened layer on a certain surface of the main copper foil, such as a roller surface.
  • the roughened layer may include roughened particles, or nodule, and a coating layer covering the roughened particles.
  • appropriate salts such as sodium tungstate or ferrous sulfate, can be selectively added to the electrolyte to control the distribution of roughened particles. Examples of manufacturing parameter ranges are as follows:
  • Phthal sulfonimide sacharin, Sigma-Aldrich Company: 5 ⁇ 20mg/L(ppm)
  • This step D is to form a covering layer on the roughened layer, and the manufacturing parameter range is illustrated as follows:
  • a passivation layer is formed on at least one surface of the copper foil.
  • the passivation layer can be formed by an electrolytic deposition process.
  • a two-layer stack structure composed of nickel and zinc is exemplified.
  • the range of manufacturing parameters is exemplified as follows:
  • step F an anti-rust layer is formed on the above-mentioned copper foil, and the manufacturing parameter range is illustrated as follows:
  • This step G is to form a coupling layer on the side of the copper foil where the roughened layer is provided.
  • the copper foil is washed with water, but the surface of the copper foil is not dried.
  • the aqueous solution containing the silane coupling agent is sprayed onto the rust preventive layer on the side of the copper foil with the roughened layer, so that the silane coupling agent is adsorbed on the surface of the passivation layer. Examples of manufacturing parameter ranges are as follows:
  • Silane coupling agent (3-aminopropyltriethoxysilane)
  • This step H is to press and bond the surface-treated copper foil formed through the above steps to the carrier board to form a copper foil substrate.
  • a copper foil substrate can be formed by hot pressing the surface-treated copper foil 100 shown in FIG. 1 to a carrier.
  • Example 1 is a surface-treated copper foil, and its manufacturing procedure corresponds to step A to step G in the above-mentioned manufacturing method.
  • the manufacturing parameters that differ between Example 1 and the above-mentioned manufacturing method are described in Table 1.
  • the main copper foil is an electrolytic copper foil, and the roughened layer is provided on the roller surface of the electrolytic copper foil.
  • Examples 2-19 are substantially the same as those of Example 1, and their different manufacturing parameters are described in Table 1.
  • the main copper foils in Examples 2-1 and 13-18 are electrolytic copper foils, and the roughened layer is provided on the roller surface of the electrolytic copper foil.
  • a surface roughness measuring instrument SE 600 Series, Kosaka Laboratory Ltd.
  • Wa arithmetic mean waviness
  • the test results are described in Table 2.
  • the kurtosis (Sku) of the treated surface of the surface-treated copper foil is measured by the surface texture analysis of the laser microscope (LEXT OLS5000-SAF, Olympus).
  • the specific measurement conditions are as follows:
  • Objective lens magnification 100 times objective lens (MPLAPON-100x LEXT, Olympus)
  • the surface texture analysis of the laser microscope (LEXT OLS5000-SAF, Olympus) is used to measure the core void volume (Vvc), trough void volume (Vvv), And void volume (Vv).
  • the core void volume (Vvc) is obtained by setting the P1 value and P2 value of the load rate (mr) to 10% and 80%, respectively, and the trough void volume (Vvv) is the load rate (mr) P2 value It is obtained by setting it to 80%, and the void volume (Vv) is the sum of the aforementioned core void volume (Vvc) and trough void volume (Vvv).
  • the test results are described in Table 2.
  • the specific measurement conditions are as follows:
  • Objective lens magnification 100 times objective lens (MPLAPON-100x LEXT, Olympus)
  • the surface-treated copper foil of any of the above embodiments is made into a stripline, and the corresponding signal transmission loss is measured.
  • the structure of the strip line can be exemplified as shown in FIG. 3.
  • the strip line 300 is made of 152.4 ⁇ m resin (from SyTech Corporation’s S7439G).
  • the surface treatment copper foil of any of the above embodiments is first laminated, and then the surface treatment copper foil is made into a wire 302, and then two other resins are used (S7439G, taken from SyTech Corporation's S7439G) covers the surfaces on both sides respectively, so that the wires 302 are arranged in the resin carrier board (S7439G, SyTech Corporation.) 304.
  • the strip line 300 may further include two ground electrodes 306-1 and a ground electrode 306-2, which are respectively disposed on opposite sides of the resin carrier 304.
  • the ground electrode 306-1 and the ground electrode 306-2 may be electrically connected to each other through conductive vias, so that the ground electrode 306-1 and the ground electrode 306-2 have the same potential.
  • the specifications of the components in the strip line 300 are as follows: the length of the wire 302 is 100mm, the width w is 120 ⁇ m, and the thickness t is 35 ⁇ m; the resin carrier 304 has a Dk of 3.74 and a Df of 0.006 (according to IPC-TM650No.2.5.5.5 , Measured with a 10GHz signal); the characteristic impedance is 50 ⁇ .
  • a signal analyzer PNA N5230C network analyzer, Agilent
  • Agilent a signal analyzer
  • the output value of the other end of 302 is used to determine the signal transmission loss generated by the strip line 300.
  • the specific measurement conditions are as follows: the frequency of the electrical signal is 200MHz to 15GHz, the number of sweeps is 6401 points, and the calibration method is TRL.
  • the degree of signal transmission loss of the corresponding strip line is judged, and the detection results are recorded in Table 2.
  • the smaller the absolute value of the signal transmission loss the less the signal loss during transmission. Specifically, when the absolute value of the signal transmission loss is greater than 0.82dB/in, it means that the signal transmission performance is poor; when the absolute value of the signal transmission loss is less than or equal to 0.82dB/in, it means that the signal transmission performance is good; and when the signal transmission When the absolute value of the loss is less than 0.75dB/in, it represents the best signal transmission performance.
  • the surface-treated copper foil and the contacting carrier board can not only have better peel strength (for example, higher than or equal to 5.01lb/in), but also can reduce the generation of high-frequency electrical signals when transmitting in the conductive pattern.
  • Signal transmission loss the absolute value of signal transmission loss is less than or equal to 0.82dB/in).
  • the signal transmission loss (the absolute value of the signal transmission loss is less than or equal to 0.77 dB/in) generated when high-frequency electrical signals are transmitted in the conductive pattern can be further reduced.
  • the above-mentioned surface roughness parameters of the treated surface of the surface-treated copper foil within a specific range, for the corresponding copper foil substrates and printed circuit boards, in addition to improving the surface-treated copper foil Adhesion to the carrier (peel strength greater than 5lb/in), and can also reduce the signal transmission loss generated when high-frequency electrical signals are transmitted in the conductive pattern (the absolute value of the signal transmission loss is less than 0.75dB/in) .

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Abstract

一种表面处理铜箔，包括处理面，其中处理面的空隙体积(Vv)为0.4至2.2μm 3/μm 2，且处理面的峰度(Sku)为1.6至4.0。

Description

表面处理铜箔及铜箔基板 技术领域
本发明涉及一种铜箔的技术领域，特别是关于一种表面处理铜箔及其铜箔基板。
背景技术
随着电子产品逐渐朝向轻薄以及传递高频信号的趋势发展，对于铜箔和铜箔基板的需求也日益提升。一般而言，铜箔基板的铜导电线路会被绝缘载板承载，且通过导电线路的布局设计，其可将电信号沿着预定的路径传递至预定区域。此外，对于用于传递高频电信号(例如高于10GHz)的铜箔基板而言，其铜箔基板的导电线路也必须进一步优化，以降低因集肤效应(skin effect)而产生的信号传递损失(signal transmission loss)。所谓的集肤效应，是指随着电信号的频率增加，电流的传递路径会更集中于导线的表面，尤其是更集中于紧邻于载板的导线表面。为了降低集肤效应而产生的信号传递损失，现有作法是尽可能将铜箔基板中紧邻于载板的导线表面予以平坦化。此外，为了同时维持导线表面和载板之间的附着性，也可采用反转处理铜箔(reverse treated foil,RTF)以制作导线。其中，反转处理铜箔指铜箔的辊筒面(drum side)会被施行粗化处理制程的一种铜箔。
然而，即便上述作法确实可有效降低铜箔基板所产生的信号传递损失，其仍存有待克服的技术缺陷。举例而言，由于面向载板的导线表面会较平坦，因此导线和载板之间的附着性通常会较低。在这样的情况下，即便采用了反转处理铜箔以制作导线，铜箔基板中的导线仍很容易从载板的表面剥离，导致电信号无法沿着预定路径传递至预定区域。
因此，仍有必要提供一种表面处理铜箔及铜箔基板，以解决现有技术中所存在的缺陷。
发明内容
有鉴于此，本发明提供有一种改良的表面处理铜箔及铜箔基板，解决了现有技术中所存在的缺陷。
根据本发明的一实施例，提供一种表面处理铜箔，表面处理铜箔包括处理面，其中处理面的空隙体积(void volume，Vv)为0.4至2.2μm 3/μm 2(μm 3/μm 2是指单位 面积为1μm 2的表面所具有的体积)，且处理面的峰度(Sku)为1.6至4.0。
根据本发明的另一实施例，提供一种铜箔基板。铜箔基板包括载板以及设置于载板的至少一表面的表面处理铜箔，其中表面处理铜箔包括面向载板的处理面，且处理面的空隙体积(Vv)为0.4至2.2μm 3/μm 2，处理面的峰度(Sku)为1.6至4.0。
可选择地，根据本发明的又一实施例，提供一种表面处理铜箔。表面处理铜箔包括主体铜箔，以及设置于主体铜箔至少一表面的表面处理层。其中，表面处理层的外侧为表面处理铜箔的处理面，且表面处理层包括粗化层。处理面的空隙体积(Vv)为0.4至2.2μm 3/μm 2，处理面的峰度(Sku)为1.6至4.0。
可选择地，根据本发明的又一实施例，提供一种表面处理铜箔，表面处理铜箔包括电解铜箔以及设置于电解铜箔的辊筒面的表面处理层。其中，表面处理层的外侧为表面处理铜箔的处理面，且表面处理层包括粗化层。处理面的空隙体积(Vv)为0.4至2.2μm 3/μm 2，处理面的峰度(Sku)为1.6至4.0。
根据上述实施例，通过将表面处理铜箔的处理面的空隙体积(Vv)控制为0.4至2.2μm 3/μm 2，且处理面的峰度(Sku)控制为1.6至4.0，当后续将表面处理铜箔压合至载板时，处理面和载板之间的附着性会更佳，且也能保持较低的信号传递损失程度。通过提升表面处理铜箔处理面和载板之间的附着性，后续经由蚀刻程序而形成的导电线路便不易从载板的表面剥离，进而提升了铜箔基板的良率及耐用性。
附图说明
图1是根据本发明一实施例所绘示的表面处理铜箔的剖面示意图。
图2是本发明一实施例的表面处理铜箔的表面高度和负载率之间的关系图。
图3是根据本发明一实施例所绘示的带状线(strip-line)的示意图。
附图标记说明如下：
100：表面处理铜箔；100A：处理面；110：主体铜箔；110A：第一面；110B：第二面；112：表面处理层；114：粗化层；116：钝化层；118：防锈层；120：耦合层；202：空隙体积；202A：波谷部空隙体积；202B：核心部空隙体积；300：带状线；302：导线；304：树脂载板；306‐1：接地电极；306‐2：接地电极；h：厚度；t：厚度；w：宽度
具体实施方式
在下文中，加以陈述的表面处理铜箔、铜箔基板及印刷电路板的具体实施方式，使本技术领域中具有通常技术者可据以实现本发明。这些具体实施方式可参考相对应的图式，使这些图式构成实施方式的一部分。虽然本发明的实施例公开如下，然而其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范畴内，当可作些许的改动与修饰。其中，各实施例以及实验例所使用的方法，如无特别说明，则为常规方法。
针对本发明中所提及的空间相关的叙述词汇，“在…上”及“在…上方”等用语在本发明中的含义应该以最宽泛方式来解释，使得“在…上”及“在…上方”等用语不仅指直接处于某物上，而且还可以包括在有中间特征或中间层位于二者之间的情况下而处于某物上，并且“在…上”或“在…上方”不仅指处于某物之上或上方，而且还可以包括在二者之间没有中间特征或中间层的情况下而处于在某物之上或上方(即直接处于某物上)的态样。
此外，在下文中除非有相反的指示，本发明及权利要求的范围所阐述的数值参数是约略数，其可视需要而变化，或至少应根据所公开的有意义的位数数字并且使用通常的进位方式，以解读各个数值参数。本发明中，范围可表示为从一端点至另一端点，或是在两个端点之间。除非特别声明，否则本发明中的所有范围都包含端点。
须知悉的是，在不脱离本发明的精神下，下文所描述的不同实施方式中的技术特征彼此之间可以被置换、重组、混合，以构成其他的实施例。
图1是根据本发明一实施例所绘示的表面处理铜箔的剖面示意图。如图1所示，表面处理铜箔100至少包括主体铜箔110。主体铜箔110可以是压延铜箔或是电解铜箔，其厚度通常大于或等于6μm，例如介于7-250μm之间，或介于9μm～210μm之间。对于主体铜箔110为电解铜箔的情形，此电解铜箔可通过电沉积(或称电解、电解沉积、电镀)制程而被形成。主体铜箔110具有两相对设置的第一面110A和第二面110B。根据本发明的一实施例，当主体铜箔110为压延铜箔时，第一面110A和第二面110B至少一者的算术平均高度(Ra)为0.1μ～0.4μm，但不限定于此。根据本发明的一实施例，当主体铜箔110为电解铜箔时，电解铜箔的辊筒面(drum side)可以对应至主体铜箔110的第一面110A，而电解铜箔的沉积 面(deposited side)可以对应至主体铜箔110的第二面110B，但不限定于此。
根据本发明的一实施例，主体铜箔110的第一面110A和第二面110B上可分别设置有其他的层，例如可在第一面110A设置表面处理层112，及/或在第二面110B设置另一表面处理层112。根据本发明的其他实施例，主体铜箔110的第一面110A和第二面110B可以进一步设置有其他的单层或多层结构、或是第一面110A和第二面110B的表面处理层112可以被其他的单层或多层结构取代、或是第一面110A和第二面110B未设置有任何层，但不限定于此。因此，在这些实施例中，表面处理铜箔100的处理面100A便不会对应至表面处理层112的外侧面，而可能会对应至其他单层或多层结构的外侧面，或可能会对应至主体铜箔110的第一面110A和第二面110B，但不限定于此。
前述表面处理层112可以是单层，或是包括多个子层的堆叠层。对于表面处理层112是堆叠层的情形，各子层可选自由粗化层114、钝化层116、防锈层118以及耦合层120所构成的群组。对于设置有表面处理层112的表面处理铜箔100而言，表面处理层112的外侧面可以被视为是表面处理铜箔100的处理面100A，经由后续将表面处理铜箔100压合至载板的制程，此处理面100A会接触载板。值得一提的是，当表面处理层112有多个时，表面处理层112彼此之间的子层结构可以相同或不同。根据本发明的一实施例，主体铜箔110为压延铜箔，且表面处理层112至少包含粗化层114。根据本发明的一实施例，主体铜箔110为电解铜箔，表面处理层112设置于电解铜箔的辊筒面，且包含粗化层114。根据本发明的一实施例，主体铜箔110为电解铜箔，表面处理层112设置于电解铜箔的辊筒面，且包含粗化层114及钝化层116。
前述粗化层包括粗化粒子(nodule)。粗化粒子可用于增进主体铜箔的表面粗糙度，其可为铜粗化粒子或铜合金粗化粒子。其中，为了防止粗化粒子从主体铜箔剥离，可进一步在粗化层上设置覆盖层，以覆盖住粗化粒子。
钝化层可以是相同或不同组成，例如是金属层或金属合金层。其中，前述金属层可以选自但不限于镍、锌、铬、钴、钼、铁、锡，及钒，例如是：镍层、镍锌合金层、锌层、锌锡合金层或铬层。此外，金属层及金属合金层可以是单层或多层结构，例如彼此堆叠的含锌及含镍的单层。当为多层结构时，各层间的堆叠顺序可以依据需要而调整，并无一定限制，例如含锌层叠于含镍层上，或含镍层 叠于含锌层上。
防锈层是施加至金属的被覆层，其可用于避免金属受到腐蚀等而劣化。防锈层包含金属或有机化合物。当防锈层包含金属时，前述金属可以是铬或铬合金，而铬合金可进一步包含选自镍、锌、钴、钼、钒及其组合中的一者。当防锈层包含有机化合物时，前述有机化合物可以选自由三唑、噻唑、咪唑及其衍生物所组成的群组中的至少一者。
耦合层可以是由硅烷制成，其可选自但不限于3-胺基丙基三乙氧基硅烷(3-aminopropyltriethoxysilane,APTES)、N-2-(胺基乙基)-3-胺基丙基三甲氧基硅烷(N-(2-aminoethyl)-3-aminopropyltrimethoxysilane)、缩水甘油氧基丙基三乙氧基硅烷((3-glycidyloxypropyl)triethoxysilane)、8-缩水甘油氧基辛基三甲氧基硅烷((8-glycidyloxyoctyl)trimethoxysilane)、3-甲基丙烯酰氧基丙基三乙氧基硅烷(methacryloylpropyltriethoxysilane)、8-甲基丙烯酰氧基辛基三甲氧基硅烷(methacryloyloctyltrimethoxysilane)、3-丙烯酰氧基丙基三甲氧基硅烷(methacryloylpropyltrimethoxysilane)、3-巯基丙基三甲氧基硅烷((3-mercaptopropyl)trimethoxysilane)、3-缩水甘油丙基三甲氧基硅烷((3-glycidyloxypropyl)trimethoxysilane)，其用于增进表面处理铜箔与其他材料(例如载板)之间的附着性。
根据本发明的实施例，由于表面处理层中的钝化层和耦合层的总和厚度远小于粗化层的厚度，因此表面处理铜箔的处理面的表面粗糙度，例如：空隙体积(Vv)、核心部空隙体积(Vvc)、波谷部空隙体积(Vvv)、峰度(Sku)、及算术平均波度(Wa)等，主要受粗化层的影响。
上述空隙体积(Vv)、核心部空隙体积(Vvc)、及波谷部空隙体积(Vvv)是根据ISO 25178-2(2012)的定义，其等的量测可例示如图2所示。图2是本发明一实施例的表面处理铜箔的表面高度和负载率(material ratio,mr)之间的关系图。其中，空隙体积(Vv)202的计算是将曲线上方及水平切割线下方所围住的空隙的体积予以积分，其中水平切割线是该曲线在负载率为P1时所对应的高度。也即，空隙体积(Vv)202为负载率(mr)为P1(10％)的高度水平线下方，至负载率(mr)为100％的区间内的曲线上方所围绕的范围。此外，空隙体积(Vv)202是由波谷部空隙体积(Vvv)202A和核心部空隙体积(Vvc)202B加总而得。进一步而言，波谷部空隙体 积(Vvv)202A的计算是将曲线上方及另一水平切割线下方所围住的空隙的体积予以积分，其中该另一水平切割线的位置是该曲线在负载率(mr)为P2时所对应的高度；而核心部空隙体积(Vvc)202B的计算是将曲线及两水平切割线所围住的空隙的体积予以积分，其中两水平切割线的位置是该曲线分别在负载率(mr)为P1和P2时所对应的高度。需注意的是，如未特别声明，本发明所指的空隙体积(Vv)是到负载率(mr)为10％所计算的值，波谷部空隙体积(Vvv)是负载率(mr)为80％所计算的值，核心部空隙体积(Vvc)是负载率(mr)为10％至80％之间所计算的值。
在本发明中，处理面的空隙体积(Vv)为0.4～2.2μm 3/μm 2，较佳为0.4～1.9μm 3/μm 2。此外，空隙体积(Vv)是由波谷部空隙体积(Vvv)和核心部空隙体积(Vvc)加总而得，在本发明中，核心部空隙体积(Vvc)较佳为0.3～2.1μm 3/μm 2，且波谷部空隙体积(Vvv)较佳为0.01～0.10μm 3/μm 2。
上述峰度(Sku)是指衡量一表面的高度分布的尖锐度(sharpness)的指标。当Sku的数值越低，代表此表面的高度分布越趋平整状；反之，当Sku的数值越高，则代表此表面的峰或谷的尖锐度较高，也即陡峭的峰或谷较多。在本发明中，处理面的峰度(Sku)为1.6～4.0，较佳为2.0～4.0。
上述算术平均波度(Wa)是指由比粗糙度大的间隔所引起的表面的周期性起伏。其中，处理面的算术平均波度(Wa)较佳为0.10～0.40μm、更佳为0.10～0.30μm。
根据本发明的实施例，当处理面的空隙体积(Vv)及峰度(Sku)分别位于0.4～2.2μm 3/μm 2和1.6～4.0的范围时，对于相应的铜箔基板和印刷电路板而言，表面处理铜箔和相接触的载板除了可以具有较佳的剥离强度(例如高于或等于5.01lb/in)，也可以同时降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于或等于0.82dB/in)。
根据本发明的另一实施例，当处理面的空隙体积(Vv)及峰度(Sku)分别位于0.4～2.2μm 3/μm 2和2.0～4.0的范围时，对于相应的铜箔基板和印刷电路板而言，可以进一步降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于或等于0.77dB/in)。
根据本发明的又一实施例，当处理面的空隙体积(Vv)及峰度(Sku)分别位于0.4～2.2μm 3/μm 2和1.6～4.0的范围时，且算术平均波度(Wa)小于或等于0.40μm 时，对于相应的铜箔基板和印刷电路板而言，可以进一步降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于或等于0.77dB/in)。且当算术平均波度(Wa)再进一步小于0.30μm时，信号传递损失的绝对值会再进一步抑制为低于0.75dB/in。因此，根据本发明的各实施例，通过控制表面处理铜箔的处理面的表面粗糙度参数，则对于相应的铜箔基板和印刷电路板而言，除了可以提升表面处理铜箔和载板之间的附着性，也可以同时降低高频电信号在导电图案中传递时所产生的信号传递损失。
前述表面处理铜箔可再进一步加工制成铜箔基板。铜箔基板至少包括载板和表面处理铜箔。该表面处里铜箔设置于该载板的至少一表面，且包括一处理面。其中，表面处理铜箔的处理面面向且直接接触载板。
其中，上述载板可采用电木板、高分子板、或玻璃纤维板，但并不限于此。所述高分子板的高分子成分可例如：环氧树脂(epoxy resin)、酚醛树脂(phenolic resins)、聚酯树脂(polyester resins)、聚酰亚胺树脂(polyimide resins)、压克力(acrylics)、甲醛树脂(formaldehyde resins)、双马来酰亚胺三嗪树脂(bismaleimidetriazine resins，又称BT树脂)、氰酸酯树脂(cyanate ester resin)、含氟聚合物(fluoropolymers)、聚醚砜(poly ether sulfone)、纤维素热塑性塑料(cellulosic thermoplastics)、聚碳酸酯(polycarbonate)、聚烯烃(polyolefins)、聚丙烯(polypropylene)、聚硫化物(polysulfide)、聚氨酯(polyurethane)、聚酰亚胺树脂(polyimide)、液晶高分子(Liquid Crystal Polymer,LCP)、聚氧二甲苯(polyphenylene oxide,PPO)。上述玻璃纤维板可以是玻璃纤维布织物料浸泡于前述高分子(如：环氧树脂)后所形成的预浸渍材料(prepreg)。
在下文中，进一步针对表面处理铜箔以及铜箔基板的制作方法予以例示性地描述。制作方法中的各步骤分述如下：
(1)步骤A
实施步骤A，以提供主体铜箔。其中，主体铜箔可以是压延铜箔或是电解铜箔。对于主体铜箔是压延铜箔的情况，此压延铜箔表面的算术平均高度(Ra)可介于特定区间，例如0.1μ～0.4μm，或0.15～0.25μm；而对于主体铜箔是电解铜箔的情况，可以利用电解沉积(electrodeposition)的方式，以形成此电解铜箔。在电解沉积过程中，金属阴极辊筒会持续转动，且电解铜箔会被连续形成于金属阴极 辊筒的表面，并自金属阴极辊筒的某一侧被剥离。其中，电解铜箔面向金属阴极辊筒的表面可称作是辊筒面，而电解铜箔远离金属阴极辊筒的表面可称作是沉积面。此外，在电解沉积的过程中，由于金属阴极辊筒的表面会被些许氧化，而产生不平坦的表面，进而降低了电解铜箔的辊筒面的平坦度。因此，可以进一步在金属阴极辊筒的相邻处设置抛光辊筒(polish buff)，使金属阴极辊筒和抛光辊筒之间具有接触面。通过让金属阴极辊筒和抛光辊筒以相反的方向转动，便可以使得金属阴极辊筒表面的氧化层被抛光辊筒去除，进而维持了金属阴极辊筒的表面平坦度。
对于压延铜箔而言，其特征例示如下：
〈1.1压延铜箔〉
算术平均高度(Ra)：0.1μ～0.4μm
对于电解铜箔而言，其制造参数范围例示如下：
〈1.2硫酸铜电解液的组成及电解条件〉
硫酸铜(CuSO 4·5H 2O)：320g/L
硫酸：100g/L
氯离子(从盐酸而来，RCI Labscan Ltd.)：20mg/L
明胶(SV,Nippi,Inc.)：0.35mg/L
液温：50℃
电流密度：70A/dm 2
〈1.3金属阴极辊筒〉
材质：钛
转速：3m/min
〈1.4抛光辊筒〉
型号(Nippon Tokushu Kento Co.,Ltd)：#500、#1000、#1500、#2000
转速：250～550rpm
(2)步骤B
本步骤B是对上述主体铜箔施行表面清洁的制程，以确保主体铜箔的表面不具有污染物(例如油污、氧化物)，其制造参数范围例示如下：
〈2.1清洗液的组成及清洁条件〉
硫酸铜：130g/L
硫酸：50g/L
液温：27℃
浸渍时间：30秒
(3)步骤C
本步骤C是在上述主体铜箔的表面形成粗化层。可通过电解沉积，以将粗化层形成于主体铜箔的某一面，例如辊筒面。其中，粗化层可以包括粗化粒子，或称为瘤状结构(nodule)，和覆盖住粗化粒子的覆盖层。其中，在形成粗化粒子时，可以选择性地在电解液中添加适当的盐类，例如钨酸钠或硫酸亚铁，以控制粗化粒子的分布情形。制造参数范围例示如下：
〈3.1制作粗化粒子的参数〉
硫酸铜(CuSO 4·5H 2O)：70g/L
硫酸：100g/L
钨酸钠(Na 2WO 4)：50～450mg/L(ppm)
硫酸亚铁(FeSO 4)：1000～3000mg/L(ppm)
邻苯甲酰磺酰亚胺(糖精,Sigma-Aldrich Company):5～20mg/L(ppm)
液温：25℃
电流密度：10A/dm 2
时间：10秒
(4)步骤D
本步骤D是在上述粗化层上形成覆盖层，其制造参数范围例示如下：
〈4.1制作覆盖层的参数〉
硫酸铜(CuSO 4·5H 2O)：320g/L
硫酸：100g/L
液温：40℃
电流密度：15A/dm 2
时间：10秒
(5)步骤E
本步骤E是在上述铜箔的至少一表面形成钝化层。可以通过电解沉积制程以 形成钝化层，对于钝化层是例示由镍、锌所构成的两层堆叠结构，其制造参数范围例示如下：
〈5.1含镍层的电解液组成及电解条件〉
硫酸镍(NiSO 4)：188g/L
硼酸(H 3BO 3)：32g/L
次磷酸(H 3PO 2)：4g/L
液温：20℃
溶液pH：3.5
电流密度：0.7A/dm 2
时间：3秒
〈5.2含锌层的电解液组成及电解条件〉
硫酸锌(ZnSO 4)：11g/L
偏钒酸铵(NH 4VO 3)：0.25g/L
液温：15℃
溶液pH：13
电流密度：0.5A/dm 2
时间：2秒
(6)步骤F
本步骤F是在上述铜箔上形成防锈层，其制造参数范围例示如下：
〈6.1含铬层的电解液组成及电解条件〉
铬酸：5g/L
液温：35℃
溶液pH：12.5
电流密度：10A/dm 2
时间：5秒
(7)步骤G
本步骤G是在上述铜箔设置粗化层的一侧上形成耦合层。举例而言，完成上述电解制程后，用水洗涤铜箔，但不干燥铜箔表面。之后将含有硅烷耦合剂的水溶液喷涂至铜箔设有粗化层侧的防锈层上，使得硅烷耦合剂吸附于钝化层的表 面。制造参数范围例示如下：
〈7.1硅烷耦合剂的参数〉
硅烷耦合剂：(3-胺基丙基)三乙氧基硅烷(3-aminopropyltriethoxysilane)
水溶液的硅烷耦合剂浓度：0.25wt.％
喷涂时间：10秒
(8)步骤H
本步骤H是将经由上述步骤而形成的表面处理铜箔压合至载板，以形成铜箔基板。根据本发明的一实施例，可通过将图1所示的表面处理铜箔100热压至载板，而形成铜箔基板。
为了使本领域的通常知识者得据以实现本发明，下文将进一步详细描述本发明的各具体实施例，以具体说明本发明的表面处理铜箔及铜箔基板。需注意的是，以下实施例仅为例示性，不应以其限制性地解释本发明。也即，在不超出本发明范畴的情况下，可适当地改变各实施例中所采用的材料、材料的用量及比率以及处理流程等。
实施例1
实施例1为表面处理铜箔，其制造程序对应于上述制作方法中的步骤A至步骤G。实施例1与上述制作方法之间相异的制造参数，记载于表1中。其中，主体铜箔为电解铜箔，且粗化层设置在电解铜箔的辊筒面上。
实施例2-19
实施例2-19的制造程序大致相同于实施例1的制造程序，其彼此之间不同的制造参数记载于表1中。其中，实施例2-1、13-18中的主体铜箔为电解铜箔，且粗化层设置在电解铜箔的辊筒面上。
实施例12及实施例19在制作方法所采用的主体铜箔为压延铜箔(Ra＝0.2μm)，而非电解铜箔。
表1
Figure PCTCN2020072282-appb-000001
Figure PCTCN2020072282-appb-000002
以下进一步描述上述各实施例1-19的各项检测结果，例如：〈算术平均波度(Wa)〉、〈峰度(Sku)〉、〈核心部空隙体积(Vvc)〉、〈波谷部空隙体积(Vvv)〉、〈空隙体积(Vv)〉、〈剥离强度〉、及〈信号传递损失〉。
〈算术平均波度(Wa)〉
根据标准JIS B0601-2013 4.2.1，以表面粗糙度测量仪(SE 600Series,Kosaka Laboratory Ltd.)检测各实施例的表面处理铜箔的处理面的算术平均波度(Wa)。具体量测条件如下：测针尖端的直径为2μm、测针尖端的锥角为90°、测量长度为7.5mm、轮廓曲线过滤器的截止值为λc＝0.8mm、λf＝2.5mm。检测结果记载于表2中。
〈峰度(Sku)〉
根据标准ISO 25178-2：2012，以激光显微镜(LEXT OLS5000-SAF,Olympus)的表面纹理分析，测量表面处理铜箔的处理面的峰度(Sku)。具体测量条件如下：
光源波长：405nm
物镜倍率：100倍物镜(MPLAPON-100x LEXT,Olympus)
光学变焦：1.0倍
观察面积：129μm×129μm
分辨率：1024像素×1024像素
条件：启用激光显微镜的自动倾斜消除功能(Auto tilt removal)
滤镜：无滤镜(unfiltered)
空气温度：24±3℃
相对湿度：63±3％
〈核心部空隙体积(Vvc)〉、〈波谷部空隙体积(Vvv)〉、〈空隙体积(Vv)〉
根据标准ISO 25178-2：2012，以激光显微镜(LEXT OLS5000-SAF,Olympus)的表面纹理分析，测量表面处理铜箔的处理面的核心部空隙体积(Vvc)、波谷部空隙体积(Vvv)、及空隙体积(Vv)。其中，核心部空隙体积(Vvc)是由设定负载率(mr)的P1值及P2值分别为10％及80％而予以获得，波谷部空隙体积(Vvv)是负载率(mr)P2值设定为80％而予以获得，空隙体积(Vv)为前述核心部空隙体积(Vvc)及波谷部空隙体积(Vvv)之和。检测结果记载于表2中。具体测量条件如下：
光源波长：405nm
物镜倍率：100倍物镜(MPLAPON-100x LEXT,Olympus)
光学变焦：1.0倍
观察面积：129μm×129μm
分辨率：1024像素×1024像素
条件：启用激光显微镜的自动倾斜消除功能(Auto tilt removal)
滤镜：无滤镜(unfiltered)
空气温度：24±3℃
相对湿度：63±3％
〈剥离强度〉
将6片厚度各自为0.076mm的市售树脂片(S7439G,SyTech Corporation.)堆叠 在一起，以形成树脂片堆叠层，并将上述任一实施例的表面处理铜箔设置于树脂片堆叠层上。接着，将表面处理铜箔压合至树脂片堆叠层，以形成积层板。压合条件如下：温度200℃、压力400psi、及压合时间120分钟。
之后，根据标准JIS C 6471，使用万能试验机，以将表面处理铜箔以90°的角度从积层板剥离。检测结果记载于表2中。
〈信号传递损失〉
将上述任一实施例的表面处理铜箔制作成带状线(stripline)，并测量其相应的信号传递损失。其中，带状线的结构可例示如图3所示。带状线300是在152.4μm的树脂(取自SyTech Corporation之S7439G)上先贴合上述任一实施例的表面处理铜箔，而后将表面处理铜箔制作成导线302，再使用另外两片树脂(S7439G，取自SyTech Corporation之S7439G)分别覆盖两侧表面，使导线302被设置于树脂载板(S7439G,SyTech Corporation.)304之中。带状线300还可包括两接地电极306-1和接地电极306-2，分别设置于树脂载板304的相对两侧。接地电极306-1和接地电极306-2彼此之间可以通过导电通孔而彼此电连接，而使得接地电极306-1和接地电极306-2具有等电位。
带状线300中各部件的规格如下：导线302的长度为100mm、宽度w为120μm、厚度t为35μm；树脂载板304的Dk为3.74、Df为0.006(依据IPC-TM 650No.2.5.5.5，以10GHz信号测量)；特征阻抗为50Ω。
根据标准Cisco S3方法，利用信号分析仪(PNA N5230C network analyzer,Agilent)在接地电极306-1、306-2均为接地电位的情况下，将电信号由导线302的某一端输入，并测量导线302的另一端的输出值，以判别带状线300所产生的信号传递损失。具体量测条件如下：电信号频率为200MHz至15GHz、扫描数为6401点、校正方式为TRL。
最后，以电信号频率为8GHz的情况，判别相应带状线的信号传递损失的程度，检测结果记载于表2中。其中，当信号传递损失的绝对值越小，代表信号在传递时的损失程度越少。具体而言，当信号传递损失的绝对值大于0.82dB/in时，代表信号传递表现差；当信号传递损失的绝对值小于或等于0.82dB/in时，代表信号传递表现良好；而当信号传递损失的绝对值小于0.75dB/in时，代表信号传递表现最佳。
表2
Figure PCTCN2020072282-appb-000003
根据上述实施例1-14，当处理面的空隙体积(Vv)及峰度(Sku)分别位于0.4～2.2μm 3/μm 2和1.6～4.0的范围时，对于相应的铜箔基板和印刷电路板而言，表面处理铜箔和相接触的载板除了可以具有较佳的剥离强度(例如高于或等于5.01lb/in)，也可以同时降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于或等于0.82dB/in)。
根据本发明的实施例1-12，当处理面的空隙体积(Vv)及峰度(Sku)分别位于0.4～2.2μm 3/μm 2和1.6～4.0的范围时，且算术平均波度(Wa)小于或等于0.40μm时，对于相应的铜箔基板和印刷电路板而言，可以进一步降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于或等于0.77dB/in)。
根据本发明的实施例1-12，当处理面的空隙体积(Vv)及峰度(Sku)分别位于0.4～2.2μm 3/μm 2和2.0～4.0的范围时，对于相应的铜箔基板和印刷电路板而言，可以进一步降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于或等于0.77dB/in)。
根据本发明的上述各实施例，通过将表面处理铜箔的处理面的上述表面粗糙度参数控制在特定范围，则对于相应的铜箔基板和印刷电路板而言，除了可以提升表面处理铜箔和载板之间的附着性(剥离强度大于5lb/in)，也可以同时降低高频电信号在导电图案中传递时所产生的信号传递损失(信号传递损失的绝对值小于0.75dB/in)。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

  1. 一种表面处理铜箔，其特征在于，包括一处理面，其中所述处理面的空隙体积(Vv)为0.4至2.2μm 3/μm 2，且所述处理面的峰度(Sku)为1.6至4.0。
  2. 如权利要求1所述的表面处理铜箔，其特征在于，所述处理面的算术平均波度(Wa)小于或等于0.40μm。
  3. 如权利要求1所述的表面处理铜箔，其特征在于，所述处理面的峰度(Sku)为2.0至4.0。
  4. 如权利要求3所述的表面处理铜箔，其特征在于，所述处理面的算术平均波度(Wa)为0.10至0.40μm。
  5. 如权利要求4所述的表面处理铜箔，其特征在于，所述处理面的空隙体积(Vv)为0.4至1.9μm 3/μm 2，且所述处理面的算术平均波度(Wa)为0.10至0.30μm。
  6. 如权利要求1所述的表面处理铜箔，其特征在于，所述处理面的核心部空隙体积(Vvc)为0.3至2.1μm 3/μm 2。
  7. 如权利要求1所述的表面处理铜箔，其特征在于，所述处理面的波谷部空隙体积(Vvv)为0.01至0.10μm 3/μm 2。
  8. 如权利要求1至7中任一项所述的表面处理铜箔，其特征在于，所述表面处理铜箔进一步包括：
    一主体铜箔；以及
    一表面处理层，设置于所述主体铜箔的至少一表面，其中，所述表面处理层的外侧为所述处理面。
  9. 如权利要求8所述的表面处理铜箔，其特征在于，所述主体铜箔为压延铜箔。
  10. 如权利要求8所述的表面处理铜箔，其特征在于，所述主体铜箔为电解铜箔，且包括一辊筒面以及一沉积面，所述表面处理层设置在所述辊筒面。
  11. 如权利要求10所述的表面处理铜箔，其特征在于，所述表面处理层包括一子层，所述子层为粗化层。
  12. 如权利要求11所述的表面处理铜箔，其特征在于，所述表面处理层还进一步包括至少一个其他的子层，所述至少一个其他的子层选自由钝化层及耦合层所构成的群组。
  13. 如权利要求12所述的表面处理铜箔，其特征在于，所述钝化层包含至少一金属，所述金属选自由镍、锌、铬、钴、钼、铁、锡、及钒所构成的群组。
  14. 一种铜箔基板，其特征在于，包括：
    一载板；以及
    一表面处理铜箔，设置于所述载板的至少一表面，其中所述表面处理铜箔包括面向所述载板的一处理面，且所述处理面的空隙体积(Vv)为0.4至2.2μm 3/μm 2，所述处理面的峰度(Sku)为1.6至4.0。
  15. 如权利要求14所述的铜箔基板，其特征在于，所述表面处理铜箔的所述处理面直接接触所述载板。
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