WO2009114670A2 - Ensemble de dés interconnectés électriquement montés sur un support - Google Patents

Ensemble de dés interconnectés électriquement montés sur un support Download PDF

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Publication number
WO2009114670A2
WO2009114670A2 PCT/US2009/036921 US2009036921W WO2009114670A2 WO 2009114670 A2 WO2009114670 A2 WO 2009114670A2 US 2009036921 W US2009036921 W US 2009036921W WO 2009114670 A2 WO2009114670 A2 WO 2009114670A2
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WO
WIPO (PCT)
Prior art keywords
die
support
sites
additional
stack
Prior art date
Application number
PCT/US2009/036921
Other languages
English (en)
Other versions
WO2009114670A3 (fr
Inventor
Simon J.S. Mcelrea
Marc E. Robinson
Lawrence Douglas Andrews, Jr.
Original Assignee
Vertical Circuits, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vertical Circuits, Inc. filed Critical Vertical Circuits, Inc.
Priority to JP2010550853A priority Critical patent/JP5763924B2/ja
Priority to CN200980112952XA priority patent/CN101999167B/zh
Publication of WO2009114670A2 publication Critical patent/WO2009114670A2/fr
Publication of WO2009114670A3 publication Critical patent/WO2009114670A3/fr

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Definitions

  • This invention relates to electrical interconnection of integrated circuit chips and, particularly, to mounting interconnected stacked die onto a support.
  • a typical semiconductor die has a front ("active") side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges.
  • Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed.
  • Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die.
  • Other die as provided have die pads arranged in one or two rows at the front side near the center of the die, and these may be referred to as center pad die.
  • the die may be "rerouted" to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die.
  • Semiconductor die may be electrically connected with other circuitry in a package, for example on a package substrate or on a leadframe, by any of several means. Such z-interconnection may be made, for example, by wire bonds, or by flip chip interconnects, or by tab interconnects.
  • the package substrate or leadframe provides for electrical connection of the package to underlying circuitry (second-level interconnection), such as circuitry on a printed circuit board, in a device in which the package is installed for use.
  • U.S. Patent No. 7,245,021 describes a vertically stacked die assembly including a plurality of integrated circuit die electrically interconnected by "vertical conducting elements". The die are covered with an electrically insulative conformal coating. The vertical conducting elements are formed of a conductive polymer material, applied adjacent the edge of the die.
  • the die are provided with metallic conducting elements, each having one end attached to electrical connection points at the die periphery and having the other end embedded in a vertical conducting polymer element.
  • U.S. Patent No. 7,215,018 describes a similar vertically stacked die assembly mounted onto a ball grid array (“BGA”) or land grid array (“LGA”) substrate.
  • the stacked die assembly is mounted onto the BGA or LGA substrate by electrical and physical connection of the vertical conducting elements ("vertical interconnects") to electrical connection lands on the surface of the substrate.
  • the electrical connection is said to be done by use of a conductive polymer "dot" or "puddle” between the vertical interconnect of the stack of die and the substrate.
  • the substrate can include means for making electrical connection between the bottom of the substrate and a printed circuit board, such as solder balls or bumps, or "LGA contacts” on the bottom of the substrate.
  • the invention features electrical connection of stacked die assemblies to connection sites on any support, without electrical connection to any interposed die or substrate or leadframe or package.
  • Each die in the stacked die assembly has peripheral interconnect terminals, and the die in the stack are electrically interconnected by lines or traces of an electrically conductive material, which may be an electrically conductive polymer, or an electrically conductive ink, that contacts interconnect terminals on the respective die.
  • the interconnect material may include a curable polymer.
  • the stacked die assembly may be mounted directly onto a surface of the support to which the die stack assembly is electrically connected, Or, the stacked die assembly may be mounted onto a surface of an additional support (such as an additional die or substrate or leadframe or package) and electrically connected to connection sites on the support.
  • the additional support includes a semiconductor construct that is electrically connected to additional connection sites on the support to which the stacked die assembly is electrically connected.
  • the invention features a support having electrical connection sites at a surface thereof, and a stacked die assembly mounted onto the surface and electrically connected to one or more of the connection sites, wherein each die in the stacked die assembly has peripheral interconnect terminals, and the die in the stack are electrically interconnected by lines or traces of an electrically conductive material, which may be an electrically conductive polymer, or an electrically conductive ink, that contacts interconnect terminals on the respective die.
  • an electrically conductive material which may be an electrically conductive polymer, or an electrically conductive ink
  • the traces of electrically conductive material that interconnect the die in the stack may also connect to the connection sites on the support.
  • the die stack is positioned on or in relation to the support so that the interconnect terminals on the die are suitably aligned with corresponding connection sites on the support circuitry, and then the interconnect material is applied in a suitable pattern over the interconnect terminal on the die and the connection sites on the support.
  • the interconnect material includes a curable polymer
  • the material may be cured following the application of the curable material to the die and the connection sites.
  • an additional quantity of an electrically conductive material may be provided to make contact between the die stack interconnects and the connection sites on the support.
  • the die stack assembly interconnection is completed prior to positioning the assembly on or in relation to the support, and in such embodiments where the interconnect material includes a curable polymer, the material may be cured or partially cured following the application of the curable material to the die and prior to positioning the assembly on or in relation to the support. Cured or partially cured interconnects can improve mechanical stability of the stack assembly during subsequent handling, such as during installation of the assembly on the support.
  • the additional material may be applied to the connection sites on the support, or to contact sites on the interconnects, prior to positioning the assembly on or in relation to the support.
  • the additional material may be the same as, or may be different from, the material of the die stack interconnects; and, where the additional material is a curable polymer, a final cure is carried out following the positioning of the assembly on or in relation to the support.
  • the invention features a first support having electrical connection sites at a surface thereof, a second support mounted on the first support, and a stacked die assembly mounted onto a surface of the second support and electrically connected to one or more of the connection sites on the first support, wherein each die in the stacked die assembly has peripheral interconnect terminals, and the die in the stack are electrically interconnected by lines or traces of an electrically conductive material, which may be an electrically conductive polymer, or an electrically conductive ink, that contacts interconnect terminals on the respective die.
  • the additional support is electrically connected to the first support.
  • at least some of the electrical connections of the die in the stacked die units or assemblies are not electrically connected to the additional support and, in some such embodiments there is no direct electrical connection between the die unit or assembly and interconnect pads or sites on the additional support.
  • the additional support serves as a mechanical or structural support for the die assembly or unit, and includes no electrical or electronic components. It may include, for example, a dummy die; or a sheet of dielectric material; or a heat dissipating sheet or block of a material having a high heat capacity or high thermal conductivity.
  • the additional support may include only passive electrical features.
  • the passive electrical features in the additional support may be electrically connected to one or more sites in the first support; or they may be connected to a selected number (less than all) of the interconnections in the die unit or assembly; or they may be connected to a selected number (less than all) of the interconnections in the die unit or assembly as well as to one or more sites in the support.
  • the additional support may include, for example, a ground plane.
  • the additional support may include electronic circuitry, and may include one or more semiconductor devices.
  • the additional support may be a semiconductor package; or an additional die.
  • connection sites in the additional support may be electrically connected to sites in the first support; or to a selected number (less than all) of the interconnections in the die unit or assembly; or to a selected number (less than all) of the interconnections in the die unit or assembly as well as to one or more sites in the support.
  • the additional support includes electronic circuitry
  • the electronic circuitry in the second support and the die assembly or unit are separately connected to the first support. That is, the electrical connections between the die assembly or unit and the first support bypass the second support, and the respective connections may be made to separate sets of sites on the first support.
  • the additional support is a die; pads on the die are connected to a second set of bond sites on the first support, and interconnects in the die assembly or unit are connected to a first set of bond sites on the first support.
  • the additional support is a semiconductor package, and lands on the package are connected to a second set of bond pads on the first support, and interconnects in the die assembly or unit are connected to a first set of bond sites on the first support.
  • the interconnect material is an electrically conductive polymer, such as an electrically conductive epoxy, for example; or an electrically conductive ink.
  • the electrically conductive polymer is a curable polymer, and may be curable in stages.
  • the interconnect material may include, for example, a matrix containing an electrically conductive filler; the matrix may be a curable or settable material, and the electrically conductive fill may be in particulate form, for example, such that when the matrix sets or is cured, the material is itself electrically conductive.
  • the material is a conductive epoxy such as a silver filled epoxy; for example, a filled epoxy having 60 - 90% (more usually 80 - 85%) silver may be suitable.
  • the epoxy is cured following dispensing, resulting in some embodiments in a fusion of the series of dots into a continuous interconnect strand.
  • the interconnect material can be applied using an application tool such as, for example, a syringe or a nozzle or a needle.
  • the material exits the tool in a deposition direction generally toward the die pads or interconnect terminals, and the tool is moved over the presented stack face in a work direction.
  • the material may be extruded from the tool in a continuous flow, or, the material may exit the tool dropwise.
  • the material exits the tool as a jet of droplets, and is deposited as dots which coalesce upon contact, or following contact, with a stack face surface.
  • the deposition direction is generally perpendicular to the sidewall surface of the die, and in other embodiments the deposition direction is at an angle off perpendicular to the sidewall surface of the die.
  • the tool may be moved in a generally linear work direction, or in a zig-zag work direction, depending upon the location on the various die of the corresponding terminals to be connected.
  • a plurality of interconnect traces are formed in a single operation, and in some such embodiments all the interconnect traces on a given stacked assembly are formed in a single operation (or in a number of operations fewer than the number of traces).
  • the application tool may in such instances include a number of needles or nozzles ganged together in a row generally parallel to the die edges.
  • the interconnects are applied by printing, for example using a print head (which may have a suitable array of nozzles), or for example by screen printing or using a mask.
  • the interconnects are formed using a photosensitive material, and photoexposure procedure to pattern the material.
  • the material may be a photocurable electrically conductive material, such as a metal-filled photopolymerizable organic polymer, for example; and the material is applied generally over an area that includes pads or interconnect terminals, then is exposed to light in the desired patterned, and the uncured material is removed.
  • the additional small amount of material may be applied to the die stack interconnects in a transfer operation, for example by dipping shallowly into a reservoir of the interconnect material, or by screen printing or stencil printing, for example.
  • the additional small amount of material may be applied to the connection sites on the support by a dispense operation.
  • the material may be dispensed using an application tool, and the material may exit the tool under control of an apparatus using pressure dispense (for example under a controlled time and pressure regime), piston dispense (for example under a controlled time and piston travel regime), or auger dispense (for example under a controlled time and augur rotation regime).
  • the material may be applied to the connection sites on the support by a patterned print operation, using for example an array of jets or apertures.
  • the material may be dispensed by droplets, or in a continuous stream.
  • the stacked die assembly can be electrically connected directly onto any electrical connection sites on any support, using an electrically conductive polymer or electrically conductive ink.
  • Suitable supports include, in one general category, any dielectric substrate carrying patterned electrical conductors in one or more layers.
  • the dielectric substrate may be or include a natural or synthetic organic or inorganic material.
  • circuitry formed on or in a glass or ceramic or silicon or other dielectric sheet or film can constitute a suitable support.
  • Other suitable supports include conventional circuit boards such as printed circuit boards, which may be, for example, motherboards, or module boards, or daughterboards.
  • the invention features stacked die units or stacked die assemblies electrically interconnected with circuitry on a support in a device for use.
  • the stacked die assembly is interconnected such that the active side of the die faces toward the underlying circuitry; in other embodiments the stacked die assembly is interconnected such that the back side of the die faces toward the underlying circuitry.
  • one or more die in the stack may be oriented facing away from the underlying circuitry while one or more other die in the stack face toward the underlying circuitry.
  • the die or the stack of die is oriented so that the plane of the die is nonparallel with the die mount surface of the support; in some such embodiments the plane of the die is oriented perpendicular to the plane of the die mount surface of the support; or is oriented at some other angle between parallel and perpendicular,
  • the die are provided with an electrically insulative conformal coating over at least the front surface and the sidewalls adjacent the die margin on which the interconnect pads are arranged, and in some such embodiments the die are provided with a electrically insulative conformal coating over the front surface, the back surface, and the sidewall surfaces of the die.
  • the conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that it may contact.
  • the material of the conformal coating includes an organic polymer, for example a polymer of p-xylene or a derivative thereof, such as a polyxylylene polymer, e.g., a parylene C or a parylene N, or a parylene A, or a parylene SR.
  • the conformal coating is formed by deposition, for example by vapor deposition, or liquid phase deposition, or by solid phase deposition.
  • an underfill material is applied between the die stack and the support. In some embodiments it may be preferred to select an underfill material that is rigid, to provide mechanical stability to the die and support assembly.
  • the assemblies according to the invention can be used for building computers, telecommunications equipment, and consumer and industrial electronics devices.
  • FIG. 1 is a diagrammatic representation illustrating a generalized support to which a die assembly can be electrically connected according to the invention.
  • FIG. 2 is a diagrammatic sketch in partial sectional view showing a stack of four die mounted on a BGA substrate.
  • FIGs. 3A - 3F are diagrammatic sketches in sectional view showing examples of various die edge configurations.
  • FIGs. 4A - 4F are diagrammatic sketches in sectional view showing stacks of die having die edge configurations as in FIGs. 3A - 3F.
  • FIGs. 5A - 5F are diagrammatic sketches in sectional view showing stacks of die having die edge configurations as in FIGs. 3A - 3F, in which the respective die are covered by a conformal dielectric coating.
  • FIGs. 6A, 6B are diagrammatic sketches in plan and sectional views illustrating die stacked in an offset configuration.
  • FIGs. 7A - 7C are diagrammatic sketches in sectional views illustrating die stacks constructed generally as in FIGs. 6A, 6B mounted on a support according to examples of the invention.
  • FIGs. 8 and 9 are diagrammatic representations each illustrating generalized first and second supports to which a die assembly can be mounted and electrically connected according to other embodiments of the invention.
  • FIGs. 1OA, 10B are diagrammatic sketches in plan and sectional views illustrating a die assembly in an offset configuration, mounted onto a die (serving as a second substrate) and electrically connected to a first substrate according to an embodiment of the invention.
  • stacked die assemblies are electrically connected to interconnect sites on any support, without an interposed substrate or leadframe; and electrical interconnection of the die in the stack, and of the die stack to the support, is made by way of an electrically conductive polymer or an electrically conductive ink, without solder, or wires, sockets, pins, or other connectors.
  • FIG. 1 illustrates symbolically in a sectional view a generalized support 10, having a connection side 12 and a reverse side 14. Interconnect sites 16 are present at least at the connection side of the support.
  • the thickness of the support is not indicated in the FIG., as the support may range from very thick to very thin, depending among other things upon the character of the support; for instance, a printed circuit board may have a greater thickness than substrate having two metal layers separated by a single dielectric layer.
  • the support may have greater or lesser length and width dimensions, as suggested by dashed arrows 11 and 13.
  • the die stack may be directly connected to interconnect sites at an attachment side of any of a wide variety of categories of supports, including for example: other die, including for example logic chips; other die stacks; other packaged devices or components; circuit boards, including system circuit boards, motherboards, daughterboards, module boards, and the like; leadframes; and the like.
  • FIG. 2 shows generally at 20 such a stack 21 of four die 12, 14, 16, 18 mounted on a BGA substrate 22 in a partial sectional view.
  • each die e.g., die 12
  • Adjacent die in the stack may optionally be mounted one upon the other using an adhesive.
  • Adjacent with reference to die in a stack means the die are vertically adjacent; die may also be horizontally adjacent, for example in a wafer or in a die array or, in some configurations, on a common support.).
  • a film adhesive piece is employed (e.g., 33 between adjacent die 14 and 16).
  • Bond pads 228 are arranged at the die mount surface 224 of the substrate 22.
  • the die are arranged one over another with the respective interconnect terminals 129, 149, 169, 189 aligned vertically (that is, generally perpendicular to the front or back side of the die).
  • the die stack 21 is mounted on the substrate with the respective interconnect terminals aligned at least partly over the respective bond pad 228.
  • Solder balls 227 are attached in a reflow process to an array of lands 226 exposed at the side of the substrate 225 opposite the die mount side 224.
  • the array of solder balls provides for second-level interconnection of the assembly 20 onto underlying circuitry in a device for use, for example on a leadframe, or a printed circuit board, for example.
  • the die stack may be mounted on the substrate using an adhesive.
  • the die 18 adjacent the substrate 22 is affixed to the die mount side 224 of the substrate 22 using a film adhesive 37.
  • a configuration as shown in FIG. 2 may be made by forming the die stack and then mounting the die stack on a substrate 22; or, alternatively, it may be made in a build-up manner, by stacking the die serially on the substrate, that is by mounting die 18 on the substrate 22 (optionally using an adhesive 37), then mounting die 16 on die 18 (optionally using an adhesive 33), then mounting die 14 on die 18, efc, and then applying the interconnect material to the terminals on the die as well as to the bond pad on the substrate in a continuous operation.
  • FIG. 2 shows the stacked die assembly on the substrate following cure of the interconnect.
  • the assembly in this example has a stack of four die mounted on a substrate, in which the die are electrically interconnected to one another, and to the substrate circuitry (z-interconnection) by the interconnect 410; that is the interconnect 410 provides electrical continuity between the interconnect terminals 129, 149, 169, 189 and the bond pad 228 on the substrate 22.
  • FIGs. 3A - 3F show examples of various die edge configurations in die to be interconnected according to various embodiments of the invention.
  • FIG. 3A shows a die having an "off-die" interconnect. The die is shown in a partial sectional view, having an active side 315 at which the integrated circuitry 311 of the die is formed, and a die sidewall 319. In an off die configuration an interconnect terminal 322 is bonded to an interconnect pad (die pad) 313.
  • the die pad may be a peripheral die pad in the die as provided, or it may be situated at or near the die periphery as a result of rerouting of the die circuitry.
  • the interconnect terminal may be, for example, a wire (formed for example in a wire bond operation) or a tab or ribbon (formed for example in a ribbon bond operation).
  • the interconnect terminal 322 extends outwardly beyond the die edge 319 (hence, "off-die" terminal).
  • FIG. 3B shows a die having a bump or glob 323 of an electrically conductive polymer material deposited onto the die pad 313.
  • the glob may be shaped so that it extends toward the die edge, and may extend to the die edge or (as in the example shown in FIG. 3B) slightly beyond the die edge 19; it may be in the shape of a thumb, for example. Alternatively, the glob may be formed entirely above the pad, as shown for example in FIG. 5B.
  • the conductive polymer material may be, for example, a curable conductive polymer such as a conductive epoxy.
  • FIG. 3C shows a die having an interconnect terminal 324 formed in or at the active side of the die, at or near the margin of the die where the active side 315 of the die meets the die sidewall 319.
  • Such a marginal interconnect terminal may be an extension of a die pad, for example, and may be situated at or near the die margin as a result of rerouting of the die circuitry.
  • FIG. 3D shows a die having an interconnect terminal 326 formed in the die sidewall 319.
  • the interconnect terminal may be connected to the integrated circuitry of the die by attachment of a pad of conductive material to an extension of the die pad, for example, or to rerouting circuitry.
  • FIG. 3E shows a die having an interconnect terminal formed so that it wraps around a chamfer that is formed at the front side die edge (at the intersection of the die sidewall 319 with active side 315 of the die).
  • Such a wraparound terminal has a terminal portion 327 on the chamfer, and a terminal portion 328 on the die sidewall.
  • a similar wraparound terminal may be formed over the back side die edge (at the intersection of the die sidewall with back side 317 of the die), where no chamfer is present.
  • FIG. 3F shows a die having an interconnect terminal formed so that it wraps around a chamfer that is formed at the front side die edge (at the intersection of the die sidewall with active side 315 of the die), and further around a chamfer that is formed at the back side die edge (at the intersection of the die sidewall with back side 317 of the die).
  • Such a wraparound terminal has a terminal portion 327 on the front edge chamfer, and a terminal portion 328 on the die sidewall, and a terminal portion 329 on the back edge chamfer.
  • FIGs. 4A - 4F show arrangements of die as in, respectively, FIGs. 3A - 3F, oriented one over another (in these examples, each having three die in the stack). The die are shown
  • FIGs. 4A and 4B show, the off-die terminals 322, 323 project at the stack face, making them available for connection by a variety of methods.
  • FIG. 4C shows, interconnect terminals 324 in the margin of the active side of the die are beneath the margins of die stacked over them (except that the active side of one of the die is exposed and readily accessible for interconnection).
  • 4D, 4E, and 4F show, by contrast, interconnect terminals 326 formed in the die edge (FIG. 4D), and wraparound interconnect terminals 327, 328 (FIG. 4E) or 327, 328, 329 (FIG. 4F) are presented at the stack face for interconnection.
  • FIGs. 5A - 5F show stacked die arranged generally as in FIGs. 4A - 4F, respectively.
  • each die 52 is covered with a conformal insulative coating 54, having openings 55 over the die pads.
  • FIG. 5A shows a three-die stack of die having off-die terminals 522. Because the off die interconnect terminals in this example stand above the front side of the die, adjacent die in the stack are separated by a space 53.
  • a spacer may optionally be interposed in the space 53 to support adjacent die; optionally the spacer may be a film adhesive of suitable thickness both to fill the space and to affix the die to one another.
  • the off-die interconnect terminals 522 are vertically aligned, and are presented at the stack face as indicated by arrows 50, so that they may be readily interconnected using, for example, a vertically-oriented interconnect, as described generally in U.S. 7,245,021 , for example,
  • FIG. 5B shows a three-die stack of die having globs 523 of an electrically conductive polymer material deposited onto the die pad.
  • the glob is formed entirely above the exposed die pad, and does not extend toward the stack face (compare, FIGs. 3B, 4B,
  • the globs stand above the front side of the die, so that adjacent die in the stack are separated by a space 53 and, optionally, a spacer may be interposed in the space 53 to support adjacent die; and optionally the spacer may be a film adhesive of suitable thickness both to fill the space and to affix the die to one another.
  • FIG. 5C shows a three-die stack of die having an interconnect terminal 524 formed in or at the active side of the die, at or near the margin of the die where the active side of the die meets the die sidewall.
  • the interconnect terminals 524 of lower die in the stack that is, all the die except the uppermost die in the stack
  • Interconnection of die in such a stack may be made by a vertically-oriented interconnect at the stack face, provided that the interconnect intrudes between adjacent die onto the interconnect terminals 524.
  • the interconnect material as applied (such as an electrically conductive epoxy) has some capacity to flow into the space at the margin between adjacent die, to make electrical connection with interconnect terminals in the margin at the active side of the die. This necessitates providing a separation 53 between adjacent die sufficient to permit the intrusion.
  • a spacer may optionally be interposed in the space 53 to support adjacent die; and optionally the spacer may be a film adhesive of suitable thickness both to fill the space and to affix the die to one another.
  • FIGs. 5D, 5E, and 5F shows a three-die stack of die having an interconnect terminal formed in or at the die sidewall and presented at the stack face as shown by the arrows 50.
  • the conformal coating covers at least the front side and the back side of the die.
  • Such a configuration may be made by coating the entirety of all surfaces of the die and then forming openings through the coating to expose the underlying interconnect terminals; or such a configuration may be made by coating only the front surface and the back surface of the die, leaving the interconnect terminals uncoated. Because the interconnect terminals are presented at the stack face, and because the interconnect terminals do not stand above the front side of the die, no space is required between adjacent die in the stack.
  • the surface of the coating at the backside of an upper die can rest directly upon the surface of the coating on the front ("active") side of the adjacent lower die in the stack.
  • Stacked die in configurations as shown for example in FIGs. 5D, 5E, and 5F can be readily interconnected using, for example, an interconnect applied to the stack face, that is, by an interconnect applied to the sidewalls of the die in the stack.
  • Die in a stack electrically interconnected in this manner can according to the invention be electrically connected with connection sites on any of a variety of supports by direct connection without use of solder and without any interposed substrate or leadframe.
  • the die are stacked so that the die sidewalls are vertically aligned, substantially flush with an imaginary plane perpendicular to the plane of the x-y plane of the die, the plane being referred to at some points as the stack face. Because the interconnect material is applied in a generally liquid state, the interconnect material as applied is flowable or deformable to some extent. Accordingly, misalignment of the die sidewalls can be tolerated without compromising the integrity of the interconnections.
  • the die are offset by design, so that the stack has a stepped configuration at the die edges having interconnect terminals to be interconnected. This may be particularly useful where the interconnect terminals are not directly accessible at the die sidewall, for example as for die configured as shown in FIG. 5C.
  • An interconnected die stack having offset die is shown by way of example in FIGs. 6A, 6B.
  • FIG. 6A shows in a plan view an arrangement of stacked die, each die having interconnect terminals arranged in one margin adjacent a front die edge, and showing interconnect material formed over corresponding interconnect terminals; and FIG. 6B shows the stack in a sectional view as indicated at 6B - 6B in FIG. 6A.
  • the interconnect terminals are in this example situated in a row alongside a front die edge.
  • the die in this example is covered on all surfaces (back surface, front surface, sidewalls) by a conformal coating, provided with openings exposing the interconnect terminals.
  • Successive coated die in the stack may, as in these examples, rest directly one upon another, such that the coating on the back side of an upper die can contact the coating on the front side of the underlying die.
  • the die are all of the same size, and the pads are located along only one die edge. Accordingly, successive die in the stack are displaced only in a direction orthogonal to a die edge along which the pads are situated.
  • Each die need be displaced only to an extent at least sufficient to expose enough of the area of the pads in the underlying die to permit the interconnect material to make reliable electrical contact with the pads and, accordingly, the extent of displacement, indicated for example at d in the FIGs., is shown greater than necessary. In principle, the displacement may be sufficient if at least a fraction of the area of the pads is left uncovered by the overlying die.
  • the interconnect material as deposited may not contact the pad over an area great enough to establish a reliable electrical connection when the material is cured. It may be preferred to minimize the extent of displacement, so as to minimize the footprint of the stack.
  • the stack may be supported, for example, at the back side of the lowest of the die in the stack, and the interconnect material may be applied along a trajectory over the pads to be connected and the die surfaces between them.
  • the interconnect material may be applied using an application tool such as, for example, a syringe or a nozzle. The material exits the tool in a deposition direction generally toward the interconnect terminals, and the tool is moved over the die stack face in a work direction.
  • Die stacks having resulting traces of interconnect material are shown by way of illustration at 62 in FIGs. 6A, 6B. This procedure is repeated to deposit traces connecting all the pads for which electrical interconnection is desired, and following deposition the material is cured.
  • Assemblies of electrically interconnected stacked die can optionally be tested prior to further processing.
  • Complete assemblies can be mounted on a support, and interconnected die in the stack can be connected with underlying circuitry by way of secured electrical contact with the interconnections.
  • a printed circuit board or package substrate can be provided, having bond pads arranged at a die attach side to correspond with the ends 61 or 63 of the die stack interconnects. Referring to FIG.
  • the interconnect 62 has an end 63 at the margin of the active side of a die at the top (or, if the assembly is inverted, at the bottom) of the assembly, and an end 61 at a back side edge of a die at the bottom (or, if the assembly is inverted, at the top) of the assembly.
  • a support such as a circuit board, for example, can be provided having z-interconnect sites arranged in a manner corresponding to the arrangement of interconnect ends 61 or 63.
  • the assembly can be mounted on the support for example with the active sides of the die facing toward the support, and with the interconnect ends 63 aligned with and contacting the z-interconnect sites (see, for example, FIG.
  • the assembly can be mounted with the die oriented perpendicularly (or at any other angle) to the support (see, for example, FIG. 7C), with the interconnect ends 61 aligned with and contacting the z-interconnect sites.
  • the die in the stacked die assembly may be all of the same size, as shown for example in the FIGs. 6A, 6B, but die of different sizes may according to the invention be stacked and interconnected by conductive polymer traces.
  • a smaller die may be stacked on a larger die, with the smaller die situated so that peripheral die pads in the margin near at least one die edge of the larger die are available for interconnection.
  • the stack of die may appear in section as a stepped pyramid; or, the die may be displaced in one direction with respect to a first die edge, but vertically interconnected on another die edge.
  • An upper die may be larger in one dimension (that is, the die may be same width but one longer than the other), or in both directions (that is, one die both wider and longer than the other) than a lower die.
  • a 10 x 10 mm die may be stacked over a 10 x 12 mm die having peripheral pads at the shorter edges.
  • the smaller die is situated over the larger die such that the die pads at the narrow ends of the larger die are exposed adjacent two edges of the smaller die.
  • a 10 x 10 mm die may be stacked over a 12 x 12 mm die, and situated such that peripheral pads along any one or more (or all four) edges of the larger die are available for interconnection.
  • Stacked die assemblies according to the invention may have as many die as may be desired, and there may as a matter of mechanical design be no upper limit.
  • the illustrated examples show three or four or seven die in each stack, but assemblies having two or more die in the stack are contemplated. Particularly, for example, assemblies having four, or six, or eight, or 16 or 17 die may be made and mounted without solder and without an interposed substrate or leadframe directly onto a support.
  • larger stacked die assemblies may be made by constructing stacked die units in a modular design, and then stacking modular units.
  • the stackable modular units can be robust and testable. For example, particular two-die units and four die units may constitute modules; from these modules a six-die assembly may be made by stacking a two-die unit and a four-die unit, or an eight-die assembly may be made by stacking two four-die units, for example.
  • stacked die units or assemblies constructed according to the invention can be mounted on and electrically interconnected with circuitry directly on a support.
  • a stacked die unit can be mounted upon a circuit side of package substrate, and electrically interconnected by connection of all or selected ones of the interconnect ends of the unit with bond pads on the substrate.
  • the substrate may be any of a variety of package substrates, including for example laminated or buildup substrates having one or more patterned metal films and one or more dielectric layers, such a BT substrates or ceramic substrates for example; and flex substrates, for example.
  • a stacked die unit can be mounted upon the active side of another die, and electrically interconnected by connection of all or selected ones of the interconnect ends of the unit with pads on the die.
  • a die stack assembly can be mounted on a leadframe, and electrically interconnected by connection of al!
  • a die stack assembly can be mounted on a printed circuit board (such as a motherboard, for example), and electrically interconnected by connection of all or selected ones of the interconnect ends of the unit with sites on the printed circuit.
  • the stacked die units or assemblies may be electrically connected to a first support by connection of all or selected ones of the interconnect ends of the unit with sites on the support, and mounted on an additional support. The additional support may itself be electrically connected to the first support.
  • the additional support may have no electrical or electronic components, so that it serves simply as a mechanical or structural support for the die assembly or unit. It may include, for example, a dummy die; or a sheet of dielectric material; or a heat dissipating sheet or block of a material having a high heat capacity or high thermal conductivity.
  • the additional support may include only passive electrical features.
  • the passive electrical features in the additional support may be electrically connected to one or more sites in the first support; or they may be connected to a selected number (less than all) of the interconnections in the die unit or assembly; or they may be connected to a selected number (less than all) of the interconnections in the die unit or assembly as well as to one or more sites in the support. It may include, for example, a ground plane.
  • the additional support may include electrical circuitry. It may include, for example, a printed circuit board; or a package substrate; or a leadframe. [0079]
  • the additional support may include electronic circuitry, and may include one or more semiconductor devices.
  • the additional support may be a semiconductor package; or an additional die.
  • one or more connection sites in the additional support may be electrically connected to sites in the first support; or to a selected number (less than all) of the interconnections in the die unit or assembly; or to a selected number (less than all) of the interconnections in the die unit or assembly as well as to one or more sites in the support.
  • the additional support includes electronic circuitry
  • the electronic circuitry in the second support and the die assembly or unit are separately connected to the first support. That is, the electrical connections between the die assembly or unit and the first support bypass the second support, and the respective connections may be made to separate sets of sites on the first support.
  • the additional support is a die; pads on the die are connected to a second set of bond sites on the first support, and interconnects in the die assembly or unit are connected to a first set of bond sites on the first support.
  • the additional support is a semiconductor package, and lands on the package are connected to a second set of bond pads on the first support, and interconnects in the die assembly or unit are connected to a first set of bond sites on the first support.
  • FIG. 8 illustrates symbolically in a sectional view a generalized second support 80, having a die mount side 82 and a reverse side 84., arranged generally parallel to a generalized first support 10 configured as described in FIG. 1.
  • FIG. 9 illustrates symbolically in a sectional view a generalized second support 90, having a die mount side 92 and a reverse side 94., arranged generally perpendicular to a generalized first support 10 configured as described in FIG. 1.
  • a die assembly or unit can be mounted on the die mount side 82 or 92 of the second support 80 or 90, and the die assembly can be electrically connected to the Interconnect sites 16 at the connection side of the first support, generally as described above.
  • the thickness of the second support is not indicated in the FIG., as the support may range from very thick to very thin, depending among other things upon the character of the second support.
  • a printed circuit board may have a greater thickness than a laminated substrate having two metal layers separated by a single dielectric layer, or than a flex substrate; and, for instance, a package may have greater thickness than a die.
  • the first and second supports may have greater or lesser length and width dimensions, as suggested in FIGs. 8 and 9 by dashed arrows 11 and 13 and arrow 81.
  • FIGs. 10A and 10B illustrate an example of an embodiment in which the additional support is a die, mounted onto and electrically connected to the first support by flip chip interconnect; and in which the die assembly is an offset stack of die that is connected to the first support and is not electrically connected to the flip-chip die.
  • the first support HO has a circuit surface 112 at which a row of first bond sites 116 and an array of second bond sites 118 exposed for electrical connection.
  • the additional support 180 is a die (a "supporting die") having an array of pads 184 at one surface, and having solder bumps 186 attached to the die pads 184.
  • the array of die pads 184 and the array of second bond sites 118 are arranged so that the bumps align with corresponding second bond sites when the supporting die is positioned in a die-down orientation over the first support.
  • the row of first bond sites 116 is arranged so that when the supporting die 180 is so aligned, an edge of the supporting die 180 is parallel to and adjacent to the row of first bond sites 116 or (as in the example shown in the FIGs.) partly overlying the row of first bond sites 116.
  • the bumps 186 are mated to and electrically connected to the pads 118 by reflow of the solder bumps.
  • the backside 182 of the die 180 faces away from the first support, and provides a mounting surface for the die assembly 60, which is configured in this example generally as described with reference to FIGs. 6A, 6B.
  • the interconnect edge of the die assembly is situated near (and in this example is set back slightly from) the edge of the die 180 that is oriented parallel the row of bond sites 116.
  • the die-to-die electrical interconnects are extended as illustrated at 162, to connect the electrical interconnects 62 to corresponding respective first bonds sites 116. [0084] Referring to FIGs. 1OA, 10B, various additional embodiments are contemplated.
  • the die may be electrically connected to the first support by tab interconnects.
  • the second support may be a leadframe package, oriented with exposed package leads or lands facing the first support, and the package may be mounted in a conventional surface mount fashion; or, for example, the second support may be a LGA or BGA package, oriented with the land side facing the first support, and the package may be mounted and electrically connected in a conventional solder ball grid or surface mount fashion.
  • the supporting die may have any of a variety of functionalities.
  • the die assembly may be a stack of memory die and the supporting die may include processor functionality, such as an analog or digital signal processing, for example.
  • the supporting die may be a base band controller IC, for example, and the die assembly may include a stack of memory die.
  • the die assembly may be a stack of memory die and the additional package may include one or more die having any of a variety of functionalities, including one or more signal processing functionalities, for example.
  • the additional support may be a die mounted die-up, that is, with the active side facing away from the first support, and electrically connected to the first support by wire bonds connecting rows or arrays of die pads along one or more die margins to corresponding bond sites on the first support.
  • one or more edges of the supporting die has no die pads, and the supporting die is situated such the pad-free edge of the supporting die is parallel to and adjacent to (or partly overlying) a row of first bond sites in the first support.
  • the die unit or assembly is then mounted over the upward-facing surface of the supporting die and situated such that the interconnect edge of the die assembly is situated near (and may be set back slightly from) the pad-free edge of the supporting die.
  • the die-to-die electrical interconnects are extended to connect the electrical interconnects to corresponding first bonds sites in the first support, generally as described above.
  • the second support may be a leadframe package or LGA package, oriented with exposed package leads or lands facing away from the first support, and the package may be mounted is a suitable position on the first substrate and electrically connected to the first support by, for example wire bonds connecting leads or lands on the supporting package to bond sites in the first support.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

L’invention concerne des ensembles de dés empilés qui sont connectés électriquement à des sites de raccordement sur un support quelconque, sans raccordement électrique à un substrat interposé ou à une grille de connexion et sans soudure.
PCT/US2009/036921 2008-03-12 2009-03-12 Ensemble de dés interconnectés électriquement montés sur un support WO2009114670A2 (fr)

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CN200980112952XA CN101999167B (zh) 2008-03-12 2009-03-12 支撑安装的电互连管芯组件

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JP (1) JP5763924B2 (fr)
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US9252116B2 (en) 2007-09-10 2016-02-02 Invensas Corporation Semiconductor die mount by conformal die coating
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US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
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US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
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US20160218088A1 (en) 2016-07-28
CN101999167B (zh) 2013-07-17
CN101999167A (zh) 2011-03-30
KR101554761B1 (ko) 2015-09-21
US20130099392A1 (en) 2013-04-25
US9305862B2 (en) 2016-04-05
KR20100123858A (ko) 2010-11-25
US8178978B2 (en) 2012-05-15
JP2011514012A (ja) 2011-04-28
CN103325764A (zh) 2013-09-25
CN103325764B (zh) 2016-09-07
TWI515863B (zh) 2016-01-01
WO2009114670A3 (fr) 2009-11-26
US20090230528A1 (en) 2009-09-17
JP5763924B2 (ja) 2015-08-12
TW201005916A (en) 2010-02-01

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