TWI502712B - 具有與先鑽孔或中間鑽孔之結構連接之後接點的微電子元件 - Google Patents

具有與先鑽孔或中間鑽孔之結構連接之後接點的微電子元件 Download PDF

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TWI502712B
TWI502712B TW099140226A TW99140226A TWI502712B TW I502712 B TWI502712 B TW I502712B TW 099140226 A TW099140226 A TW 099140226A TW 99140226 A TW99140226 A TW 99140226A TW I502712 B TWI502712 B TW I502712B
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Taiwan
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opening
region
conductive
microelectronic
front surface
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TW099140226A
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TW201205758A (en
Inventor
Vage Oganesian
Belgacem Haba
Ilyas Mohammed
Craig Mitchell
Piyush Savalia
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Tessera Inc
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Description

具有與先鑽孔或中間鑽孔之結構連接之後接點的微電子元件
本發明係關於微電子裝置之封裝，尤其半導體裝置之封裝。
微電子裝置通常包含諸如矽或砷化鎵之半導體材料之薄板，通常稱為晶粒或半導體晶片。半導體晶片通常以個別預先封裝之單元形式提供。在一些單元設計中，將半導體晶片安裝至基板或晶片載體上，又將基板或晶片載體安裝於諸如印刷電路板之電路板上。
在半導體晶片之第一面(例如前表面)中製造主動電路。為有助於電連接至主動電路，在晶片之同一面裝備有結合襯墊。結合襯墊通常圍繞晶粒之邊緣或對於許多儲存裝置在晶粒中心中以規則陣列置放。結合襯墊通常由導電金屬(諸如銅或鋁)以約0.5微米(μm)之厚度製成。結合襯墊可包括單層或多層金屬。結合襯墊之尺寸將隨裝置類型而變，但通常量測一側上的幾十至幾百微米。
穿矽通孔(TSV)可用以在上面安置結合襯墊之半導體晶片前表面與前表面相對之半導體晶片後表面之間提供電連接。習知TSV孔洞可能減少欲用以容納主動電路之第一面的一部分。可用於主動電路之第一面上可用空間之該減少可能增加產生各半導體晶片所需之矽量，藉此可能增加各晶片之成本。
在晶片之任何物理排列中尺寸為重要考慮因素。隨著攜帶型電子裝置之快速進展對晶片之更緊密物理排列之需要更加強烈。僅舉例而言，通常稱為「智慧型手機(smart phone)」之裝置整合具有強力資料處理器之蜂巢式電話、記憶體及輔助裝置(諸如全球定位系統接收器)、電子照相機及區域網路連接以及高解析度顯示器及相關影像處理晶片之功能。該等裝置可提供諸如全網際網路連接性、包括全解析度視訊、導航、電子銀行及更多之娛樂之能力，所有能力均處於袖珍裝置中。複雜攜帶型裝置需要封裝許多晶片至小空間中。此外，一些晶片具有許多輸入及輸出連接，通常稱為「I/O」。此等I/O必須與其他晶片之I/O相互連接。互連應短且應具有低阻抗以使得信號傳播延遲減至最小。形成互連之組件不應大大增加總成之尺寸。類似需要出現於其他應用中，例如資料伺服器，諸如用於網際網路搜索引擎中之彼等資料伺服器。舉例而言，在複雜晶片之間提供許多短、低阻抗互連之結構可增加搜索引擎之帶寬且降低其功率消耗。
儘管半導體通孔形成及互連已取得進展，但可進行其他改良以增加在前晶片表面與後晶片表面之間產生連接之方法，且對可由該等方法產生之結構進行改良。
微電子單元包括具有單晶形式之半導體區域的微電子元件，例如積體電路晶片。半導體區域具有在第一方向上延伸之前表面、鄰近前表面之主動電路元件、遠離前表面之後表面及向後表面延伸之導電通孔。導電通孔可藉由無機介電層與半導體區域絕緣。開口可自後表面部分通過半導體區域之厚度延伸，其中開口及導電通孔在第一方向上具有各別寬度。在開口匯合導電通孔的地方，開口寬度可大於導電通孔之寬度。後接點可電連接至導電通孔且在後表面暴露，以與諸如另一類似微電子單元、微電子封裝或電路板之外部電路元件電連接。
在一實施例中，可在開口內提供聚合物電介質，且導電互連與後接點及導電通孔電連接且在至少開口內延伸，聚合物電介質使導電互連與半導體區域分離。在一特定實施例中，導電互連與開口之外形相符。
在一實施例中，導電互連在導電通孔與後接點之間的第一方向上延伸，該第一方向至少實質上垂直，其中垂直方向為微電子元件前表面與後表面之間的厚度方向。在一實施例中，聚合物電介質可包括在第一方向上延伸之孔。開口鄰近於孔之表面可在朝向前表面的第二方向上延伸，且第二方向可相對於第一方向呈銳角延伸。
在一特定實施例中，導電通孔包括金屬，其可為例如鎢、銅、鎳、鈦或鋁中之一或多者。在一實施例中，導電通孔之至少一部分包括多晶半導體。在一特定實施例中，導電通孔之寬度不大於10微米。
可在微電子元件前表面暴露前接點以使微電子元件與外部電路元件電互連。前表面可在第一方向橫向之第二方向上延伸，且導電通孔可與前接點電連接。在一實施例中，導電通孔之至少一個邊緣可經安置在第一或第二方向中之至少一個方向上超過前接點之邊緣。
微電子元件中之開口可包括自後表面延伸之第一開口，第一開口在第一方向上具有第一寬度；自第一開口向前表面延伸之第二開口。在第一開口及第二開口匯合的地方，第二開口可具有小於第一寬度之第二寬度。導電通孔可在第二開口內暴露，且後接點可通過第一開口及第二開口與導電通孔電連接。
在一實施例中，第二寬度可能大於導電通孔之寬度。第二開口可在朝向前表面之方向上逐漸變細至變得較小。第一開口可在朝向第二開口之方向上逐漸變細至變得較小。
在一實施例中，複數個導電通孔可在開口內暴露，且複數個後接點通過開口與導電通孔電連接。
微電子元件可包括複數個與導電通孔電連接且沿開口之至少一個表面向後接點延伸之導電跡線。
在一實施例中，複數個後接點可覆蓋半導體區域中之開口，且微電子元件可另外包括複數個自導電通孔延伸至後接點之導電互連。
在一特定實施例中，垂直方向可為微電子元件前表面與後表面之間的厚度方向，且導電互連可在導電通孔與後接點之間的垂直方向上延伸。
在一特定實施例中，一或多個其他電子組件可電連接至如一或多個上述實施例所述之微電子單元。
系統可另外包括外殼，其中結構及其他電子組件可安裝至外殼。
根據本發明一實施例提供製造微電子單元之方法。在該實施例中，微電子元件可包括單晶形式且具有前表面及遠離前表面之後表面之半導體區域。可鄰近前表面安置主動電路元件，包括犧牲材料之區域可向後表面延伸。加工可包括藉由通過自後表面延伸且暴露區域之開口所施加之加工移除犧牲材料之至少一部分。犧牲材料可包括例如多晶半導體或鎢。
加工可包括形成至少部分置換所移除之犧牲材料的導電區域。在一實施例中，加工可包括形成電連接至導電區域且在後表面暴露以與電路元件電連接之後接點。
在一實施例中，形成開口之步驟可另外包括形成自後表面向前表面延伸之第一開口。可在第一開口內形成第一層。接著，可通過第一層中之開口移除半導體區域之材料，形成自第一開口向前表面延伸之第二開口。
在一實施例中，形成第一層之步驟可包括藉由將聚合物電化學沈積於至少第一開口之內表面上形成裝襯第一開口之介電層。
在一實例中，可使用光微影界定第一層中開口之程度及位置。在特定情況下，可使用雷射界定第一層中開口之程度及位置。
該方法可另外包括移除第一層，接著在第一開口及第二開口之內表面上形成介電層。接著，可形成包括後接點之導電結構，該導電結構係藉由介電層與半導體區域絕緣。
在一特定實施例中，移除步驟藉由通過第一開口及第二開口施加之加工移除犧牲材料之至少一部分。微電子元件可另外包括分離犧牲材料區域與半導體區域之介電區域。犧牲材料可包括多晶半導體。移除步驟可移除多晶半導體之至少一部分，且形成導電接點之步驟可包括至少在開口內形成遠離導電通孔延伸之導電互連。後接點可與導電互連電連接。
在一特定實施例中，介電區域可包括無機介電材料，且形成介電層之步驟可包括將聚合材料沈積於開口之至少一個內表面上。移除步驟可相對於介電區域選擇性地移除多晶半導體材料。
在一特定實施例中，聚合材料可電化學沈積。
在一特定實施例中，形成後接點之步驟包括在第二開口之至少一個內表面上形成介電層，接著用導電材料填充至少第二開口。
在一實例中，形成後接點之步驟可包括在第二開口內形成第二介電層，接著將金屬層沈積於第二介電層之表面上，金屬層與至少第二開口之外形相符。
根據本發明一實施例，提供製造微電子元件之方法。微電子元件可包括單晶形式且具有在第一方向上延伸之前表面、鄰近前表面之主動電路元件、在前表面暴露之前導電接點及遠離前表面之後表面的半導體區域。包括金屬之導電通孔可向後表面延伸。在一實例中，導電通孔之邊緣可在前表面一方向上偏移超過前導電接點之邊緣。
該方法可包括在半導體區域中形成自後表面延伸且暴露導電通孔之開口。可形成電連接至導電通孔且在後表面暴露以與電路元件電連接之後接點。
在一實施例中，形成開口之步驟可包括形成自後表面向前表面延伸之第一開口。可用第一層裝襯開口，接著可通過第一層中之開口移除半導體區域之材料。以此方式，可形成自第一開口向前表面延伸之第二開口。
在一實例中，可在形成後接點之前將聚合材料沈積於開口之至少一個內表面上，形成介電層。在一特定實例中，聚合材料可電化學沈積。
在一實施例中，形成第一層之步驟可包括藉由將聚合物電化學沈積於至少第一開口之內表面上形成裝襯第一開口之介電層。
在一實例中，可使用光微影界定第一層中開口之程度及位置。或者，可使用雷射界定第一層中開口之程度及位置。
一實施例提供移除第一層。接著，可在第一開口及第二開口之內表面上形成介電層。接著，可形成包括後接點之導電結構，該導電結構係藉由介電層與半導體區域絕緣。
在一特定實施例中，形成後接點之步驟可包括在第二開口之至少一個內表面上形成介電層。接著可用導電材料填充第二開口以及可能存在之第一開口。
在一實施例中，形成後接點之步驟可包括在第二開口內形成第二介電層。金屬層可沈積於第二介電層之表面上。在一特定實施例中，金屬層可與至少第二開口之外形相符，或者可填充第二開口或以柱或不與開口之外形相符之另一結構形式提供。
本發明之其他態樣所提供之系統併入有根據本發明之上述態樣之微電子結構、根據本發明之上述態樣之複合晶片或兩者結合其他電子裝置。舉例而言，可將系統安置於可為攜帶型外殼之單一外殼中。根據本發明之此態樣中之較佳實施例之系統與類似習知系統相比可能更緊密。
單晶半導體基板，例如完整晶圓100或一部分晶圓示於圖1中。晶圓或晶圓部分100展示具有複數個個別區域102，該等區域102在各區域102之圍緣104彼此附接。經由另外所述之加工，區域102可成為個別微電子元件，例如積體電路晶片。除非另有規定，否則在包括複數個以此方式彼此附接之區域的晶圓或晶圓部分上執行如下所述之加工，下文中將任一區域稱為「晶圓」。最初，晶圓100之厚度106為幾百微米。晶圓基本上可由矽或例如III-V半導體化合物(諸如砷化鎵(GaAs)及其類似物)或II-VI半導體化合物之化合物半導體材料組成。
現參考圖2及以下描述「先鑽孔(via first)」流。如圖2所示，在晶圓中由作為主要表面之晶圓前表面112形成溝槽108、110，溝槽向晶圓之遠離前表面之後表面114延伸。後表面通常為在晶圓厚度106之方向上與前表面分離之晶圓的主要表面。一些溝槽108相對較淺；例如通常延伸至距前表面112為70至500奈米之深度。其他溝槽110通常延伸至約300奈米至幾微米或幾十微米範圍內之深度。一般而言，與溝槽108相比溝槽110延伸至較大深度，以致當溝槽108延伸至400奈米之深度時，例如溝槽110延伸至大於400奈米之深度。
如圖2中另外所示，晶圓可經加工在溝槽108中形成隔離區118且在溝槽110中形成介電層122。隔離區118通常可由用諸如氧化物(例如二氧化矽)之無機介電材料填充溝槽108形成。介電層122可藉由沈積諸如氧化物之無機介電層於溝槽110中來提供。在一特定實例中，無機介電層可包括氧化矽、氮化矽、氮氧化矽或其一或多種之組合。
圖3說明在溝槽110內形成多晶半導體材料120之區域的進一步加工。在一實例中，多晶半導體材料為多晶矽(polycrystalline silicon)，下文中為「多晶矽(polysilicon)」或「多晶矽(poly)」。在一特定實例中，其中多晶矽僅用作犧牲層，多晶矽可提供為固有或輕微摻雜之半導體材料。在另一實例中，尤其在多晶矽形成最終導電結構之一部分的情況下，將多晶矽用諸如磷或砷及其他物質之n型摻雜劑或諸如硼之p型摻雜劑重摻雜(例如以5×1018 cm-3 至5×1021 cm-3 之摻雜劑濃度)。可將多晶矽沈積於介電層122上。沈積介電材料及多晶矽之後，可移除溝槽外部覆蓋前表面112之過量多晶矽及介電材料。舉例而言，可使用化學機械拋光(「CMP」)移除前表面112上之該等層，同時亦使至少經填充溝槽118之表面與前表面112成平面。或者，替代形成多晶矽區域120，區域可包括諸如鎢或鈦之金屬，該金屬能夠耐受用以形成晶圓之主動電路元件之後續加工。
如圖4所示，執行進一步加工以在晶圓100之單晶半導體區域中形成主動電路元件124，例如半導體裝置，諸如電晶體、二極體、其他裝置或其組合。主動電路元件可藉由隔離區118及主動電路元件124之半導體區域相對於鄰近其之晶圓100之部分的摻雜劑類型差異彼此電隔離。主動電路元件通常藉由裝襯溝槽110之介電層122而與晶圓之高摻雜多晶矽區域120分離。通常在形成隔離區118及多晶矽區域120之後或與此同時加工形成主動電路元件。鑒於此，多晶矽區域120需要耐受用於形成主動電路元件中，諸如用於將摻雜劑驅動至主動電路元件之各半導體區域之通常高於600℃且可能高達1400℃之高加工溫度。
在形成主動電路元件之後，在單晶晶圓100之前表面112頂上形成介電層132。形成延伸通過介電層且分別電接觸多晶矽區域120及主動電路元件124之接觸通孔126、128。接觸通孔可包括多晶半導體材料、金屬、金屬合金(例如矽化物)、導電金屬化合物或其組合。在一特定實施例中，接觸通孔126、128可包括耐火金屬，例如鎢、鈦或其組合。此等金屬可藉由物理氣相沈積(「PVD」)、濺鍍或化學氣相沈積(「CVD」)來沈積。如同多晶矽，鎢及鈦亦耐受後續高溫加工。
圖4另外說明使主動電路元件與多晶矽區域120電連接之金屬線130。為進行說明，展示金屬線130使接觸通孔126與接觸通孔128連接。然而，金屬線不需要直接連接接觸通孔126、128。舉例而言，使多晶矽區域120與主動電路元件124連接之金屬線可提供於安置於高於形成接觸通孔126、128之介電層132且距離主要表面112更遠之介電層(未圖示)中之較高位準金屬層中。
另一介電層134覆蓋介電層132及一或多個安置於介電層132、134之間的介電層(未圖示)，該介電層134中可提供具有金屬線路136及通孔137之其他層。此等金屬線路136及通孔137可通過線路130及通孔126電連接一或多個多晶矽區域120與相應前接點138。在上述加工之後，導電接點138(例如金屬墊、柱或柱與墊之組合)可在晶圓140之暴露前表面141處暴露。接點138可例如藉由通孔與金屬線之組合(未圖示)與一些或所有多晶矽區域電連接，該通孔及金屬線之組合可在較高位準介電層(未圖示)及介電層134內自金屬線130延伸至接點138。導電接點138具有在晶圓之橫向142延伸之橫向尺寸144，該橫向尺寸144大於多晶矽區域同一方向142之相應橫向尺寸146。如圖4所示，導電接點138不需要與多晶矽區域120對準。此外，多晶矽區域120之圍緣148可經安置超過最接近之接點圍緣139。甚至可能晶圓之特定接點138不覆蓋及甚至部分不覆蓋晶圓之任何多晶矽區域120之主要表面149。
圖5說明後續加工階段，其中如下另外所述在進一步加工形成後導電接點之前可減小晶圓140之厚度。在一實例中，可藉由自後表面114研磨或磨平減小晶圓140之厚度。在一實施例中，研磨或磨平之後晶圓140之最終厚度減至幾十微米至100-200微米。在一特定實施例中，最終厚度可小於10微米。視情況在研磨或磨平期間，可將晶圓140之經暴露前表面150(亦即暴露接點138之表面)夾持至夾盤(未圖示)或諸如經由黏著劑固定於載體基板152上以支撐晶圓140。
接著，如圖6所示，可形成自晶圓140之後表面114向前表面150延伸之開口154。開口154可由若干方法中之任一者或組合形成。開口可由移除單晶半導體材料之後表面與多晶矽區域120之間的至少一部分以及裝襯多晶矽區域之介電層122之一部分形成。在特定實例中，開口154可由雷射切除、機械研磨、蝕刻或引導研磨顆粒流朝向晶圓之後表面114形成。在一實施例中，開口154可由一或多種技術形成，該或該等技術為此在與此同時申請之共同擁有同在申請中之名為：「METHODS OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM」的美國申請案第12/842,612號中所述，其揭示內容以引用方式併入本文中。
通常，晶圓140之橫向142之開口寬度156大於同一橫向之多晶矽區域120之寬度158。寬度156通常為與延伸前表面150及後表面114之平面平行的第一及第二方向之開口154之小尺寸。
圖7提供圖6中所示總成之替代視圖，其中已將特徵放大至與圖6相比較小之程度，以便看見大量多晶矽區域120、主動電路元件124及暴露至少一些多晶矽區域120之由後表面得到之開口154。亦如圖7中所示，一部分介電層122使多晶矽區域與形成主動電路元件124之相鄰區域分離。
此後，如圖8所示，可在後表面114上及在開口154內形成介電層160。介電層160可包括可具有無機或聚合組成之多種類型之介電材料中之任一者。在一特定實施例中，介電層160包括聚合材料。可使用各種方法形成介電層160。在一實例中，將可流動介電材料施加於晶圓100之後表面114，接著在「旋塗」操作期間將可流動材料更均勻分佈於晶圓之後表面上，隨後進行可包括加熱之乾燥循環。在另一實例中，可將介電材料之熱塑薄膜施加於晶圓100之後表面114，此後加熱包括晶圓及蓋板元件之總成，從而導致薄膜向下流至開口154。在另一實例中，可使用氣相沈積形成介電層。
在另一實例中，可將晶圓100浸漬於介電沈積浴中，形成保形介電塗層或層160。可使用諸如電泳沈積或電解沈積之電化學沈積形成保形介電塗層，以致使保形介電塗層僅沈積於總成之經暴露導電及半導電表面上。在沈積期間，使半導體裝置晶圓保持在所需電位且將電極浸漬於浴中以使浴保持在不同所需電位。接著在適當條件下使總成保持於浴中歷時足以在導電或半導電之裝置晶圓之暴露表面上，包括(但不限於)沿背面114及開口154之壁155、及犧牲材料區域之表面(例如多晶矽或鎢等)上形成電化學沈積保形介電塗層160之時間。只要在欲藉此塗佈之表面與浴之間維持足夠強之電場即可出現電泳沈積。甚至在強電場已不再存在之後仍可持續電解沈積。電泳沈積塗層本身之限制在於在其達到由例如其沈積之電壓、濃度等參數控制之一定厚度之後，沈積終止。電泳沈積在總成之導電及/或半導電外表面上形成連續且均勻厚度之保形塗層。另外，電泳沈積塗層由於其介電(不導電)特性通常不在可能存在之現有介電層上形成。換言之，電泳沈積之特性為不會形成於覆蓋導體之介電材料層上，其限制條件為介電材料層具有產生介電特性之足夠厚度。電泳沈積通常不會出現在厚度大於約10微米至幾十微米之介電層上。
在一實施例中，保形介電層160可由陰極環氧化物沈積前驅體形成。或者，可使用聚胺基甲酸酯或丙烯酸系沈積前驅體。多種電泳塗佈前驅體組合物及供應源列於以下表1中。
此後，如圖9所示，在聚合層160中形成開口164，在各開口內暴露多晶矽區域。在一實施例中，可使用光微影界定聚合層160中開口164之程度及位置。在另一實施例中，可使用雷射界定開口164之程度及位置。現可移除各多晶矽區域120內之多晶矽(圖8)，諸如藉由相對於晶圓140之其他材料，亦即介電層(例如無機介電層，諸如圍繞各多晶矽區域之氧化層122)選擇性地蝕刻其中之多晶矽。亦可相對於其他介電材料，諸如層162，例如安置於單晶半導體區域100之前主要表面112與晶圓之暴露前表面150之間的氧化物或其他材料選擇性地執行多晶矽蝕刻。當區域120中之材料為除多晶半導體外之材料(諸如鎢)時，例如可藉由實施蝕刻或其他加工通過介電層中之開口164來移除鎢。
此後，如圖10中所示，在一實施例中，可在開口及多晶矽區域先前佔據之位置中形成金屬166層。在一實例中，可諸如藉由電鍍加工將金屬沈積於開口中及晶圓140之後表面114上，此後可移除覆蓋後表面114之過量金屬。諸如銅、鎳、鋁或其組合之金屬可說明性地包括於金屬層中。一或多個其他金屬、金屬合金或導電金屬化合物層可提供為催化劑材料種子層以與介電層黏附或提供為障壁金屬層諸如用於避免金屬層與鄰近介電層之間的離子移動。在一些情況下，鎢、鈦或兩者可擔當此等其他金屬層中之一些的任務。介電層122在自其中移除多晶矽之後仍在原位之情況下，可將置換多晶矽區域中所移除之材料的金屬稱為「導電通孔」220。晶圓後表面114之平面方向142之各導電通孔的寬度167說明性地小於10微米。
接著可使用後續電鍍加工形成如圖11所示在晶圓之後表面114處暴露的後接點168，例如導電墊。或者，當在開口內形成金屬層166之過程中在後表面上形成金屬層時，可將彼金屬層圖案化或擴大以形成後接點168。可將在至少開口154內遠離導電通孔220延伸且連接至接點168之金屬層166之一部分視為「導電互連」。如圖11A中特定所示，各開口154可在其中含有單一金屬層166，其與在後表面114暴露的後接點168電連接。然而，如下關於圖19、圖20及圖21所述，可能存在其他配置。
亦如圖12所示，可諸如藉由於前接點138(例如晶圓之導電金屬墊)上電鍍金屬視情況形成與前接點138接觸之再分佈層(RDL)170。可視情況形成RDL以形成與後接點168實質上垂直對準(亦即呈垂直方向172)之結合襯墊延伸、跡線或其他導電墊。在此情況下，可由使一晶圓140A之前導電接點138與另一晶圓140B之後接點168電連接形成多晶圓總成180。在一實例中，接點138、168可經由RDL 170與至少RDL與後接點168之間的黏結層174連接，黏結層174包括接合金屬，例如錫、焊料、導電膏、各向異性導電黏著劑或其他導電連接材料。或者，在其他實例中，接點138、168可經由諸如熱壓接合、擴散接合或其他技術之另一連接技術電連接在一起。
圖14說明另一階段，其中可將多晶圓總成180(圖13)沿微電子元件(例如積體電路晶片)之切割路線切斷以在其中形成堆疊微電子單元182，該堆疊微電子單元182含有作為各晶圓140A、140B(圖13)之切斷部分的單元184A、184B。現可經由暴露之前接點138或RDL層170及接合金屬188將微電子單元182電連接至電路板186或其他電路元件。或者，可以類似方式經由單元184A之後接點168及其間之接合金屬將微電子單元182連接至電路板。
如圖15所示，在如上關於圖8及圖9所述之方法的變化形式中，將諸如光阻層或其他材料之材料之犧牲層190施加於開口154內及後表面114上。接著在犧牲層190中形成開口，其暴露多晶矽區域。接著可諸如藉由以相對於其他材料(例如暴露於蝕刻劑之犧牲層190及介電層122)具有選擇性之方式蝕刻多晶矽完全移除一部分多晶矽區域或多晶矽材料通過犧牲層190中之開口。
此後，如圖16中所示，可自半導體區域100之開口154及後表面114移除犧牲層190，此後可形成介電層192(圖17)以覆蓋半導體區域100之暴露表面。接著重新開始加工，形成如上關於圖10所述之金屬層166。
圖18說明上述實施例(圖6-圖11)之變化形式，其中自後表面延伸之開口為梯形開口，其中第一開口204自後表面114向前表面延伸，接著第二開口206自第一開口內向前表面延伸以便暴露犧牲區域220。在一實施例中，開口之某些態樣及伴隨開口之介電或導電結構之態樣可如2008年2月26日申請之美國申請案第12/072,508號及2010年5月21日申請之美國申請案第12/784,841號中所述，此等申請案之揭示內容以引用的方式併入本文中。在一實施例中，諸如後表面114的第一開口之最大寬度258大於第二開口之最大寬度260。另外，最大寬度260可能大於在用如上關於圖10所示且所述之金屬替換區域220中移除之多晶矽材料之後得到之導電通孔之最大寬度262。如圖18所示，可使第一開口204朝向前表面之方向逐漸變細至變得較小，其亦為朝向第二開口206之方向。亦可使第二開口206朝向前表面之方向逐漸變細至變得較小。如圖18中另外所示，裝襯第一開口之介電層264可為與裝襯第二開口之介電層266相同之層或不同之層。焊劑遮罩270說明性地可覆蓋後表面114之一部分，使後接點168在焊劑遮罩之開口272內暴露。
圖19說明上述實施例(圖6-圖11)之另一變化形式，其中導電互連274沿介電層264延伸且延伸至後表面114上，在後表面中其與後接點268電連接。在一實施例中，可由導電互連274整體形成後接點268例如作為同一金屬層之一部分或一組金屬層，其係同時形成於介電層264在開口254內及後表面114上之暴露表面276、278上。如圖19中所示，導電互連沿開口之第一壁254A而非沿其第二壁254B延伸。在一實施例中，導電互連可與上面放置其之開口254之壁254A的外形(contour)相符。在一實施例中，導電互連274可為在第一開口內延伸之唯一導電元件，且可例如通過第二開口256自暴露於其之單一導電通孔延伸。
或者，如圖20所示，導電互連274及其他導電互連274可提供為複數個覆蓋相對大開口254之內表面之導電跡線，許多導電通孔220直接暴露或通過通孔與第一開口之間的相應第二開口暴露。另外，晶圓之微電子元件102在其中可具有一個以上第一開口。舉例而言，複數個導電互連374(圖20)可沿另一第一開口354之一或多個內表面延伸，該另一第一開口354自後表面向前表面延伸，導電互連374與覆蓋後表面之後接點368電連接。如圖20中所示，導電互連274可以朝導電通孔與後接點之間的開口之傾斜壁之上的方向延伸。或者，一或多個導電互連，諸如互連274A、274B可以部分朝傾斜壁之上的方向且部分沿傾斜壁之方向延伸。在一特定實施例中，導電互連可以諸如如與此同時申請之共同擁有之名為「NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS」的美國申請案第12/842,669號中所述形成導電元件，例如跡線之方式形成，其揭示內容以引用的方式併入本文中。在另一變化形式中，可提供單一開口454(圖21)，導電互連474自其在多個方向上延伸。在一實例中，積體電路晶片可為具有複數個導電通孔420之動態隨機存取記憶體(「DRAM」)晶片，導電互連474可直接或例如通過第二開口間接連接至該複數個導電通孔。如圖21所示，一些導電互連474可在第一方向430上自導電通孔420延伸，而其他導電互連474在第二方向432上自導電通孔420延伸。
圖22說明特定變化形式，其中後接點568提供為覆蓋填充開口554之介電材料區域590的導電墊。在此情況下，後接點568可經由金屬柱與導電通孔連接，該金屬柱延伸通過孔592(延伸通過介電區域590)。在一例示性實施例中，在第二開口內形成介電層558、導電通孔520及金屬層556之後，由聚合材料藉由填充第一開口形成介電區域590。接著，可諸如藉由雷射切除、機械研磨或其他技術在介電區域中形成孔。接著可在孔中形成金屬層以形成柱566。
在一特定實施例中，孔可具有在垂直方向510，亦即相對於單晶半導體區域100之前表面112之法線方向上延伸之壁570。在此情況下，在其中形成之柱566在垂直方向510上在導電通孔520與上面提供導電接點568之表面593之間延伸。該壁570以不同於開口554之壁552的方向且以相對於開口554之壁552為銳角512延伸。在另一實施例中，孔之壁570可能不會在垂直方向上延伸，然而相對於開口554之壁552的延伸方向呈銳角512延伸。
在一實施例中，柱566可為具有中心開口之中空管樣結構；在另一實施例中，柱可為實體，亦即在其中不具有開口。在形成柱之後，導電墊可在柱頂上形成為後接點。在另一實施例中，可省略導電墊。在此情況下，柱之暴露端可延伸至高於介電區域之表面593、與表面593共面或略低於表面593凹進。
圖23說明圖19中所示實施例之變化形式，其中在形成金屬層之前不移除多晶矽區域620。相反，當形成與多晶矽區域620接觸之金屬層668時，使多晶矽區域620保留在原位，金屬層668形成沿介電層664之壁延伸且與後接點670電連接之導電互連之至少一部分。如上實施例(圖19)中，覆蓋後表面上之介電層或在第一開口內之導電互連之一部分672可與後接點670整體形成。在與以上(圖20-圖21)所示且所述之彼等實施例類似之特定實施例中，複數個導電互連可沿開口之一或多個內表面自與各別多晶矽區域620連接之複數個金屬層668延伸。
在一特定實施例中，在形成導電互連之後，可用介電材料680填充開口654。以此方式，介電材料680可有助於增強結構之機械強度，且亦可在開口654內之各別導電互連之間提供絕緣。
如圖24所示，在實施例(圖22)之變化形式中，在自區域720移除多晶矽之後，一部分多晶矽仍可保留其中。在一種情況下，保留之多晶矽可填充區域720鄰近於單晶半導體區域100之前表面112的一部分。接著，其上形成之金屬層768接觸最初形成之介電層770之壁內所含之體積內的多晶矽。以此方式，提供自前表面112延伸通過原始通孔之保留多晶矽部分720且通過圍繞原始多晶矽部分之壁內所含之金屬部分724的導電結構。
圖25說明上文關於圖19所示且所述之實施例的另一變化形式，其中第二開口856內之金屬層868與半導體區域100中第二開口之表面870之外形相符。如特定所示，金屬層868可至少實質上覆蓋且可完全覆蓋第二開口856內之介電層872之內表面。
參考圖26-圖27，現描述實施「中間鑽孔(via middle)」製造方法所需之其他變化形式。中間鑽孔製造方法與上述先鑽孔製造方法之不同之處在於在形成導電通孔920(圖27)之前執行用於形成主動電路元件924(圖26)之高溫加工。如在上述實施例中，通孔920延伸至的深度D1低於主動電路元件924延伸至的深度D2。通常在用於形成主動電路元件924之至少高溫加工完成之後形成此實施例之導電通孔920。然而，可在形成連接介電區域934內之晶圓之一或多個金屬化層(metallization level)內之線路的晶圓之佈線元件(例如金屬線路936及通孔937)之前且在形成在晶圓940之外表面942暴露之導電接點938(例如導電墊)之前形成導電通孔920。因為通孔920不需要耐受高溫加工，所以其可由最終金屬形成。在一實例中，通孔920可包括諸如鎳、銅或鋁之金屬。在一特定實施例中，通孔920可由電鍍形成。在另一實例中，通孔可包括鎢或鈦，且可由例如PVD或CVD方法或其組合形成。
如圖27所示，導電通孔自單晶半導體區域100之前主要表面912上的介電層932之主要表面931之高度H1延伸，該等通孔延伸至的深度D1通常低於主動電路元件924延伸至的深度D2。
在晶圓940具有預先存在之中間鑽孔結構(圖27)之情況下，現可如上關於圖5、圖6及圖7及圖8所述執行加工。關於圖9，現可在介電層160中形成孔洞164。然而，因為中間鑽孔方法中之導電通孔920由金屬替代具有較大電阻之犧牲材料(諸如多晶矽)形成，所以不需要移除通孔920內之金屬。因此，省略自多晶矽區域移除多晶矽之步驟，且作為替代接著將該結構金屬化形成如上文關於圖10-圖11所示且所述之連接至導電通孔之導電互連及後接點。亦可進行進一步加工以形成如上關於圖12所述之前RDL。亦可根據如上關於圖13-圖14、關於圖15-圖17、圖18、圖19-圖20、圖19、圖21、圖22或圖25所述之特定變化形式執行加工。在特定情況下，中間鑽孔起始結構之導電通孔920內之金屬可為銅、鎳或鋁或其組合。
在特定實施例中，以引用的方式併入本文中且與此同時申請之以下專利申請案揭示與本文揭示內容有關且可適用於以下所述結構及方法的其他詳情、方法及結構：通孔及通孔導體可由諸如與此同時待審之同在申請中共同讓渡之名為「MICROELECTRONIC ELEMENTS HAVING METALLIC PADS OVELYING VIAS」、「METHOD OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM」、「NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS」、「ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN」及「MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION」之美國專利申請案及公開之美國專利申請公開案第20080246136號中更詳細揭示之彼等方法之方法形成，其揭示內容以引用的方式併入本文中。
上文討論之結構提供卓越的三維互連能力。此等能力可用於任何類型之晶片。僅舉例而言，可將以下晶片之組合包括於如以上所討論之結構中：(i)處理器及用於處理器之記憶體；(ii)複數個相同類型之記憶體晶片；(iii)複數個不同類型之記憶體晶片，諸如DRAM及SRAM；(iv)影像感測器及用以處理來自感測器之影像的影像處理器；(v)特殊應用積體電路(「ASIC」)及記憶體。可在構造不同電子系統時利用以上所討論之結構。舉例而言，根據本發明之另一實施例之系統900包括如上所述之結構906結合其他電子組件908及910。在所述實例中，組件908為半導體晶片，而組件910為顯示屏，但可使用任何其他組件。當然，儘管為清晰說明起見僅描述圖28中的另兩個組件，但該系統可包括許多該等組件。如上所述之結構906可為例如如上結合圖14或圖18-圖27中之任一者所討論之微電子單元184A或堆疊微電子總成182、或如參考圖14所討論之併入有複數個晶片之結構184A。在另一變化形式中，可提供兩者，且可使用許多該等結構。將結構906及組件908及910安裝於以虛線示意性描繪之常見外殼901中，且必要時彼此相互電連接以形成所需電路。在所示之例示性系統中，系統包括電路板902，諸如可撓性印刷電路板，且該電路板包括使組件彼此互連之許多導體904，圖28僅描述其中一個。然而，此僅為例示性的；可使用產生電連接之任何合適結構。將外殼901描述成為例如蜂巢式電話或個人數位助理中可用之攜帶型外殼，且屏幕910在外殼之表面處暴露。在結構906包括諸如成像晶片之感光元件之情況下，亦可提供透鏡911或其他光學裝置以發送光至結構。此外，圖28中所示之簡化系統僅為例示性的；可使用以上所討論之結構製造其他系統，包括通常視為固定結構之系統，諸如桌上計算機、路由器及其類似物。
因為可在不背離本發明之情況下利用以上所討論之特徵之此等及其他變化及組合，所以上述較佳實施例之描述應視為說明而非限制如申請專利範圍所界定之本發明。
100．．．晶圓/單晶半導體區域
102．．．區域/晶圓之微電子元件
104．．．圍緣
106．．．晶圓厚度
108．．．溝槽
110．．．溝槽
112．．．前表面
114．．．後表面
118．．．隔離區/經填充溝槽
120．．．多晶矽區域
122．．．介電層
124．．．主動電路元件
126．．．接觸通孔
128．．．接觸通孔
130．．．金屬線/線路
132．．．介電層
134．．．介電層
136．．．金屬線路
137．．．通孔
138．．．前導電接點
139．．．接點之圍緣
140．．．晶圓
140A．．．晶圓
140B．．．晶圓
141．．．暴露前表面
142．．．晶圓之橫向
144．．．橫向尺寸
146．．．橫向尺寸
148．．．多晶矽區域120之圍緣
149．．．主要表面
150．．．前表面
152．．．載體基板
154．．．開口
155．．．開口154之壁
156．．．開口寬度
158．．．多晶矽區域122之寬度
160．．．介電層/聚合層
162．．．層
164．．．開口/孔洞
166．．．金屬層
167．．．各導電通孔的寬度
168．．．後接點
170．．．再分佈層(RDL)
172．．．垂直方向
174．．．黏結層
180．．．多晶圓總成
182．．．堆疊微電子單元/堆疊微電子總成/微電子單元
184A．．．微電子單元
184B．．．微電子單元
186．．．電路板
188．．．接合金屬
190．．．犧牲層
192．．．介電層
204．．．第一開口
206．．．第二開口
220．．．導電通孔/犧牲區域
254．．．開口
254A．．．開口之第一壁
254B．．．開口之第二壁
256．．．第二開口
258．．．第一開口之最大寬度
260．．．第二開口之最大寬度
262．．．導電通孔之最大寬度
264．．．裝襯第一開口之介電層
266．．．裝襯第二開口之介電層
268．．．後接點
270．．．焊劑遮罩
272．．．焊劑遮罩之開口
274．．．導電互連
274A．．．互連
274B．．．互連
276．．．暴露表面
278．．．暴露表面
354．．．第一開口
368．．．後接點
374．．．導電互連
420．．．導電通孔
430．．．第一方向
432．．．第二方向
454．．．單一開口
474．．．導電互連
510．．．垂直方向
512．．．銳角
520．．．導電通孔
552．．．開口554之壁
554．．．開口
556．．．金屬層
558．．．介電層
566．．．柱
568．．．後接點/導電接點
570．．．壁
590．．．介電區域
592．．．孔/表面
620．．．多晶矽區域
654．．．開口
664．．．介電層
668．．．金屬層
670．．．後接點
672．．．導電互連之一部分
680．．．介電材料
720．．．區域/多晶矽部分
724．．．金屬部分
768．．．金屬層
770．．．介電層
856．．．第二開口
868．．．金屬層
870．．．第二開口之表面
872．．．介電層
900．．．系統
901．．．外殼
902．．．電路板
904．．．導體
906．．．結構
908．．．電子組件
910．．．電子組件/屏幕
911．．．透鏡
912．．．前主要表面
920．．．導電通孔
924．．．主動電路元件
931．．．主要表面
932．．．介電層
934．．．介電區域
936．．．金屬線路
937．．．通孔
938．．．導電接點
940．．．晶圓
942．．．外表面
D1．．．深度
D2．．．深度
H1．．．高度
圖1為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖2為說明根據本發明一實施例之微電子單元的製造方法中圖1之階段後之階段的剖視圖；
圖3為說明根據本發明一實施例之微電子單元的製造方法中之另一階段之剖視圖；
圖4為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖5為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖6為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖7為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖8為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖9為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖10為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖11為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖12為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖13為說明根據本發明一實施例之堆疊微電子總成的製造方法中之階段之剖視圖；
圖14為說明根據本發明一實施例之堆疊微電子總成之結構及互連之剖視圖；
圖15為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖16為說明根據本發明一實施例之微電子單元的製造方法中之階段之剖視圖；
圖17為說明根據本發明一實施例之堆疊微電子總成的製造方法中之階段之剖視圖；
圖18為說明根據本發明一實施例之微電子單元結構之剖視圖；
圖19為說明根據圖18中所示之本發明一實施例之變化形式的微電子單元結構之剖視圖；
圖20說明與根據本發明一實施例之微電子單元的圖19剖視圖對應之俯視平面圖；
圖21說明根據本發明一實施例之圖20所示微電子單元之變化形式的與圖19剖視圖對應之俯視平面圖；
圖22為說明根據圖18中所示之本發明一實施例之變化形式的微電子單元結構之剖視圖；
圖23為說明根據圖18中所示之本發明一實施例之變化形式的微電子單元結構之剖視圖；
圖24為說明根據圖18中所示之本發明一實施例之變化形式的微電子單元結構之剖視圖；
圖25為說明根據圖18中所示之本發明一實施例之變化形式的微電子單元結構之剖視圖；
圖26為說明根據圖1-圖18所示之實施例之變化形式之微電子單元製造方法中之階段之剖視圖；
圖27為說明根據圖1-圖18所示之實施例之變化形式之微電子單元製造方法中之另一階段之剖視圖；及
圖28為根據本發明一實施例之系統的示意性描述。
114．．．後表面
168．．．後接點
204．．．第一開口
206．．．第二開口
220．．．導電通孔/犧牲區域
258．．．第一開口之最大寬度
260．．．第二開口之最大寬度
262．．．導電通孔之最大寬度
264．．．裝襯第一開口之介電層
266．．．裝襯第二開口之介電層
270．．．焊劑遮罩
272．．．焊劑遮罩之開口

Claims (30)

  1. 一種微電子單元，其包含：包括單晶半導體區域且具有在第一方向上延伸之前表面的微電子元件、曝露在該前表面之前接點、鄰近該前表面之主動電路元件、遠離該前表面之後表面及在前表面之下向該後表面延伸之導電通孔、電耦合該導電通孔之多晶矽半導體材料區域，該導電通孔被放置在部分通過該單晶半導體區域之厚度延伸之溝槽中、及自後表面部分通過該單晶半導體區域之厚度之開口至少延伸到該多晶矽半導體材料區域，該開口及該多晶矽半導體材料區域在該第一方向上具有各別寬度，該開口之寬度大於該多晶矽半導體材料區域之寬度；及在該後表面暴露以與外部電路元件電連接並且藉由在該開口中之導電互連、藉由耦合至其之該多晶矽半導體材料區域、及藉由與該多晶矽半導體材料區域電耦合之該導電通孔而電耦合該前接點之後接點。
  2. 如請求項1之微電子單元，其另外包含該開口內之聚合物電介質，該聚合物電介質使該導電互連與該單晶半導體區域分離。
  3. 如請求項2之微電子單元，其中該導電互連與該開口之外形相符。
  4. 如請求項2之微電子單元，其中垂直方向為微電子元件在該前表面與該後表面之間的厚度方向，且該導電互連在該多晶矽半導體材料區域與該後接點之間的第二方向 上延伸，該第二方向至少實質上垂直。
  5. 如請求項4之微電子單元，其中該聚合物電介質包括在該第二方向上延伸之孔，且該開口鄰近於該孔之表面在朝向該前表面的第三方向上延伸，該第三方向相對於該第二方向呈銳角延伸。
  6. 如請求項1之微電子單元，其中該多晶矽半導體材料區域係經安置在該第一或平行於該前表面之第二方向中之至少一個方向上至少部分地超過該前接點之邊緣。
  7. 如請求項1之微電子單元，其中該多晶矽半導體材料區域之寬度不大於10微米。
  8. 如請求項1之微電子單元，其中該開口包括自該後表面延伸之第一開口、自該第一開口向該前表面延伸之第二開口，在該第一開口及該第二開口匯合的地方，該第一開口具有在該第一方向上之第一寬度且該第二開口具有小於該第一寬度之第二寬度，其中該第二開口至少延伸至該多晶矽半導體材料區域，且該後接點通過該第一開口及該第二開口與該多晶矽半導體材料區域電耦合。
  9. 如請求項8之微電子單元，其中該第二寬度大於該多晶矽半導體材料區域之寬度。
  10. 如請求項8之微電子單元，該第二開口在朝向該前表面之方向上逐漸變細至變得較小。
  11. 如請求項8之微電子單元，其中該第一開口在朝向該第二開口之方向上逐漸變細至變得較小。
  12. 如請求項1之微電子單元，其中該微電子元件包括複數 個多晶矽半導體材料區域，其之各者係至少部分地暴露在該開口內，且複數個該等後接點藉由複數個導電互連而電耦合該等多晶矽半導體材料區域。
  13. 如請求項12之微電子單元，其中該些複數個導電互連為與該等多晶矽半導體材料區域電耦合的複數個導電跡線該等導電跡線沿該開口之至少一個表面朝向該等後接點延伸。
  14. 如請求項12之微電子單元，其中該複數個後接點覆蓋該開口。
  15. 如請求項14之微電子單元，其中垂直方向為該微電子元件在該前表面與該後表面之間的厚度方向，且該等導電互連在該等多晶矽半導體材料區域與該等後接點之間的垂直方向上延伸。
  16. 一種微電子系統，其包含如請求項1之微電子單元及一或多個電連接至該微電子單元之其他電子組件。
  17. 如請求項16之微電子系統，其另外包含外殼，該微電子單元及該等其他電子組件係安裝至該外殼。
  18. 一種微電子單元之製造方法，其包含：提供微電子元件，其包括單晶半導體區域且具有前表面及暴露在該前表面的前接點、鄰近該前表面的主動電路元件、遠離該前表面之後表面之半導體區域及第一區域，該第一區域包括被安置在溝槽中而與該單晶半導體區域絕緣之多晶矽半導體材料或鎢中之一者，該單晶半導體區域朝向該後表面延伸、及整個被安置在該前和後 表面之間的通孔，該前接點係藉由該通孔而與該第一區域電耦合；通過自該後表面延伸且暴露該第一區域之開口來移除該第一區域之該多晶矽半導體或鎢材料之至少一部分；形成至少部分置換該所移除之該第一區域之多晶矽半導體或鎢材料的導電區域；形成電耦合至該導電區域且在該後表面暴露以與電路元件電連接之後接點。
  19. 如請求項18之方法，其中該形成該開口之步驟另外包括形成自該後表面向該前表面延伸之第一開口、在該第一開口內形成第一層、接著通過該第一層中之開口移除該單晶半導體區域之材料，形成自該第一開口向該前表面延伸之第二開口。
  20. 如請求項19之方法，其中該移除步驟藉由通過該第一開口及該第二開口施加之加工移除該第一區域之該多晶矽半導體或鎢材料之該至少一部分。
  21. 如請求項18之方法，其中該微電子元件另外包括使該第一區域與該單晶半導體區域分離之介電區域，且該第一區域之材料包括多晶半導體，其中該移除步驟移除該多晶半導體之至少一部分，且形成導電接點之步驟包括至少在該開口內形成遠離該第一區域延伸之導電互連，該後接點係與該導電互連電連接。
  22. 如請求項21之方法，其中該介電區域包括無機介電材料且該形成該介電層之步驟包括使聚合材料沈積於該開口 之至少一個內表面上。
  23. 如請求項21之方法，其中該移除步驟相對於該介電區域選擇性地移除該多晶半導體材料。
  24. 如請求項22之方法，其中該聚合材料係電化學沈積。
  25. 如請求項19之方法，其中該形成該第一層之步驟包括藉由將聚合物電化學沈積於至少該第一開口之內表面上形成裝襯該第一開口之介電層。
  26. 如請求項19之方法，其另外包含使用光微影以界定該第一層中該開口之程度及位置。
  27. 如請求項19之方法，其另外包含使用雷射以界定該第一層中該開口之程度及位置。
  28. 如請求項19之方法，其另外包含移除該第一層，接著在該第一開口及該第二開口之內表面上形成介電層，接著形成包括該後接點之導電結構，該導電結構係藉由該介電層與該單晶半導體區域絕緣。
  29. 如請求項19之微電子單元之製造方法，其中該形成該後接點之步驟包括在該第二開口之至少一個內表面上形成介電層，接著用導電材料填充至少該第二開口。
  30. 如請求項19之微電子單元之製造方法，其中該形成該後接點之步驟包括在該第二開口內形成第二介電層，接著將金屬層沈積於該第二介電層之表面上，該金屬層與至少該第二開口之外形相符。
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EP2596520A1 (en) 2013-05-29
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US20120018863A1 (en) 2012-01-26
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