JP5412506B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5412506B2 JP5412506B2 JP2011505820A JP2011505820A JP5412506B2 JP 5412506 B2 JP5412506 B2 JP 5412506B2 JP 2011505820 A JP2011505820 A JP 2011505820A JP 2011505820 A JP2011505820 A JP 2011505820A JP 5412506 B2 JP5412506 B2 JP 5412506B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- hole
- stacked
- conductive film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 404
- 239000000758 substrate Substances 0.000 claims description 163
- 239000010410 layer Substances 0.000 claims description 92
- 239000011248 coating agent Substances 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 19
- 238000003384 imaging method Methods 0.000 claims description 6
- 230000006870 function Effects 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 description 51
- 239000010953 base metal Substances 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 20
- 239000000463 material Substances 0.000 description 16
- 238000005530 etching Methods 0.000 description 14
- 230000004048 modification Effects 0.000 description 10
- 238000012986 modification Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000005498 polishing Methods 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下、本発明の第1の実施形態に係る半導体装置について、図面を参照しながら説明する。尚、以下に示す各図面の内容、並びに種々の構成要素の形状、材料及び寸法等はいずれも例示であって、本実施形態に示した内容には限定されない。また、本発明の趣旨を逸脱しない範囲において、本実施形態に示した内容を適宜変更可能である。
以下、本発明の第2の実施形態に係る半導体装置について、図面を参照しながら説明する。尚、以下に示す各図面の内容、並びに種々の構成要素の形状、材料及び寸法等はいずれも例示であって、本実施形態に示した内容には限定されない。また、本発明の趣旨を逸脱しない範囲において、本実施形態に示した内容を適宜変更可能である。
以下、本発明の第3の実施形態に係る積層型半導体装置、具体的には、本発明の第1又は第2の実施形態に係る半導体装置を少なくとも1つ含む複数の半導体装置が三次元的に積層された積層型半導体装置について、図面を参照しながら説明する。尚、以下に示す各図面の内容、並びに種々の構成要素の形状、材料及び寸法等はいずれも例示であって、本実施形態に示した内容には限定されない。また、本発明の趣旨を逸脱しない範囲において、本実施形態に示した内容を適宜変更可能である。
100a 半導体基板100のデバイス形成面(第1面)
100b 半導体基板100の裏面(第2面)
101 絶縁層(埋め込み絶縁層)
102、103 絶縁膜
104 絶縁膜(第1の絶縁性ビア被覆膜)
105 第1の導電膜
111 第1の孔
112 第2の孔
201 素子分離
202 ゲート電極
203 層間絶縁膜
204 配線
205 絶縁性サイドウォールスペーサ
301 多層配線構造
401 電極パッド
402 接続端子
500、500A、500B、500C 半導体装置
501 絶縁膜(第2の絶縁性ビア被覆膜)
502 下地金属層
503 第2の導電膜
504 接続端子
600 回路基板
604 電極パッド
605 封止樹脂(樹脂層)
Claims (16)
- 活性素子が形成された第1面及びその反対側の第2面を有する半導体基板と、
前記半導体基板を貫通する貫通ビアと、
前記活性素子上及び前記第1面上に形成された層間絶縁膜とを備え、
前記貫通ビアは、前記半導体基板における前記第1面側に形成された第1の導電膜と、前記半導体基板における前記第2面側に形成された第2の導電膜との積層構造を有し、
前記半導体基板において、前記第1面及び前記第2面から離間した内部に絶縁層が埋め込まれており、
前記第1の導電膜と前記第2の導電膜とは前記絶縁層中で電気的に接続していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の導電膜は、前記半導体基板における前記第1面側に形成された第1の孔に埋め込まれており、
前記第2の導電膜は、前記半導体基板における前記第2面側に形成された第2の孔に埋め込まれており、
前記第1の孔と前記第2の孔とが接続すると共に前記第1の導電膜と前記第2の導電膜とが電気的に接続することにより、前記貫通ビアが構成されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第1の孔における前記第2の孔との接続箇所での開口径と比べて、前記第2の孔における前記第1の孔との接続箇所での開口径の方が大きいことを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記第1の孔の深さは前記第2の孔の深さよりも深いことを特徴とする半導体装置。 - 請求項2〜4のいずれか1項に記載の半導体装置において、
前記第1の孔における前記第1面側での開口径と比べて、前記第2の孔における前記第2面側での開口径の方が大きいことを特徴とする半導体装置。 - 請求項1〜5のいずれか1項に記載の半導体装置において、
前記絶縁層は、前記半導体基板の面方向において不連続に形成されていることを特徴とする半導体装置。 - 請求項1〜6のいずれか1項に記載の半導体装置において、
前記第1の導電膜と前記半導体基板との間には第1の絶縁性ビア被覆膜が形成されており、
前記第2の導電膜と前記半導体基板との間には第2の絶縁性ビア被覆膜が形成されていることを特徴とする半導体装置。 - 請求項1〜7のいずれか1項に記載の半導体装置において、
前記半導体基板は、SIMOX基板又はSOI基板であり、
前記絶縁層は、前記SIMOX基板又は前記SOI基板の内部に設けられたシリコン酸化膜であることを特徴とする半導体装置。 - ロジック回路を有する第1の半導体装置と、固体撮像素子を有する第2の半導体装置とが積層されてなる積層型半導体装置であって、
前記第1の半導体装置及び前記第2の半導体装置のうちの少なくとも1つの半導体装置が、請求項1〜8のいずれか1項に記載の半導体装置であることを特徴とする積層型半導体装置。 - 請求項9に記載の積層型半導体装置において、
前記第1の半導体装置の上に前記第2の半導体装置が積層されていることを特徴とする積層型半導体装置。 - 第1の半導体装置と第2の半導体装置と第3の半導体装置とが積層されてなる積層型半導体装置であって、
前記第2の半導体装置は、前記第1の半導体装置における第1領域の上に積層されており、
前記第3の半導体装置は、前記第1の半導体装置における第2領域の上に積層されており、
前記第1の半導体装置、前記第2の半導体装置及び前記第3の半導体装置のうちの少なくとも1つの半導体装置が、請求項1〜8のいずれか1項に記載の半導体装置であることを特徴とする積層型半導体装置。 - 請求項11に記載の積層型半導体装置において、
前記第1の半導体装置、前記第2の半導体装置及び前記第3の半導体装置は、互いに異なる機能を有する半導体装置であることを特徴とする積層型半導体装置。 - 請求項11又は12に記載の積層型半導体装置において、
前記第2の半導体装置の頂部と前記第3の半導体装置の頂部とは同じ高さに位置していることを特徴とする積層型半導体装置。 - 請求項11〜13のいずれか1項に記載の積層型半導体装置において、
前記第1の半導体装置はロジック回路を有していることを特徴とする積層型半導体装置。 - 請求項11〜14のいずれか1項に記載の積層型半導体装置において、
前記第2の半導体装置はメモリ素子を有していることを特徴とする積層型半導体装置。 - 請求項11〜15のいずれか1項に記載の積層型半導体装置において、
前記第3の半導体装置は固体撮像素子を有していることを特徴とする積層型半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011505820A JP5412506B2 (ja) | 2009-03-27 | 2010-02-01 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009079743 | 2009-03-27 | ||
JP2009079743 | 2009-03-27 | ||
PCT/JP2010/000580 WO2010109746A1 (ja) | 2009-03-27 | 2010-02-01 | 半導体装置及びその製造方法 |
JP2011505820A JP5412506B2 (ja) | 2009-03-27 | 2010-02-01 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2010109746A1 JPWO2010109746A1 (ja) | 2012-09-27 |
JP5412506B2 true JP5412506B2 (ja) | 2014-02-12 |
Family
ID=42780448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011505820A Expired - Fee Related JP5412506B2 (ja) | 2009-03-27 | 2010-02-01 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8421238B2 (ja) |
JP (1) | JP5412506B2 (ja) |
WO (1) | WO2010109746A1 (ja) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8796135B2 (en) * | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
US9018094B2 (en) * | 2011-03-07 | 2015-04-28 | Invensas Corporation | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates |
US8853072B2 (en) | 2011-06-06 | 2014-10-07 | Micron Technology, Inc. | Methods of forming through-substrate interconnects |
US10269863B2 (en) | 2012-04-18 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for via last through-vias |
JP6074985B2 (ja) | 2012-09-28 | 2017-02-08 | ソニー株式会社 | 半導体装置、固体撮像装置、および半導体装置の製造方法 |
JP6002008B2 (ja) * | 2012-11-19 | 2016-10-05 | 富士電機株式会社 | 半導体装置の製造方法 |
US9076785B2 (en) | 2012-12-11 | 2015-07-07 | Invensas Corporation | Method and structures for via substrate repair and assembly |
CN103500729B (zh) * | 2013-10-18 | 2015-10-14 | 中国科学院上海微系统与信息技术研究所 | 硅转接板结构及其圆片级制作方法 |
JP6213143B2 (ja) * | 2013-10-23 | 2017-10-18 | 富士電機株式会社 | 半導体基板、及び、半導体基板の製造方法 |
US9771256B2 (en) * | 2014-06-29 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company Limited | Micro electro mechanical system (MEMS) device having via extending through plug |
KR102405745B1 (ko) | 2015-08-05 | 2022-06-03 | 삼성전자주식회사 | 반도체 장치 |
JP6725231B2 (ja) * | 2015-10-06 | 2020-07-15 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子、および電子装置 |
KR102473664B1 (ko) * | 2016-01-19 | 2022-12-02 | 삼성전자주식회사 | Tsv 구조체를 가진 다중 적층 소자 |
KR102572154B1 (ko) * | 2017-11-06 | 2023-08-30 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조 방법 |
SG10201803464XA (en) * | 2017-06-12 | 2019-01-30 | Samsung Electronics Co Ltd | Semiconductor memory device and method of manufacturing the same |
US10727244B2 (en) | 2017-06-12 | 2020-07-28 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of fabricating the same |
JP2022133964A (ja) * | 2021-03-02 | 2022-09-14 | ソニーグループ株式会社 | 半導体基板、半導体基板の製造方法及び半導体基板を有する電子機器 |
CN115621192A (zh) * | 2021-07-13 | 2023-01-17 | 长鑫存储技术有限公司 | 一种半导体结构及其形成方法 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1012720A (ja) * | 1996-06-27 | 1998-01-16 | Matsushita Electric Works Ltd | 半導体装置の製造方法 |
JPH1187526A (ja) * | 1997-06-25 | 1999-03-30 | Commiss Energ Atom | マイクロエレクトロニクス素子とエッチング困難な半導体材料と金属化された孔とを備えた構造 |
JPH11195706A (ja) * | 1998-01-05 | 1999-07-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001044197A (ja) * | 1999-08-04 | 2001-02-16 | Sharp Corp | 半導体装置及びその製造方法 |
US6352923B1 (en) * | 1999-03-01 | 2002-03-05 | United Microelectronics Corp. | Method of fabricating direct contact through hole type |
JP2004342690A (ja) * | 2003-05-13 | 2004-12-02 | Rohm Co Ltd | 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置 |
JP2004349537A (ja) * | 2003-05-23 | 2004-12-09 | Renesas Technology Corp | 半導体装置 |
JP2006060067A (ja) * | 2004-08-20 | 2006-03-02 | Rohm Co Ltd | 半導体チップの製造方法、半導体チップ、半導体装置の製造法および半導体装置 |
JP2007005404A (ja) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | 半導体基板への貫通配線の形成方法 |
WO2008035261A1 (en) * | 2006-09-22 | 2008-03-27 | Nxp B.V. | Electronic device and method for making the same |
JP2008300718A (ja) * | 2007-06-01 | 2008-12-11 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2933674B2 (ja) | 1990-05-01 | 1999-08-16 | 株式会社リコー | 電気粘性流体 |
JPH04145301A (ja) | 1990-10-08 | 1992-05-19 | Nobuo Mori | 電柱の支線角度の事前測定用器具 |
US6809421B1 (en) | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
JP4011695B2 (ja) | 1996-12-02 | 2007-11-21 | 株式会社東芝 | マルチチップ半導体装置用チップおよびその形成方法 |
US6734453B2 (en) * | 2000-08-08 | 2004-05-11 | Translucent Photonics, Inc. | Devices with optical gain in silicon |
JP4570809B2 (ja) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | 積層型半導体装置及びその製造方法 |
WO2004064159A1 (ja) | 2003-01-15 | 2004-07-29 | Fujitsu Limited | 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法 |
US7300857B2 (en) * | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
JP2008226989A (ja) * | 2007-03-09 | 2008-09-25 | Elpida Memory Inc | 半導体装置及び半導体装置の製造方法 |
KR101572600B1 (ko) * | 2007-10-10 | 2015-11-27 | 테세라, 인코포레이티드 | 다층 배선 요소와 마이크로전자 요소가 실장된 어셈블리 |
-
2010
- 2010-02-01 JP JP2011505820A patent/JP5412506B2/ja not_active Expired - Fee Related
- 2010-02-01 WO PCT/JP2010/000580 patent/WO2010109746A1/ja active Application Filing
-
2011
- 2011-08-25 US US13/218,034 patent/US8421238B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1012720A (ja) * | 1996-06-27 | 1998-01-16 | Matsushita Electric Works Ltd | 半導体装置の製造方法 |
JPH1187526A (ja) * | 1997-06-25 | 1999-03-30 | Commiss Energ Atom | マイクロエレクトロニクス素子とエッチング困難な半導体材料と金属化された孔とを備えた構造 |
JPH11195706A (ja) * | 1998-01-05 | 1999-07-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6352923B1 (en) * | 1999-03-01 | 2002-03-05 | United Microelectronics Corp. | Method of fabricating direct contact through hole type |
JP2001044197A (ja) * | 1999-08-04 | 2001-02-16 | Sharp Corp | 半導体装置及びその製造方法 |
JP2004342690A (ja) * | 2003-05-13 | 2004-12-02 | Rohm Co Ltd | 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置 |
JP2004349537A (ja) * | 2003-05-23 | 2004-12-09 | Renesas Technology Corp | 半導体装置 |
JP2006060067A (ja) * | 2004-08-20 | 2006-03-02 | Rohm Co Ltd | 半導体チップの製造方法、半導体チップ、半導体装置の製造法および半導体装置 |
JP2007005404A (ja) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | 半導体基板への貫通配線の形成方法 |
WO2008035261A1 (en) * | 2006-09-22 | 2008-03-27 | Nxp B.V. | Electronic device and method for making the same |
JP2008300718A (ja) * | 2007-06-01 | 2008-12-11 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US8421238B2 (en) | 2013-04-16 |
US20110309520A1 (en) | 2011-12-22 |
WO2010109746A1 (ja) | 2010-09-30 |
JPWO2010109746A1 (ja) | 2012-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5412506B2 (ja) | 半導体装置 | |
US11195818B2 (en) | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit | |
US11756936B2 (en) | Backside contact to improve thermal dissipation away from semiconductor devices | |
US9559002B2 (en) | Methods of fabricating semiconductor devices with blocking layer patterns | |
US8981532B2 (en) | Semiconductor device and manufacturing method thereof | |
US8841754B2 (en) | Semiconductor devices with stress relief layers | |
CN109962064B (zh) | 半导体装置及其制造方法、和包括其的半导体封装件 | |
US20110298097A1 (en) | Semiconductor device and method for manufacturing the same | |
JP2010287831A (ja) | 半導体装置およびその製造方法 | |
US20090108404A1 (en) | Semiconductor device | |
KR20120067525A (ko) | 반도체 소자 및 이의 제조 방법 | |
KR20220010852A (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
KR100791080B1 (ko) | 금속 패드 구조체를 갖는 전자 장치 및 그 제조방법 | |
US12033919B2 (en) | Backside or frontside through substrate via (TSV) landing on metal | |
TW202310365A (zh) | 三維元件結構及其形成方法 | |
JP2010114352A (ja) | 半導体装置の製造方法および半導体装置 | |
JP2013197533A (ja) | 記憶装置及びその製造方法 | |
US20230411249A1 (en) | Semiconductor device including a through silicon via structure and method of fabricating the same | |
US11309249B2 (en) | Semiconductor package with air gap and manufacturing method thereof | |
US20100019390A1 (en) | Semiconductor device, semiconductor chip, manufacturing methods thereof, and stack package | |
KR20140134132A (ko) | 반도체 소자 및 그 형성 방법 | |
TWI546866B (zh) | 半導體元件與製作方法 | |
JP2013058525A (ja) | 半導体装置、及びその製造方法 | |
KR101037420B1 (ko) | 반도체 소자의 형성 방법 | |
WO2010022970A1 (en) | A semiconductor device including stress relaxation gaps for enhancing chip package interaction stability |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120719 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20120730 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130827 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131004 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131029 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131111 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5412506 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |