SG10201803464XA - Semiconductor memory device and method of manufacturing the same - Google Patents
Semiconductor memory device and method of manufacturing the sameInfo
- Publication number
- SG10201803464XA SG10201803464XA SG10201803464XA SG10201803464XA SG10201803464XA SG 10201803464X A SG10201803464X A SG 10201803464XA SG 10201803464X A SG10201803464X A SG 10201803464XA SG 10201803464X A SG10201803464X A SG 10201803464XA SG 10201803464X A SG10201803464X A SG 10201803464XA
- Authority
- SG
- Singapore
- Prior art keywords
- conductive layer
- memory device
- semiconductor memory
- manufacturing
- body conductive
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer. FIG. 2B
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170073390A KR20180135526A (en) | 2017-06-12 | 2017-06-12 | Semiconductor memory device and manufactureing the same |
KR1020170166233A KR102533149B1 (en) | 2017-12-05 | 2017-12-05 | Semiconductor memory device and manufactureing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201803464XA true SG10201803464XA (en) | 2019-01-30 |
Family
ID=64334302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201803464XA SG10201803464XA (en) | 2017-06-12 | 2018-04-25 | Semiconductor memory device and method of manufacturing the same |
Country Status (5)
Country | Link |
---|---|
US (2) | US10692881B2 (en) |
JP (1) | JP6985212B2 (en) |
CN (1) | CN109037210B (en) |
DE (1) | DE102018110017B4 (en) |
SG (1) | SG10201803464XA (en) |
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JP2020155485A (en) * | 2019-03-18 | 2020-09-24 | キオクシア株式会社 | Semiconductor device and manufacturing method thereof |
KR102649568B1 (en) * | 2019-05-03 | 2024-03-21 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same, and memory device and system indlucing the semiconductor device |
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KR102671791B1 (en) * | 2020-01-13 | 2024-06-04 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
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-
2018
- 2018-04-25 SG SG10201803464XA patent/SG10201803464XA/en unknown
- 2018-04-26 DE DE102018110017.5A patent/DE102018110017B4/en active Active
- 2018-05-17 US US15/982,213 patent/US10692881B2/en active Active
- 2018-06-11 JP JP2018111100A patent/JP6985212B2/en active Active
- 2018-06-12 CN CN201810600087.4A patent/CN109037210B/en active Active
-
2020
- 2020-06-15 US US16/901,171 patent/US10886299B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2019004147A (en) | 2019-01-10 |
US20180358376A1 (en) | 2018-12-13 |
JP6985212B2 (en) | 2021-12-22 |
US20200312877A1 (en) | 2020-10-01 |
CN109037210A (en) | 2018-12-18 |
DE102018110017B4 (en) | 2023-09-14 |
DE102018110017A1 (en) | 2018-12-13 |
CN109037210B (en) | 2023-09-05 |
US10692881B2 (en) | 2020-06-23 |
US10886299B2 (en) | 2021-01-05 |
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