SG10201801892YA - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- SG10201801892YA SG10201801892YA SG10201801892YA SG10201801892YA SG10201801892YA SG 10201801892Y A SG10201801892Y A SG 10201801892YA SG 10201801892Y A SG10201801892Y A SG 10201801892YA SG 10201801892Y A SG10201801892Y A SG 10201801892YA SG 10201801892Y A SG10201801892Y A SG 10201801892YA
- Authority
- SG
- Singapore
- Prior art keywords
- logic
- power line
- connection structure
- manufacturing
- semiconductor device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/528—Geometry or layout of the interconnection structure
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- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Theoretical Computer Science (AREA)
- Ceramic Engineering (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Evolutionary Computation (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Disclosed are a semiconductor device and a method of manufacturing the same. The semiconducotr device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode. [FIG. 1]
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020170071832A KR102358481B1 (en) | 2017-06-08 | 2017-06-08 | Semiconductor device and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
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SG10201801892YA true SG10201801892YA (en) | 2019-01-30 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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SG10201801892YA SG10201801892YA (en) | 2017-06-08 | 2018-03-07 | Semiconductor device and method of manufacturing the same |
Country Status (5)
Country | Link |
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US (1) | US10403619B2 (en) |
KR (1) | KR102358481B1 (en) |
CN (1) | CN109037215B (en) |
SG (1) | SG10201801892YA (en) |
TW (1) | TWI761468B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9934347B2 (en) * | 2014-10-01 | 2018-04-03 | Samsung Electronics Co., Ltd. | Integrated circuit and method of designing layout of integrated circuit |
DE102021100870B4 (en) * | 2020-05-12 | 2024-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | HYBRID LAYOUT, PROCESS, SYSTEM AND STRUCTURE |
US11893333B2 (en) | 2020-05-12 | 2024-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid sheet layout, method, system, and structure |
KR20220048666A (en) * | 2020-10-13 | 2022-04-20 | 삼성전자주식회사 | Integrated circuit including a asymmetric power line and method for designing the same |
KR20220067590A (en) * | 2020-11-16 | 2022-05-25 | 삼성전자주식회사 | Semiconductor device |
KR20220144076A (en) * | 2021-04-19 | 2022-10-26 | 삼성전자주식회사 | Semiconductor device |
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JP2001338990A (en) * | 2000-05-26 | 2001-12-07 | Fujitsu Ltd | Semiconductor device |
CN1254864C (en) * | 2001-08-02 | 2006-05-03 | 联华电子股份有限公司 | Generation of standard logic unit data-base by merging power line |
US7139184B2 (en) | 2004-12-07 | 2006-11-21 | Infineon Technologies Ag | Memory cell array |
KR100665842B1 (en) * | 2004-12-24 | 2007-01-09 | 삼성전자주식회사 | Column path circuit layout in semiconductor memory device |
JP2007129250A (en) * | 2006-12-20 | 2007-05-24 | Fujitsu Ltd | Semiconductor device |
KR100919369B1 (en) | 2007-06-27 | 2009-09-25 | 주식회사 하이닉스반도체 | Semiconductor device |
US20090167394A1 (en) | 2007-12-31 | 2009-07-02 | Texas Instruments Incorporated | Integrated circuits having devices in adjacent standard cells coupled by the gate electrode layer |
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-
2017
- 2017-06-08 KR KR1020170071832A patent/KR102358481B1/en active IP Right Grant
- 2017-10-18 US US15/787,244 patent/US10403619B2/en active Active
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2018
- 2018-03-07 SG SG10201801892YA patent/SG10201801892YA/en unknown
- 2018-03-13 TW TW107108469A patent/TWI761468B/en active
- 2018-05-17 CN CN201810475600.1A patent/CN109037215B/en active Active
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KR20180134229A (en) | 2018-12-18 |
CN109037215A (en) | 2018-12-18 |
CN109037215B (en) | 2024-03-12 |
TW201909382A (en) | 2019-03-01 |
TWI761468B (en) | 2022-04-21 |
US10403619B2 (en) | 2019-09-03 |
US20180358345A1 (en) | 2018-12-13 |
KR102358481B1 (en) | 2022-02-04 |
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