KR100919369B1 - Semiconductor device - Google Patents

Abstract

According to the present invention, a contact plug is formed on a diagonal of one side of a source edge and the other of a drain edge in a high voltage transistor including a gate and a source / drain formed on a semiconductor substrate on both sides of the gate. By forming them to intersect, a method is disclosed in which the distance between the contact plug and the gate can be widened within the same area so that a high voltage can be transmitted without a voltage drop.

Gate line, transistor, high voltage, contact plug, voltage drop

Description

Semiconductor device

1 is a view for explaining a semiconductor device according to the present invention.

FIG. 2 is a layout diagram of a semiconductor device to which the high voltage transistor shown in FIG. 1 is applied.

<Explanation of symbols for main parts of the drawings>

100a, 100b: junction region 102: device isolation layer

104: gate 106: global wordline

108: local contact plug 110: global contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to semiconductor devices for preventing voltage drops between transistors and adjacent contact plugs.

The semiconductor device includes a plurality of transistors. These transistors are electrically connected to each other through a metal layer and a contact plug. In particular, the transistors may be connected to each other through a junction such as a source or a drain, and may be electrically connected through a contact plug formed on the junction and a metal wiring in contact with the junction.

In order to operate a semiconductor device, a driving voltage is required. In particular, a high voltage is mainly used as a driving voltage to perform a program or erase operation. Transistors used to deliver such high voltages are generally referred to as high voltage transistors. For example, in the case of a NAND flash memory device, when a high voltage is applied to a global word line during a program operation, and a turn-on voltage is applied to a gate line of the high voltage transistor, the high voltage transistor is turned on and the high voltage is a local word. Passed by local word line.

Specifically, when the high voltage transistor is turned on, a channel is activated between the junctions of the high voltage transistor. The channel electrically connects the junction with the junction. When the channel is activated, contact plugs and high voltage transistors connected to the global word line and the local word line are electrically connected to each other.

The high voltage transistor must deliver the high voltage applied from the global word line to the drain through the contact plug to the local word line through the contact plug formed in the source without a voltage drop. Here, the distance between the gate and the contact plug has a great influence on the voltage drop of the high voltage in the voltage transfer characteristic of the high voltage transistor. That is, only a sufficient distance between the gate of the high voltage transistor and the contact plug formed on the source or drain can be maintained so that the high voltage can be transmitted without a voltage drop. To this end, keeping the distance between the gate and the contact plug wide may increase the area occupied by the high voltage transistor, thereby lowering the degree of integration.

According to the present invention, a contact plug is formed on a diagonal of one side of a source edge and the other of a drain edge in a high voltage transistor including a gate and a source / drain formed on a semiconductor substrate on both sides of the gate. By forming to intersect (preferably in the vertical direction), the distance between the contact plug and the gate can be widened within the same area, so that high voltage can be transmitted without a voltage drop.

The semiconductor device according to the embodiment of the present invention includes a global word line. It includes a gate disposed diagonally in preparation for the global word line. And a drain formed in the semiconductor substrate between the gate and the global word line. And a source formed on the semiconductor substrate in a direction opposite to the drain with respect to the gate. A first contact plug is formed in a first region where the drain and the global word line overlap each other, and the first region is farthest from the gate. The semiconductor device includes a semiconductor device including a second contact plug formed in a second region that is farthest from the gate in the region in which the source is formed.

A semiconductor device according to another embodiment of the present invention includes first and second sources formed in an active region of a semiconductor substrate. And a drain formed between the first and second sources. And a global wordline formed on the central region of the drain. First and second gate lines are formed between the first and second sources and drains, respectively, and are symmetrical with respect to the global word line and have different distances between opposite ends thereof. And a first contact plug in contact with the global word line, the first contact plug being formed in the first region farthest from the vertical distance from the first and second gate lines. And a second contact plug formed on the first source and formed on the second region farthest from the first gate line. The semiconductor device may include a semiconductor device formed on the second source and including a third contact plug formed on the third region farthest from the second gate line.

The first gate is arranged such that the line vertically intersects between the first and second contact plugs, and the second gate line is arranged to vertically intersect between the first and third contact plugs.

In an embodiment, a semiconductor device may include a semiconductor substrate in which a first active region, an isolation layer, and a second active region are formed in parallel with each other. And a global word line formed over the center of the first active region, the device isolation layer, and the second active region. The first gate line and the second gate line may be symmetrical with respect to the global word line, and the symmetric intervals on the first and second active regions may be different from the symmetry interval on the device isolation layer. And a first drain contact plug formed on the first active region and in contact with the global word line, the first drain contact plug formed in the first region that is farthest from the first and second gate lines. And a second drain contact plug formed on the second active region and in contact with the global word line and formed on the second region farthest from the first region.

The first and second active regions include drains formed between the first and second gate lines, respectively, and first and second sources formed in opposite directions to the drains based on the first and second gate lines, respectively. On the first source, a first source contact plug is formed in a region where the vertical distance from the first gate line is farthest. In addition, the second source includes a second source contact plug formed in a region where the vertical distance from the second gate line is farthest.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a view for explaining a semiconductor device according to the present invention.

Referring to FIG. 1, the high voltage transistor includes a gate 104 and junction regions 100a and 100b formed at both sides of the gate 104. The junction region 100a may be a drain, and the junction region 100b may be a source. Contact plugs 108 and 110 are formed on the junction regions 100a and 100b, respectively. Reference numeral 102a, which has not been described, is an isolation layer. In the NAND flash memory device, the contact plug 110 formed on the drain 100a is connected to the global word line 106, and the contact plug 108 formed on the source 100b is connected to the local word line (not shown). Can be.

In the above, the contact plug 110 is formed in the first region where the vertical distance is the farthest from the gate 104 among the regions where the drain 100a and the global word line 106 overlap, and the contact plug 108 is a source. In the region where the 100b is formed, the second region is formed farthest from the gate 104. As such, the contact plugs 108 and 110 are formed on the diagonal. The gate 104 is formed diagonally between the contact plugs 108 and 110 and is preferably formed perpendicular to the diagonals of the sources / drains 100a and 100b. In this case, the spacing (A or B) between the gate 104 and the contact plugs 108 and 110 is made wider than when the contact plugs 108 and 110 are formed in the center of the source / drain 100a and 100b, respectively. Can be.

In the above structure, when a high voltage is applied to the global word line 106, the high voltage reaches the junction 100a through the contact plug 110. When a voltage is applied to the gate 104, a channel is formed under the gate 104 to electrically connect the drain 100a and the source 100b. Accordingly, the high voltage reached to the junction 100a is transmitted to the junction 100b through the channel, and the high voltage delivered to the junction 100b is transmitted to the word line (not shown) through the contact plug 108.

If the gate 104 is arranged in a straight line in parallel with the global word line 106, to secure a gap between the gate 104 and the contact plug 108 or the gate 104 and the contact plug 110. Is difficult, so a voltage drop can occur.

However, in the present invention, the gate 104 and the contact plugs 108 and 110 are adjusted by adjusting the positions of the contact plugs 108 and 110 and forming the gate 104 obliquely between the contact plugs 108 and 110 as described above. By increasing the interval of), it can transmit high voltage without dropping the voltage.

When the gate 104 is formed obliquely as shown in FIG. 1, the contact plug 108 is formed at the edge of the source 100b, and the contact plug 110 is formed at the edge of the drain 100a. In this case, the distance between the contact plugs 108a and 110 and the gate 104 may be adjusted, and the inclination angle θ of the gate 104 may also be adjusted. The angle θ of the gate 104 between the contact plugs 108 and 110 is preferably formed at an angle greater than 0 ° and less than 90 °, for example.

A case in which the high voltage transistor having the above structure is applied to a NAND flash memory device will be described below.

FIG. 2 is a layout diagram of a semiconductor device to which the high voltage transistor shown in FIG. 1 is applied.

Referring to FIG. 2, in a NAND flash memory device, a plurality of pairs of high voltage transistors sharing a junction region (eg, a drain) are provided, and a structure in which a plurality of pairs of transistors are arranged in parallel is required. The high voltage transistors included in the above structure serve to transfer the high voltage applied through the global word line 106 to the local word line (not shown). The pair of transistors includes two gates and three junction regions 100a to 100c. That is, the two transistors share the drain 100b between the gates, and the sources 100a and 100c are disposed on the opposite side of the drain 100a around the gates 104a and 104b, respectively. The first gate included in the pair of transistors is connected to the first gate included in the pair of adjacent transistors to form the first gate line 104a, and the second gate included in the pair of transistors is adjacent to the first gate line 104a. The second gate line 104b is connected to the second gate included in the pair of transistors.

Meanwhile, contact plugs 108a 108b and 110 are formed in the junction regions 100a to 100c included in the pair of transistors, respectively. The location where the contact plugs 108a, 108b and 110 are formed is important for the high voltage transistor to deliver a high voltage without dropping the voltage. The contact plugs 108a and 108b are formed in regions where the vertical distance from the gates 104a and 104b is farthest from the regions in which the source 100b is formed, and the contact plugs 110 share drains shared by the two transistors. 100a) It is preferable to form in a region where the vertical distance from the gate 104a and 104b is farthest from the center. In this case, the contact plugs 108a, 108b, and 110 are disposed in the drain 100a and the source 100b in a zigzag form in a pair of transistors. The contact plug 110 formed in the drain 100a is connected to the global word line 106, and the contact plugs 108a and 108b formed in the source 100b are connected to the local word line (not shown), respectively.

The first gate line 104a is formed between the drain contact plug 110 and the first source contact plug 108a. In this case, the distance between the first gate line 104a and the drain contact plug 110 and the first source contact plug 108a should be kept as far as possible. Therefore, the first gate line 104a is preferably formed in a direction perpendicular to the line connecting the drain contact plug 110 and the first source contact plug 108a. On the other hand, in the pair of adjacent transistors, contact plugs 108a and 110 are formed on opposite sides, respectively, so that the first gate line 104a must be formed in a wavy shape to maintain the maximum gap therebetween.

Similarly, the second gate line 104b is formed to maintain a distance between the drain contact plug 110 and the second source contact plug 108b, and the first gate line 104a based on the global word line 106. It is formed to be symmetrical. Thus, the first and second gate lines 104a and 104b are formed to be zigzag in symmetry with each other. For example, the interval between the first and second gate lines 104a and 104b is minimized in the odd-numbered device isolation region 102a, and the first and second gate lines 104a in the even-numbered device isolation region 102b. And 104b) are maximized.

By arranging the gate lines 104a and 104b and the contact plugs 108a, 108b, and 110 in the above structure, the gap can be secured to the maximum, so that a high voltage can be transmitted without a voltage drop.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, in a high voltage transistor including a gate and a source / drain formed on a semiconductor substrate on both sides of the gate, contact plugs are formed at a distance from the gate line of the transistor, respectively, and the gates are formed to cross the diagonal lines between the contact plugs. By increasing the distance between the contact plug and the gate within the same area, high voltage can be delivered without voltage drop.

Claims (9)

Global wordline; A gate disposed diagonally with respect to the global word line; A drain formed on the semiconductor substrate between the gate and the global word line; A source formed on the semiconductor substrate in a direction opposite to the drain with respect to the gate; A first contact plug formed in a first region of which the vertical distance is farthest from the gate among regions where the drain and the global word line overlap each other; And And a second contact plug formed in a second region of which the vertical distance is farthest from the gate among the regions where the source is formed. The method of claim 1, And the gate is disposed to vertically intersect the first and second contact plugs. First and second sources formed in the active region of the semiconductor substrate; A drain formed between the first and second sources; A global word line formed on a central region of the drain; First and second gate lines formed between the first and second sources and the drain, respectively, symmetrically with respect to the global word line, and having different distances between opposite ends of the global word lines; A first contact plug in contact with the global word line, the first contact plug being formed in a first region farthest from the vertical distance from the first and second gate lines; A second contact plug formed on an upper portion of the first source and formed on a second region farthest from the first gate line; And And a third contact plug formed on the second source, the third contact plug being formed on the third region farthest from the second gate line. The method of claim 3, wherein And the first gate line is disposed to vertically intersect the first and second contact plugs. The method of claim 3, wherein And the second gate line is disposed to vertically intersect the first and third contact plugs. A semiconductor substrate having a first active region, an isolation layer, and a second active region parallel to each other; A global word line formed on a center of the first active region, the device isolation layer, and the second active region; First and second gate lines that are symmetrical with respect to the global word line and have symmetric spacings on the first and second active regions different from symmetric spacings on the device isolation layer; A first drain contact plug formed on the first active region and in contact with the global word line and formed in a first region farthest from the first and second gate lines; And And a second drain contact plug formed on the second active region and in contact with the global word line and formed on a second region farthest from the first region. The method of claim 6, wherein the first and second active regions, A drain formed between the first and second gate lines, respectively; And And first and second sources respectively formed in opposite directions to the drain based on the first and second gate lines. The method of claim 7, wherein And a first source contact plug on the first source, the first source contact plug being formed in an area farthest from the first gate line. The method of claim 7, wherein And a second source contact plug on the second source, the second source contact plug being formed in a region farthest from the second gate line.

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