SG10201804464UA - Three-dimensional semiconductor memory device and method of fabricating the same - Google Patents
Three-dimensional semiconductor memory device and method of fabricating the sameInfo
- Publication number
- SG10201804464UA SG10201804464UA SG10201804464UA SG10201804464UA SG10201804464UA SG 10201804464U A SG10201804464U A SG 10201804464UA SG 10201804464U A SG10201804464U A SG 10201804464UA SG 10201804464U A SG10201804464U A SG 10201804464UA SG 10201804464U A SG10201804464U A SG 10201804464UA
- Authority
- SG
- Singapore
- Prior art keywords
- insulating layer
- cell array
- peripheral circuit
- fabricating
- semiconductor memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Abstract
OF THE DISCLOSURE Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region. FIG. 4
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170112028A KR102452562B1 (en) | 2017-09-01 | 2017-09-01 | Three-dimensional semiconductor devices and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201804464UA true SG10201804464UA (en) | 2019-04-29 |
Family
ID=65514800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201804464UA SG10201804464UA (en) | 2017-09-01 | 2018-05-25 | Three-dimensional semiconductor memory device and method of fabricating the same |
Country Status (4)
Country | Link |
---|---|
US (2) | US10566338B2 (en) |
KR (1) | KR102452562B1 (en) |
CN (1) | CN109427803A (en) |
SG (1) | SG10201804464UA (en) |
Families Citing this family (14)
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US10714536B2 (en) * | 2018-10-23 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to form memory cells separated by a void-free dielectric structure |
TWI681553B (en) * | 2019-03-21 | 2020-01-01 | 華邦電子股份有限公司 | Integrated circuit and method of manufacturing the same |
US10971508B2 (en) | 2019-04-23 | 2021-04-06 | Winbond Electronics Corp. | Integrated circuit and method of manufacturing the same |
KR20200132136A (en) * | 2019-05-15 | 2020-11-25 | 삼성전자주식회사 | Three dimensional semiconductor memory device |
FR3099299B1 (en) * | 2019-07-24 | 2021-08-06 | Commissariat Energie Atomique | ASSEMBLY MOLD TO MANUFACTURE A THREE-DIMENSIONAL DEVICE INCLUDING SEVERAL MICROELECTRONIC COMPONENTS |
CN110770902B (en) * | 2019-08-23 | 2021-08-17 | 长江存储科技有限责任公司 | Vertical storage device |
KR20210054373A (en) * | 2019-11-05 | 2021-05-13 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
KR20210090929A (en) * | 2020-01-13 | 2021-07-21 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
CN111244046B (en) * | 2020-01-20 | 2021-09-21 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
KR20210136459A (en) * | 2020-05-07 | 2021-11-17 | 에스케이하이닉스 주식회사 | Semiconductor memory device and manufacturing method of the same |
WO2022082345A1 (en) * | 2020-10-19 | 2022-04-28 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional nand memory device with split channel gates |
KR20220078102A (en) * | 2020-12-03 | 2022-06-10 | 삼성전자주식회사 | Semiconductor device and electronic system including the same |
CN113707664B (en) * | 2021-08-26 | 2024-04-09 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
CN114270515A (en) * | 2021-09-01 | 2022-04-01 | 长江存储科技有限责任公司 | Method for forming dielectric layer in forming semiconductor device |
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-
2017
- 2017-09-01 KR KR1020170112028A patent/KR102452562B1/en active IP Right Grant
-
2018
- 2018-03-15 US US15/922,186 patent/US10566338B2/en active Active
- 2018-05-25 SG SG10201804464UA patent/SG10201804464UA/en unknown
- 2018-08-31 CN CN201811018562.3A patent/CN109427803A/en active Pending
-
2020
- 2020-02-18 US US16/793,301 patent/US10916554B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN109427803A (en) | 2019-03-05 |
US10566338B2 (en) | 2020-02-18 |
US20200185398A1 (en) | 2020-06-11 |
KR20190025795A (en) | 2019-03-12 |
US20190074282A1 (en) | 2019-03-07 |
KR102452562B1 (en) | 2022-10-11 |
US10916554B2 (en) | 2021-02-09 |
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