SG10201803458SA - Semiconductor memory device and method of manufacturing the same - Google Patents
Semiconductor memory device and method of manufacturing the sameInfo
- Publication number
- SG10201803458SA SG10201803458SA SG10201803458SA SG10201803458SA SG10201803458SA SG 10201803458S A SG10201803458S A SG 10201803458SA SG 10201803458S A SG10201803458S A SG 10201803458SA SG 10201803458S A SG10201803458S A SG 10201803458SA SG 10201803458S A SG10201803458S A SG 10201803458SA
- Authority
- SG
- Singapore
- Prior art keywords
- work
- electrode structure
- layer
- function adjustment
- memory device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element. Fig. 2A
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170092879A KR102279732B1 (en) | 2017-07-21 | 2017-07-21 | Semiconductor memory device and method of forming the same |
Publications (1)
Publication Number | Publication Date |
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SG10201803458SA true SG10201803458SA (en) | 2019-02-27 |
Family
ID=65023430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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SG10201803458SA SG10201803458SA (en) | 2017-07-21 | 2018-04-25 | Semiconductor memory device and method of manufacturing the same |
Country Status (4)
Country | Link |
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US (2) | US10312243B2 (en) |
KR (1) | KR102279732B1 (en) |
CN (1) | CN109285835B (en) |
SG (1) | SG10201803458SA (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102279732B1 (en) | 2017-07-21 | 2021-07-22 | 삼성전자주식회사 | Semiconductor memory device and method of forming the same |
KR102657070B1 (en) | 2019-01-03 | 2024-04-16 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
TWI678794B (en) * | 2019-02-01 | 2019-12-01 | 華邦電子股份有限公司 | Dynamic random access memory and method of fabricating the same |
US11211491B2 (en) * | 2019-07-24 | 2021-12-28 | Nanya Technology Corporation | Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same |
US11315930B2 (en) * | 2020-02-14 | 2022-04-26 | Nanya Technology Corporation | Semiconductor structure and method of manufacturing the same |
US11264390B2 (en) * | 2020-04-16 | 2022-03-01 | Nanya Technology Corporation | Semiconductor memory device with air gaps between conductive features and method for preparing the same |
KR20220033587A (en) * | 2020-09-08 | 2022-03-17 | 삼성전자주식회사 | Semiconductor devices |
CN114695269A (en) * | 2020-12-30 | 2022-07-01 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
US11424360B1 (en) | 2021-02-04 | 2022-08-23 | Nanya Technology Corporation | Semiconductor device and method for manufacturing the same |
CN113540092B (en) * | 2021-07-14 | 2024-03-15 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
US11895830B2 (en) * | 2021-12-03 | 2024-02-06 | Nanya Technology Corporation | Method for manufacturing semiconductor device |
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KR102156643B1 (en) * | 2014-05-14 | 2020-09-17 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of the same |
KR102162733B1 (en) * | 2014-05-29 | 2020-10-07 | 에스케이하이닉스 주식회사 | Dual work function bruied gate type transistor, method for manufacturing the same and electronic device having the same |
KR102250583B1 (en) * | 2014-12-16 | 2021-05-12 | 에스케이하이닉스 주식회사 | Semiconductor device having dual work function gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same |
KR102242989B1 (en) * | 2014-12-16 | 2021-04-22 | 에스케이하이닉스 주식회사 | Semiconductor device having dual work function gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same |
KR102295641B1 (en) | 2015-03-02 | 2021-08-27 | 삼성전자주식회사 | Semiconductor device and manufacturing the same |
KR102271239B1 (en) * | 2015-03-23 | 2021-06-29 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
KR102336033B1 (en) | 2015-04-22 | 2021-12-08 | 에스케이하이닉스 주식회사 | Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same |
KR102230196B1 (en) | 2015-04-23 | 2021-03-19 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
KR102389819B1 (en) * | 2015-06-17 | 2022-04-22 | 삼성전자주식회사 | Method for manufacturing Semiconductor device having oxidized barrier layer |
KR102381342B1 (en) | 2015-09-18 | 2022-03-31 | 삼성전자주식회사 | Method of Forming a Semiconductor Device Having a Gate |
KR102396085B1 (en) | 2015-10-28 | 2022-05-12 | 에스케이하이닉스 주식회사 | Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same |
KR102481478B1 (en) | 2016-06-16 | 2022-12-26 | 삼성전자 주식회사 | Semiconductor devices and method of forming the same |
KR102279732B1 (en) | 2017-07-21 | 2021-07-22 | 삼성전자주식회사 | Semiconductor memory device and method of forming the same |
-
2017
- 2017-07-21 KR KR1020170092879A patent/KR102279732B1/en active IP Right Grant
-
2018
- 2018-03-14 US US15/920,628 patent/US10312243B2/en active Active
- 2018-04-25 SG SG10201803458SA patent/SG10201803458SA/en unknown
- 2018-07-16 CN CN201810777809.3A patent/CN109285835B/en active Active
-
2019
- 2019-05-07 US US16/405,548 patent/US10818672B2/en active Active
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KR102279732B1 (en) | 2021-07-22 |
US20190027480A1 (en) | 2019-01-24 |
CN109285835B (en) | 2023-08-18 |
KR20190010805A (en) | 2019-01-31 |
US10312243B2 (en) | 2019-06-04 |
US20190267386A1 (en) | 2019-08-29 |
US10818672B2 (en) | 2020-10-27 |
CN109285835A (en) | 2019-01-29 |
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