JP6149634B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  The field effect transistor has a gate electrode formed on a semiconductor substrate via a gate insulating film, and source / drain regions formed on both sides of the gate electrode in the semiconductor substrate. The gate electrode includes a polysilicon gate formed from a polysilicon film and a metal gate formed from a metal film.

  As a method of adjusting the effective work function of the polysilicon gate, there is a method of changing the amount of impurities implanted into the gate electrode. On the other hand, in the metal gate, the work function cannot be changed by adjusting the impurity implantation amount, so that the adjustment range of the threshold voltage tends to be narrower than that of the polysilicon gate.

  The following example is known as a method for adjusting a threshold voltage in a MOSFET having a polysilicon gate or a MOSFET having a metal gate, that is, a method for adjusting a work function of a gate electrode.

For example, a stacked structure of a silicon dioxide film as a gate insulating film and a high dielectric constant (high-k) dielectric film containing hafnium-based oxide is formed on a silicon substrate, and a polysilicon gate is formed thereon. MOSFETs having such are known. In this structure, the threshold voltage is changed by changing the annealing temperature of the high-k dielectric film by lamp annealing. In this case, the annealing temperature is set in the range of 900 ° C. to 1050 ° C., for example. In addition, by covering a part of the plurality of MOSFETs with a protective film of SiO ₂ or Si ₃ N ₄ , the temperature due to the lamp annealing to the high-k dielectric film of some of the MOSFETs is differentiated. There is known a method for making different threshold values of MOSFETs. In this case, lamp annealing is applied in a direction perpendicular to the substrate surface, and the annealing temperature for the MOSFET is controlled by utilizing the difference in reflectance of the film surface by adjusting the thickness of the protective film.

Further, an HfO ₂ film is formed as a gate insulating film on the silicon substrate, a metal gate made of TaN is formed thereon, and a two-layer monolayer La ₂ Hf ₂ O ₇ interface layer is formed between the metal gate and the gate insulating film. A MOSFET having a structure in which is formed is known. In this case, the La ₂ Hf ₂ O ₇ interface layer of the two-layer monolayer is annealed to change its work function. In this case, the annealing temperature is set within a range of 600 ° C. to 1000 ° C., for example.

Furthermore, a structure is known in which a silicon dioxide film and an HfO ₂ film are formed as a gate insulating film on a silicon substrate, and a TiN film, a TiAl film, a metal cap layer, and a tungsten (W) layer are formed as metal gates thereon. It has been. In this structure, it is known that the work function of the gate electrode is changed by diffusing Al from the TiAl film to the TiN film by annealing the metal gate. In this structure, it is also known that the work function is made different by changing the annealing temperature, and it is known that the annealing temperature is set to 420 ° C. and 520 ° C., for example. It is also known that with this structure, the work function after annealing can be reduced by continuously forming a TiN film and a TiAl film without breaking the vacuum. It is also known that the work function of the gate electrode is changed by changing the ratio of the thickness of the TiN film to the thickness of the TiAl film.

JP 2010-021365 A JP 2007-324593 A A. Veloso et al. "Gate-last vs. gate-first technology for aggressively scaled EOT logic / RF CMOS" 2011 Symposium on VLSI Technology, pp.34-35

  In the process of forming a MOS transistor having a metal gate, first, a dummy gate is formed on a silicon substrate, and then a source / drain region is formed in the silicon substrate by impurity ion implantation, and the source / drain region is activated by annealing. Turn into. After that, an interlayer insulating film for embedding the dummy gate is formed. Further, after the interlayer insulating film is polished to expose the upper surface of the dummy gate, the dummy gate is selectively removed and then the dummy gate is removed. A metal gate is formed in the recessed portion.

Even if the metal gate is covered with the SiO ₂ protective film to reflect light and the heating temperature is adjusted by lamp annealing as described above, the upper surface of the metal gate is also a reflective surface. It is difficult to adjust the temperature difference between them.

  Further, when a metal gate having a laminated structure including a TiN layer, a TiAl layer, and a W layer is to be formed, a thickness formed as an intermediate layer in a narrow recess, for example, a thickness of a 2.7 nm TiAl film It is difficult to change the work function by adjusting each of the metal gates.

  An object of the present invention is to provide a semiconductor device capable of making threshold voltages of a plurality of MOS transistors each having a metal gate whose periphery is covered with an insulating film, and a method for manufacturing the same.

According to one aspect of the present embodiment, a step of forming a first dummy gate on a first region and a second dummy gate on a second region of the semiconductor substrate, and the first region of the semiconductor substrate Forming a first pair of source / drain regions on both sides of the first dummy gate, and a second pair of source / drain regions on both sides of the second dummy gate in the second region of the semiconductor substrate. Forming a source / drain region; forming a first insulating film around each of the first dummy gate and the second dummy gate; removing the first dummy gate and the second dummy gate; Forming a first recess and a second recess in the first insulating film; and forming a gate insulating film on the inner surface of the first recess, the inner surface of the second recess, and the first insulating film; The first metal on the gate insulating film Forming a second metal layer that includes a work function metal and is different from the first metal layer on the first metal layer, and forming the second metal layer on the second metal film layer. Forming a third metal layer different from the two metal layers, removing the first metal layer, the second metal layer, and the third metal layer from above the first insulating film, and in the first recess and the A step of leaving the second concave portion as a first gate electrode and a second gate electrode, a step of selectively thinning the third metal layer in the second concave portion, and the three metal layers having different thicknesses Lamp annealing the first gate electrode and the second gate electrode each having the following: diffusing the work function metal from the second metal layer to the first metal layer in the second gate electrode. A method for manufacturing a semiconductor device is provided.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

  According to this embodiment, the threshold voltages of a plurality of MOS transistors having a metal gate whose periphery is covered with an insulating film can be made different.

FIGS. 1A to 1C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 2A to 2C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 3A to 3C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 4A to 4C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 5A to 5C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 6A to 6C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. 7A to 7C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. FIGS. 8A to 8C are plan views showing the manufacturing steps of the semiconductor device according to the first embodiment. FIGS. 9A to 9C are plan views illustrating the manufacturing steps of the semiconductor device according to the first embodiment. FIGS. 10A to 10C are plan views showing the manufacturing steps of the semiconductor device according to the first embodiment. FIGS. 11A to 11C are plan views showing the manufacturing steps of the semiconductor device according to the first embodiment. FIG. 12 is a perspective view of the semiconductor device according to the second embodiment. 13A to 13C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. 14A to 14C are plan views of the device formed by the semiconductor device manufacturing process according to the second embodiment. 15A to 15C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. 16A to 16C are plan views of the device formed by the manufacturing process of the semiconductor device according to the second embodiment. 17A to 17C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. 18A and 18B are a cross-sectional view and a plan view of the semiconductor device according to the second embodiment. 19A to 19C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. 20A to 20C are plan views of the device formed by the manufacturing process of the semiconductor device according to the second embodiment. FIGS. 21A to 21C are plan views showing the manufacturing steps of the semiconductor device according to the second embodiment.

  Embodiments will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.

(First embodiment)
1 to 7 are cross-sectional views showing the steps of forming the semiconductor device according to the present embodiment, and FIGS. 8 to 11 are plan views thereof.

First, the semiconductor device forming process according to the first embodiment includes a silicon substrate which is a semiconductor substrate as illustrated in FIG. 1A showing a plan view shown in FIG. A silicon oxide film 2 and a silicon nitride film 3 are formed on 1 by, for example, a CVD method. Further, a photoresist is applied on the silicon nitride film 3. Thereafter, the photoresist is exposed to light, developed, and the like, thereby forming a resist pattern R ₁ that covers the first and second transistor formation regions A ₁ and A ₂ and exposes the periphery thereof. Note that a plurality of first and second transistor formation regions A ₁ and A ₂ are arranged although not particularly shown.

Next, as shown in FIG. 1 (b), a resist pattern R ₁ is used as a mask, the silicon nitride film 3, a silicon oxide film 2 is etched. Thereafter, the resist pattern R ₁ and chlorine-based gas using the patterned silicon nitride film 3 as a mask, for example, dry etching using a chlorine gas to etch the silicon substrate 1 by, for example, reactive ion etching (RIE) . Thereby, the element isolation trench 1a as illustrated in FIGS. 1C and 8B is formed. Thereafter, the silicon nitride film 3 and the silicon oxide film 2 are removed by wet etching using, for example, buffered hydrofluoric acid.

Next, as illustrated in FIG. 2A, an insulating film 4a, for example, a silicon oxide film is formed on the upper surface of the silicon substrate 1 and the inner surface of the element isolation groove 1a by the CVD method, and the element isolation groove 1a is formed. The insulating film 4a is completely filled. Thereafter, as illustrated in FIGS. 2B and 8C, the insulating film 4a is removed from the first and second transistor formation regions A ₁ and A ₂ by a chemical mechanical polishing (CMP) method. The insulating film 4a left in the element isolation trench 1a is used as the element isolation insulating film 4. Incidentally, the insulating film 4a may be formed before the silicon nitride film 3 is removed. In this case, the insulating film 4a is polished by CMP to expose the silicon nitride film 3, and then the silicon nitride film 3 is removed. Thereafter, the silicon oxide film 2 on the upper surface of the silicon substrate 1 is removed.

Thereafter, the first conductivity type first and second wells 5a are formed by ion-implanting a first conductivity type impurity, for example, a p-type impurity such as boron, into the first and second transistor formation regions A ₁ and A ₂ . 5b.

Next, as illustrated in FIG. 2C, a polysilicon film 6 is formed to a thickness of, for example, 30 nm to 60 nm on the exposed main surface of the silicon substrate 1 and the element isolation insulating film 4 by a CVD method. Further, a photoresist is applied on the polysilicon film 6 and exposed, developed, etc., so that a gate electrode-shaped resist pattern R _{2 is formed in} a region passing through the center of the first and second wells 5a and 5b. Form.

Next, using the resist pattern R ₂ as a mask, the polysilicon film 6 is etched by, eg, RIE, and the polysilicon film 6 is gated in each region including the first and second wells 5 a and 5 b and the element isolation insulating film 4. Use electrode shape. Thereafter, the resist pattern is removed _{R 2.} The gate electrode-shaped polysilicon film 6 is used as first and second dummy gates 6a and 6b as illustrated in FIG. 9A. The first and second dummy gates 6a and 6b are patterned so that their widths are substantially the same in the range of 15 nm to 25 nm.

Next, using the first and second dummy gates 6a and 6b as a mask, a second conductivity type impurity such as arsenic or phosphorus is applied to the first and second transistor formation regions A ₁ and A ₂ of the silicon substrate 1. Ion implantation. Thus, as illustrated in FIG. 3A, extension regions 8a to 8d having low impurity concentrations are formed on both sides of the first and second dummy gates 6a and 6b.

  Next, for example, a silicon nitride film is formed as an insulating film on the silicon substrate 1 and the first and second dummy gates 6a and 6b. Thereafter, the silicon nitride film is etched back to leave the silicon nitride film on the side surfaces of the first and second dummy gates 6a and 6b as illustrated in the plan view of FIG. Silicon films are used as insulating sidewalls 7a and 7b.

  Next, as illustrated in the cross-sectional view of FIG. 3B, the second conductive material is formed on both sides of the region including the first and second dummy gates 6a and 6b and the sidewalls 7a and 7b in the silicon substrate 1. A type impurity is ion-implanted to form second conductivity type impurity diffusion regions 8e to 8h. The impurity diffusion regions 8e to 8h overlap the extension regions 8a to 8d on both sides of each of the first and second dummy gates 6a and 6b, and are formed with a higher impurity concentration than the extension regions 8a to 8d. Thus, the extension regions 8a to 8d and the impurity diffusion regions 8e to 8h connected to each other on both sides of the first and second dummy gates 6a and 6b become the second conductivity type source / drain regions 9a to 9d, respectively.

  Next, as illustrated in FIG. 3C, a silicon oxide film is formed as an interlayer insulating film 11 on the surfaces of the first and second dummy gates 6a and 6b, the side walls 7a and 7b, and the silicon substrate 1 by plasma CVD. Form by the method. Thereafter, as illustrated in the cross-sectional view of FIG. 4A and the plan view of FIG. 9C, the upper surface of the silicon oxide film 11 is polished by CMP to flatten the upper surface, and the first, The upper surfaces of the second dummy gates 6a and 6b are exposed. In this case, the upper ends of the sidewalls 7a and 7b are also exposed.

  Next, as illustrated in the cross-sectional view of FIG. 4B and the plan view of FIG. 10A, the first and second dummy gates 6a and 6b are selectively removed, and the interlayer insulating film 11 includes First, second gate-shaped recesses 10a and 10b are formed.

  Next, as illustrated in FIG. 4C, a high-as gate insulating film 12 is formed on the upper surface of the silicon substrate 1 and the upper surface of the interlayer insulating film 11 in the first and second gate-shaped recesses 10a and 10b. A k dielectric layer, such as a hafnium oxide layer, is formed. Subsequently, a titanium nitride (TiN) layer is formed as a first metal layer 13 on the gate insulating film 12 by a sputtering method, for example, to a thickness of 1 nm to 3 nm, for example. Further, an aluminum nitride (TiAl) layer, for example, is formed as a second metal layer 14 on the first metal layer 13 to a thickness of 2 nmn to 5 nm, for example, by sputtering.

  The first metal layer 13 and the second metal layer 14 become part of a gate electrode described later. The second metal layer 14 is made of a work function adjusting metal (work function metal) such as TiAl, and is made of a material different from that of the first metal layer 13. That is, the second metal layer 14 thermally diffuses the work function adjusting metal element contained therein, for example, Al, into the first metal layer 13 close to the substrate, thereby reducing the work function of the gate electrode, that is, the threshold voltage of the MOS transistor. It has a function to adjust.

  Next, as illustrated in FIG. 5A, at least the first and second gate-shaped recesses 10 a and 10 b are completely filled as the third metal layer 15 on the second metal layer 14, for example, as a third metal layer 15. It is formed by sputtering so as to have a thickness. The third metal layer 15 is formed from a material different from that of the second metal layer 13.

  Thereafter, as illustrated in the cross-sectional view of FIG. 5B and the plan view of FIG. 10B, the gate insulating film 12 and the first to third metal layers 13 to 15 on the interlayer insulating film 11 are subjected to CMP. Remove with. Thereby, the first to third metal layers 13 to 15 left in the first and second gate-shaped recesses 10a and 10b are used as first and second gate electrodes 16a and 16b, which are metal gates, respectively. The

  Next, as illustrated in FIGS. 5C and 10C, a silicon oxide film 17 is formed as an insulating film on the interlayer insulating film 11 and the first and second gate electrodes 16a and 16b, for example. It is formed by the CVD method. Thereafter, the silicon oxide film 17 is patterned using photolithography and etching to form an opening 17a that exposes the upper surface of the second gate electrode 16b and to cover the first gate electrode 16a.

Next, the silicon substrate 1 is put into the etching chamber of the RIE apparatus, and the pressure is set to 1 Pa to 100 Pa. Further, in the etching chamber, a high frequency power source applied to the electrode is set to a frequency of 13.56 MHz, for example, a chlorine-based gas such as chlorine (Cl ₂ ) is introduced as a reaction gas, and the temperature of the silicon substrate 1 is set to about 100 ° C., for example. Set to.

  Thereby, as illustrated in FIG. 6A, the interlayer insulating film 11 and the silicon oxide film 17 thereon are used as a mask, and the second gate electrode 16b exposed from the opening 17a is etched from above. The height is lowered to, for example, about 30 nm. As a result, a space is formed above the second gate-shaped recess 10b. In this case, the thickness of each of the gate insulating film 12, the first metal layer 13 and the second metal layer 14 formed in parallel along the upper surface of the silicon substrate 1 is not changed, but the second metal layer The third metal layer 15 formed on 14 is thinner than the original. As a result, the volume of the third metal layer 15 of the second gate electrode 16b is smaller than the volume of the third metal layer 15 of the first gate electrode 16a.

The first gate electrode 16a thus formed and the source / drain regions 9a, 9b on both sides thereof form a _first NMOS transistor T1, and the second gate electrode 16b and the sources on both sides thereof. / drain regions 9c, the second NMOS transistor _{T 2} is formed by a 9d.

  Next, as illustrated in FIG. 6B, a silicon oxide film 18 is formed by CVD as another insulating film on the silicon oxide film 17 and in the opening 17a. As a result, the space formed on the second gate electrode 16b is filled with the silicon oxide film 18 in the second gate-shaped recess 10b. Thereafter, as illustrated in the cross-sectional view of FIG. 6C and the plan view of FIG. 11A, the silicon oxide films 17 and 18 are polished from the upper surface by the CMP method, and the upper surface of the first gate electrode 16a is polished. Expose. As a result, the silicon oxide films 17 and 18 on the upper surface of the interlayer insulating film 11 are removed, and the silicon oxide film 18 on the second gate electrode 16b is left in the second gate-shaped recess 10b. 11 is planarized with respect to the upper surface.

  Next, the silicon substrate 1 is transported into a lamp annealing apparatus, in which lamp annealing is performed by a lamp (not shown) disposed above the silicon substrate 1 as illustrated in FIG. Examples of the lamp annealing include rapid thermal annealing (RTA) and flash lamp annealing (FLA). In general, a W halogen lamp is used for RTA, which emits light at an infrared wavelength of about 400 nm to several μm in the visible region. Further, a Xe flash lamp is generally used as the FLA, and emits light at a wavelength of about 200 nm in the ultraviolet region to about 800 nm in the near ultraviolet region. In these wavelength regions, since the silicon oxide film does not absorb the light, lamp annealing may be performed without forming the silicon oxide film 18 on the second gate electrode 16b.

  As annealing conditions, the first and second gate electrodes 16a and 16b are heated at, for example, 400 ° C. to 900 ° C. for about 1 second to 10 seconds.

  According to such a condition, the third metal layer 15 in the second gate electrode 16b is half or less than the third metal layer 15 in the first gate electrode 16a. . For this reason, the heat capacity of the third metal layer 15 in the second gate electrode 16b is smaller than the heat capacity of the third metal layer 15 in the first gate electrode 16a and is likely to become high temperature by lamp annealing. Therefore, the time for reaching the temperature at which the Al element in the second metal layer 14 can diffuse into the first metal layer 13 by lamp annealing is shorter in the second gate electrode 16b than in the first gate electrode 16a. Further, after the lamp annealing is stopped, the heat remaining in the first and second gate electrodes 16a and 16b is also released from the upper surface of the third metal layer 15, so that the first and second gate electrodes 16a, The temperature drop time of 16b is almost the same. Therefore, the substantial amount of Al diffusion from the second metal layer 14 into the first metal layer 13 is greater in the second gate electrode 16b than in the first gate electrode 16a, and the heating temperature is also the second gate. The electrode 16b is higher.

Thereby, when the Al concentration is compared, the first metal layer 13 in the second gate electrode 16b is higher than the first metal layer 13 in the first gate electrode 16a. As a result, the work function of the second gate electrode 16b in which a large amount of Al is diffused with respect to the silicon substrate 1 is smaller than the work function of the first gate electrode 16a with respect to the silicon substrate 1. Thus, the second threshold voltage of the MOS transistor _{T 2} are, higher than the first threshold voltage of the NMOS transistor _{T 1,} a plurality of the NMOS transistors _T 1, _{T 2} identical with the metal gate of the different threshold voltages It can be formed on the silicon substrate 1. Even if Al element is diffused from the second metal layer 14 to the third metal layer 15 by lamp annealing, the work function of the gate electrodes 16a and 16b is hardly affected because it is located far from the silicon substrate 1.

  Next, as illustrated in the cross-sectional view of FIG. 7B and the plan view of FIG. 11B, the second layer is formed on the first gate electrode 16a, the insulating film 18, the interlayer insulating film 11, and the like. An interlayer insulating film 19, for example, a silicon oxide film is formed.

Thereafter, as illustrated in FIGS. 7C and 11C, the first and second gate electrodes 16a and 16b and the source / drain regions in the first and _second NMOS transistors T ₁ and T ₂ are illustrated. Contact holes 19a to 19f are formed on each of 9a to 9d. Thereafter, conductive plugs 20a to 20d are formed in the contact holes 19a to 19f. The conductive plugs 20a to 20d are formed from, for example, a laminated structure of Ti / TiN / W. Thereafter, although not particularly shown, wirings (not shown) connected to the respective conductive plugs 20a to 20d are formed on the second-layer interlayer insulating film 19. Furthermore, a multilayer wiring structure (not shown) is formed by repeatedly forming interlayer insulating films, conductive plugs, wirings, and the like.

  According to the above-described embodiment, a part of the third metal layer 15 of the second gate electrode 16b is selectively etched out of the same metal laminated structure constituting the first and second gate electrodes 16a and 16b. This reduces the heat capacity. For this reason, the time for the heat from the lamp annealing from above to propagate through the third metal layer 15 and reach the first and second metal layers 13 and 14 is greater for the second gate electrode 16b than for the first gate electrode 16a. Get faster. The heating temperature of the first and second metal films 13 and 14 is higher in the second gate electrode 16b than in the first gate electrode 16a.

  As a result, the amount of Al element diffused from the second metal film 14 is greater in the first metal layer 13 of the second gate electrode 16b than in the first metal layer 13 of the first gate electrode 16a. . Further, since the heat remaining in the third metal layer 15 at the end of the lamp annealing is released to the outside from the upper surfaces thereof, the heating of the first and second gate electrodes 16a and 16b is almost completed.

By such a method, the work function of the second gate electrode 16b having a large amount of Al diffusion into the first metal layer 13 becomes smaller than the work function of the first gate electrode 16a having a small amount of Al diffusion. Thus, the second threshold voltage of the NMOS transistor _{T 2} are, higher than the first threshold voltage of the NMOS transistor _{T 1.}

  Therefore, even if the TiAl layer serving as the second metal layer 14 in each of the first and second gate electrodes 16a and 16b is formed to have the same thickness, the amount of Al diffusion therefrom can be made different. In addition, even after the periphery of the first and second gate electrodes 16a and 16b is covered with the interlayer insulating film 11, the interlayer insulating film 11 and the silicon oxide film 18 are transmitted to perform lamp annealing. The work functions of the first and second gate electrodes 16a and 16b can be made different without being affected by the above.

  By the way, in order to make the annealing temperatures of the first and second gate electrodes 16a and 16b different, the first gate electrode 16a is covered with a metal mask while the height of the third metal layer 15 is the same, and the second A method of exposing the gate electrode 16b may be employed. However, according to such a method, when the position of the lamp irradiation direction or the metal mask is misaligned, the light irradiation distribution to the second gate electrode 16b varies due to a change in the shadow under the metal mask, and the work is performed. Function adjustment tends to be uneven. On the other hand, if the film thickness of the first and second gate electrodes 16a and 16b is adjusted as described above, a shadow phenomenon due to the metal mask does not occur even if a deviation occurs in the lamp irradiation direction. The work function of the second gate electrode 16b can be adjusted uniformly.

  By the way, the Al concentration distribution in the TiAl second metal layer 14 may be changed in the thickness direction. For example, in the TiAl second metal layer 14, the lower Al concentration near the first metal layer 13 may be lower than the far upper Al concentration. As a result, the first gate electrode 16a having a low heating effect by lamp annealing reduces the amount of Al diffusion into the first metal layer 13, but the second gate electrode 16a having a high heating effect reduces the Al diffusion to the first metal layer 13. The amount of diffusion can be increased. Therefore, the same effect can be obtained by making the thickness of the TiAl layer in the first gate electrode 16a thinner than the thickness of the second gate electrode 16b.

(Second Embodiment)
FIG. 12 is a perspective view showing the basic structure of the semiconductor device formed according to the present embodiment. FIGS. 13 to 17 and FIG. 18A are cross-sectional views showing the steps of forming the semiconductor device according to the present embodiment. 19 to 21 and FIG. 18B are plan views thereof.

First and second fin-type NMOS transistors T ₁₁ and T ₁₂ are formed on the silicon substrate 21 shown in FIG. In the first fin-type NMOS transistor T ₁₁ , the gate insulating film 32 is disposed on the front, top, and rear surfaces of the region between the source / drain regions 29 a and 29 b of the portion protruding in a fin shape from the silicon substrate 21. A first gate electrode 36a is formed. In the second fin type NMOS transistor T _12, the source / drain region 29c of the portion protruding from the silicon substrate 21 in the fin-shaped, the front face of the region between the 29d, a top surface, a gate insulating film 32 on the rear face A second gate electrode 36b is formed therethrough. The second gate electrode 36b is formed thinner than the first gate electrode 36a. A manufacturing process of the first and second fin type NMOS transistors T ₁₁ and T ₁₂ having such a basic structure will be described next.

First, a semiconductor device forming process according to the second embodiment is performed on a silicon substrate 21 as illustrated in a plan view of FIG. 19A and a cross section taken along line II-II in FIG. A silicon oxide film 22 and a silicon nitride film 23 are formed by, for example, a CVD method. Thereafter, a photoresist is applied on the silicon nitride film 23. Subsequently, by exposing and developing the photoresist, a resist pattern R ₁₁ that covers the first and second fin forming regions A ₁₁ and A ₁₂ and exposes the periphery thereof is formed. The first and second fin forming regions A ₁₁ , A ₁₂ are, for example, rectangular with a flat plane, and the short sides thereof are the distance between the pair of source / drain regions 29a-29d formed on each, that is, the gate. It is preferable that the length is shorter than the length. Note that a plurality of first and second fin formation regions A ₁₁ and A ₁₂ are arranged although not particularly shown.

Next, FIG. 13 (b), the as shown in FIG. 19 (b), a resist pattern _{R 11} used as a mask, the silicon nitride film 3, a silicon oxide film 22 is etched. Thereafter, dry etching using the resist pattern R ₁₁ and silicon nitride film 23 left on the mask, the silicon substrate 1 are etched by RIE using a chlorine-based gas. Thus, as illustrated in FIG. 13C, the first and second fin formation regions A ₁₁ and A ₁₂ of the silicon substrate 21 are projected in a fin shape, and an element isolation groove 21a is formed around the first and second fin formation regions A ₁₁ and A _12. . Thereafter, the silicon nitride film 23 and the silicon oxide film 22 are removed by wet etching using, for example, buffered hydrofluoric acid.

Next, an insulating film such as a silicon oxide film is formed by CVD on the upper surface of the first and second fin formation regions A ₁₁ and A ₁₂ and on the inner surface of the element isolation groove 21a on the silicon substrate 21 to separate the elements. The groove 21a is completely filled with an insulating film. Thereafter, as illustrated in FIGS. 14A and 19C, the insulating film is removed from the first and second fin formation regions A ₁₁ and A ₁₂ of the silicon substrate 21 by the CMP method. The insulating film left in the element isolation trench 21 a is used as the element isolation insulating film 24. Incidentally, the insulating film filling the element isolation trench 21a may be formed before the silicon nitride film 23 is removed. In this case, the insulating film is polished by the CMP method to expose the silicon nitride film 23, and then the silicon nitride film 23 is removed. Thereafter, the silicon oxide film 22 on the upper surface of the silicon substrate 21 is removed.

Next, a first conductivity type first and second well 25a is formed by ion-implanting a first conductivity type impurity, for example, a p-type impurity such as boron, into the first and second fin formation regions A ₁₁ and A ₁₂ . , 25b. Thereafter, as illustrated in FIG. 14B, the element isolation insulating film 24 in the element isolation trench 21 a is etched, whereby the first and second fin formation regions A ₁₁ , A of the silicon substrate 21 are etched. ₁₂ is projected from the element isolation insulating film 24 in a fin shape. The first and second wells 25a and 25b may be formed after protruding the active region.

Next, as illustrated in FIG. 14C, a polysilicon film 26 is formed on the silicon substrate 21 and the element isolation insulating film 24 to a thickness of, for example, 30 nm to 60 nm by the CVD method. Further, a photoresist is applied on the polysilicon film 26, and this is exposed, developed, and the like, thereby crossing the centers of the first and second wells 25a, 25b protruding in the fin shape in the silicon substrate 21. forming a resist pattern R ₁₂ of the gate electrode shape.

Next, a resist pattern R ₁₂ as a mask to etch the polysilicon film 26 for example, RIE method, first fin-shaped, second well 25a, the gate electrode shape of the polysilicon film 26 which substantially crosses the center of the 25b To do. Thereafter, the resist pattern is removed _{R 12.} The gate electrode-shaped polysilicon film 26 is used as first and second dummy gates 26a and 26b as illustrated in FIG. The first and second dummy gates 26a and 26b are patterned so that each width is 15 nm to 25 nm.

Next, using the first and second dummy gates 26a and 26b as masks, a second conductivity type impurity such as arsenic or phosphorus is applied to the first and second transistor formation regions A ₁ and A ₂ of the silicon substrate 1. Ion implantation. Thus, as illustrated in FIG. 15A, extension regions 28a to 28d having low impurity concentrations are formed on both sides of the first and second dummy gates 26a and 26b.

  Next, for example, a silicon nitride film 27 is formed as an insulating film on the silicon substrate 21 and the first and second dummy gates 26a and 26b. Thereafter, the silicon nitride film is etched back to leave the silicon nitride film on the side surfaces of the first and second dummy gates 26a and 26b as illustrated in the plan view of FIG. Silicon films are used as insulating sidewalls 27a and 27b.

  Next, as illustrated in the cross-sectional view of FIG. 15B, the first and second dummy gates 26a and 26b and the sidewalls 27a and 27b of the fin-like first and second wells 25a and 25b are formed. A second conductivity type impurity is ion-implanted on both sides of each of the included regions. Thus, second conductivity type impurity diffusion regions 28e to 28h are formed. The impurity diffusion regions 28e to 28h overlap the extension regions 28a to 28d on both sides of each of the first and second dummy gates 26a and 26b, and have a higher second conductivity type impurity concentration than the extension regions 28a to 28d. It is formed. Accordingly, the extension regions 28a to 28d and the impurity diffusion regions 28e to 28h connected to each other on both sides of the first and second dummy gates 26a and 26b become the second conductivity type source / drain regions 29a to 29d, respectively.

  Next, a silicon oxide film is formed as an interlayer insulating film 31 on the surfaces of the first and second dummy gates 26a and 26b, the sidewalls 27a and 27b, and the fin-like first and second wells 25a and 25b by plasma CVD. To form. Thereafter, as illustrated in the cross-sectional view of FIG. 15C and the plan view of FIG. 20C, the upper surface of the silicon oxide film 31 is polished by CMP to flatten the upper surface, and the first, The upper surfaces of the second dummy gates 26a and 26b are exposed. In this case, the upper ends of the sidewalls 27a and 27b are also exposed.

  Next, as illustrated in the cross-sectional view of FIG. 16A and the plan view of FIG. 21A, the first and second dummy gates 26a and 26b are selectively removed to thereby remove the interlayer insulating film 31. First and second gate-shaped recesses 30a and 30b are formed.

  Next, as illustrated in FIG. 16B, on the fin-like active regions in the first and second gate-shaped recesses 30 a and 30 b, on the element isolation insulating film 24, and between the layers of the silicon substrate 21. A high-k dielectric layer, such as a hafnium oxide layer, is formed as the gate insulating film 32 on the upper surface of the insulating film 11. Subsequently, a TiN layer is formed as a first metal layer 33 on the gate insulating film 32 by a sputtering method, for example, to a thickness of 1 nm to 3 nm, for example. Further, a TiAl layer, for example, is formed as a second metal layer 34 on the first metal layer 33 to a thickness of 2 nmn to 5 nm, for example, by sputtering.

  The first metal layer 33 and the second metal layer 34 become part of a gate electrode described later. The second metal layer 34 is formed of a work function adjusting metal (work function metal) such as TiAl, and is formed of a material different from that of the first metal layer 33. That is, the second metal layer 34 thermally diffuses the work function adjusting metal element contained therein, for example, Al, into the first metal layer 33 close to the substrate, thereby reducing the work function of the gate electrode, that is, the threshold voltage of the MOS transistor. It has a function to adjust.

  Further, a tungsten layer, for example, is formed as a third metal layer 35 on the second metal layer 34 by sputtering so as to have a thickness that completely fills at least the first and second gate-shaped recesses 30a and 30b. . The third metal layer 35 is formed from a material different from that of the second metal layer 34.

  Next, as illustrated in the plan view of FIG. 21B, the gate insulating film 32 and the first to third metal layers 33 to 35 on the interlayer insulating film 31 are removed by a CMP method. Thus, the first to third metal layers 33 to 35 left in the first and second gate-shaped recesses 30a and 30b are used as the first and second gate electrodes 36a and 36b, respectively.

  Next, steps required until a structure shown in a sectional view in FIG. First, a silicon oxide film 37 is formed as an insulating film on the interlayer insulating film 31 and the first and second gate electrodes 36a and 36b, for example, by the CVD method. After that, the silicon oxide film 37 is patterned using photolithography and etching to form an opening 37a that exposes the upper surface of the second gate electrode 36b and to cover the first gate electrode 36a.

Next, the silicon substrate 21 is placed in the etching chamber of the RIE apparatus, and the pressure is set to 1 Pa to 100 Pa. In the etching chamber, a high frequency power source applied to the electrode is set to a frequency of 13.56 MHz, for example, a chlorine-based gas, for example, chlorine (Cl ₂ ) is introduced as a reaction gas, and the temperature of the silicon substrate 21 is set to, for example, about 100 ° C. Set to.

  Thereby, as illustrated in the cross-sectional view of FIG. 17A, the interlayer insulating film 31 and the silicon oxide film 37 thereon are used as a mask, and the second gate electrode 36b exposed from the opening 37a is viewed from above. Etching is performed to reduce the height to, for example, about 30 nm. As a result, a space is formed above the second gate-shaped recess 30b. In this case, the thickness of each of the fin-like active region of the silicon substrate 21 and the gate insulating film 32, the first metal layer 33, and the second metal layer 34 formed along the upper surface of the element isolation insulating film 24 varies. There is no. However, the third metal layer 35 formed on the second metal layer 34 in the second gate electrode 36b is thinner than the third metal layer 35 of the first gate electrode 36a. As a result, the volume of the third metal layer 35 of the second gate electrode 36b becomes smaller than the volume of the third metal layer 35 of the first gate electrode 6a. FIG. 12 is a perspective view showing a state in which the sidewalls 27a and 27b, the interlayer insulating film 31, and the silicon oxide film 37 are omitted in FIG.

The first source / drain region 29a of both sides thereof with the gate electrode 36a formed by the above, a first fin-type NMOS transistor _{T 11} is formed by 29b, etc., also, the both sides and the second gate electrode 36b source / drain regions 29c, the second fin type NMOS transistor _{T 12} is formed by a 29d.

  Next, a silicon oxide film 38 is formed as a separate insulating film on the silicon oxide film 37 and in the opening 37a by the CVD method. As a result, in the second gate-shaped recess 30b, the space formed on the second gate electrode 36b is filled with the silicon oxide film 38. Thereafter, as illustrated in the cross-sectional view of FIG. 17B and the plan view of FIG. 21C, the silicon oxide films 37 and 38 are polished from the upper surface by CMP, and the upper surface of the first gate electrode 36a is polished. Expose. As a result, the silicon oxide films 37 and 38 on the upper surface of the interlayer insulating film 31 are removed, and the silicon oxide film 38 on the second gate electrode 36b is left in the second gate-shaped recess 30b. It flattens with the upper surface of 31.

  Next, the silicon substrate 21 is transported into a lamp annealing apparatus, in which lamp annealing is performed by a lamp (not shown) disposed above the silicon substrate 21 as illustrated in FIG. As the ramp annealing, there are RTA, FLA and the like shown in the first embodiment. As annealing conditions, the first and second gate electrodes 36a and 36b are heated at 400 ° C. to 900 ° C. for about 1 second to 10 seconds, for example.

According to such conditions, as in the first embodiment, the substantial Al diffusion time from the second metal layer 34 into the first metal layer 33 is the same as that of the second gate electrode 36b. It becomes longer than the gate electrode 36a, and the heating temperature is higher in the second gate electrode 36b. Accordingly, when the Al concentration is compared, the first metal layer 33 in the second gate electrode 36b is higher than the first metal layer 33 in the first gate electrode 36a. As a result, the work function of the second gate electrode 36b for the second well 25b is smaller than the work function of the first gate electrode 36a for the first well 25a. Thus, the threshold voltage of the second MOS transistor _{T 12} is higher than the threshold voltage of the first NMOS transistor _{T 11,} the same plurality of the fin type NMOS transistor _{T 12, T 12} having a metal gate of the different threshold voltages It can be formed on the silicon substrate 1. Even if Al element is diffused from the second metal layer 34 to the third metal layer 35 by the lamp annealing, the work function of the gate electrodes 36a and 36b is almost equal because it is separated from the first metal layer 31 from the silicon substrate 21. Has no effect.

Next, steps required until a structure exemplified in the cross-sectional views and plan views in FIGS. First, a second interlayer insulating film 39 is formed on the first gate electrode 36a, the insulating film 38, the interlayer insulating film 31, and the like. Thereafter, contact holes 39a to 39f are formed on the first and second gate electrodes 36a and 36b and the source / drain regions 29a to 29d in the first and second fin-type NMOS transistors T ₁₁ and T ₁₂ , respectively. To do. Thereafter, conductive plugs 40a to 40d are formed in the contact holes 39a to 39f. The conductive plugs 40a to 40d are formed, for example, from a laminated structure of Ti / TiN / W. Thereafter, although not particularly shown, wiring (not shown) connected to each of the conductive plugs 40 a to 40 d is formed on the second-layer interlayer insulating film 39. Furthermore, a multilayer wiring structure (not shown) is formed by repeatedly forming interlayer insulating films, conductive plugs, wirings, and the like.

  According to the present embodiment, the first gate electrode 36a is formed by etching the third metal layer 35 of the second gate electrode 36b in the same metal laminated structure constituting the first and second gate electrodes 36a and 36b. The third metal layer 35 is made thinner. For this reason, as in the first embodiment, the heat capacity of the second gate electrode 36b is smaller than the heat capacity of the first gate electrode 36a. Therefore, the heating temperature by lamp annealing is higher in the second gate electrode 36b. Higher than the gate electrode 36a. In this case, the thickness in the width direction of the third metal layer 25 does not change before and after the first and second wells 25a and 25b protruding in the fin shape in the silicon substrate 21, but the thickness in the height direction is not changed. Can be different.

By such a method, the work function of the second gate electrode 36b having a large amount of Al diffusion into the first metal layer 33 becomes smaller than the work function of the first gate electrode 36a having a small amount of Al diffusion. Thus, the threshold voltage of the second fin type NMOS transistor _{T 12} is higher than the threshold voltage of the first fin type NMOS transistor _{T 11.}

  Accordingly, lamp annealing is simultaneously performed from above without changing the thickness of the TiAl second metal layer 14 in each of the plurality of gate electrodes 36a and 36b on the same substrate, and the work functions of the plurality of gate electrodes 36a and 36b are different. Can be made. In addition, even when the periphery of the plurality of gate electrodes 36a and 36b is covered with the interlayer insulating film 11 and the silicon oxide film 38, lamp annealing is performed with light having a wavelength that transmits the gate electrodes 36a and 36b. it can.

  Further, according to the present embodiment, as in the first embodiment, the work function can be adjusted more uniformly than in the case where the first gate electrode 16a is covered with a metal mask that generates shadows.

In the second gate-shaped recess 30b of the interlayer insulating film 31, the upper surface of the second gate electrode 36b is covered with an insulating film 38. The insulating film 38 is excellent in light transmittance for RTA and FLA. Yes. Therefore, lamp annealing may be performed without covering the upper surface of the second gate electrode 36b with the silicon oxide film 18. Further, the Al concentration distribution in the TiAl second metal layer 34 may be uniform, but the Al concentration distribution in the thickness direction may be changed as in the first embodiment.
In the first and second embodiments, the number of stacked metals of the gate electrodes 16a, 16b, 36a, and 36b may be more than three. In this case, the metal layer containing the work function metal from the first metal layer. The thickness distribution of each layer may be formed uniformly.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, an embodiment of the present invention will be additionally described.
(Supplementary Note 1) Forming a first dummy gate on a first region of a semiconductor substrate and forming a second dummy gate on a second region; and the first dummy gate in the first region of the semiconductor substrate Forming a first pair of source / drain regions on both sides of the semiconductor substrate, and forming a second pair of source / drain regions on both sides of the second dummy gate in the second region of the semiconductor substrate. A step of forming a first insulating film around each of the first dummy gate and the second dummy gate; removing the first dummy gate and the second dummy gate; Forming a recess in the first insulating film; forming a gate insulating film on an inner surface of the first recess; an inner surface of the second recess; and the first insulating film; and Forming a first metal layer on the Forming a second metal layer containing a work function metal on the first metal layer and different from the first metal layer; and a third different from the second metal layer on the second metal film layer. Forming a metal layer; removing the first metal layer, the second metal layer, and the third metal layer from the first insulating film and leaving them in the first recess and the second recess; The first gate electrode having the three metal layers having different thicknesses, the step of forming a first gate electrode and a second gate electrode, the step of selectively thinning the third metal layer in the second recess, respectively. And a step of lamp annealing the second gate electrode and diffusing the work function metal from the second metal layer to the first metal layer in the second gate electrode. Production method.
(Appendix 2) A step of forming a second insulating film that transmits light of the lamp annealing on the third metal layer in the second recess after the third metal layer in the second recess is thinned. 2. A method of manufacturing a semiconductor device according to appendix 1, wherein:
(Supplementary note 3) The method for manufacturing a semiconductor device according to supplementary note 1 or 2, wherein the work function metal is aluminum.
(Supplementary note 4) In any one of Supplementary notes 1 to 3, wherein the first metal layer is a titanium nitride layer, the second metal layer is an aluminum nitride layer, and the third metal storage layer is a tungsten layer. The manufacturing method of the semiconductor device of description.
(Additional remark 5) Each said 2nd metal layer in said 1st gate electrode and said 2nd gate electrode is formed in the same thickness, Any one of Additional remark 1 thru | or Additional remark 4 characterized by the above-mentioned. Semiconductor device manufacturing method.
(Supplementary note 6) The semiconductor device manufacturing according to any one of supplementary notes 1 to 6, wherein the concentration of the work function metal in the second metal layer increases as the distance from the first metal layer increases. Method.
(Supplementary note 7) The first region and the second region of the semiconductor substrate have a fin shape, a first dummy gate is formed on the upper surface, the front surface, and the rear surface of the first region, and the second region The method of manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein a second dummy gate is formed on the upper surface, the front surface, and the rear surface.
(Supplementary note 8) The semiconductor according to any one of supplementary notes 1 to 7, further comprising a step of forming an element isolation insulating film around the first region and the second region of the semiconductor substrate. Device manufacturing method.
(Supplementary note 9) The method of manufacturing a semiconductor device according to any one of supplementary notes 1 to 8, wherein the lamp annealing is one of rapid thermal annealing and flash lamp annealing.
(Supplementary note 10) The supplementary notes 1 to 9, wherein the third metal layer in the second gate electrode is thinned to at least half of the thickness of the third metal layer in the first gate electrode. A method for manufacturing a semiconductor device according to any one of the above.
(Additional remark 11) The 1st laminated structure which has the 1st metal layer formed through the gate insulating film on the 1st field among semiconductor substrates, the 2nd metal layer containing a work function metal, and the 3rd metal layer A first gate electrode and a first layer of a stacked structure including the first metal layer, the second metal layer, and the third metal layer formed on a second region of the semiconductor substrate via a gate insulating film. The third metal layer in the second gate electrode is thinner than the third metal layer in the first gate electrode, and the first metal layer in the second gate electrode. The concentration of the work function metal in the semiconductor device is higher than the concentration of the work function metal in the first metal layer in the first gate electrode.
(Supplementary Note 12) The first region and the second region of the semiconductor substrate have a fin shape, and the first gate electrode is formed on the upper surface, the front surface, and the rear surface of the first region, and the second region The semiconductor device according to appendix 11, wherein a second gate electrode is formed on the upper surface, the front surface, and the rear surface of the semiconductor device.

1, 21 Silicon substrate 4, 24 Element isolation insulating film 5a, 5b, 25a, 25b Well 6a, 6b, 16a, 16b Dummy gate 7a, 7b, 17a, 17b Side wall 9a, 9b, 9c, 9d Source / drain region 10a 10b, 30a, 30b Recess 11, 31 Interlayer insulating film 12, 32 Gate insulating film 13, 33 First metal layer 14, 34 Second metal layer 15, 35 Third metal layer 16a, 16b, 36a, 36b Gate electrode 17 18 Silicon oxide films 20a-20f, 40a-40f Conductive plugs

Claims (5)

Forming a first dummy gate on the first region and a second dummy gate on the second region of the semiconductor substrate;
Forming a first pair of source / drain regions on both sides of the first dummy gate in the first region of the semiconductor substrate;
Forming a second pair of source / drain regions on both sides of the second dummy gate in the second region of the semiconductor substrate;
Forming a first insulating film around each of the first dummy gate and the second dummy gate;
Removing the first dummy gate and the second dummy gate to form a first recess and a second recess in the first insulating film;
Forming a gate insulating film on the inner surface of the first recess, the inner surface of the second recess, and the first insulating film;
Forming a first metal layer on the gate insulating film;
Forming a second metal layer containing a work function metal and different from the first metal layer on the first metal layer;
Forming a third metal layer different from the second metal layer on the second metal film layer;
The first metal layer, the second metal layer, and the third metal layer are removed from the first insulating film and left in the first recess and the second recess, respectively. Forming a gate electrode;
Selectively thinning the third metal layer in the second recess;
The first gate electrode and the second gate electrode having the three metal layers having different thicknesses are subjected to lamp annealing, and the work function metal is transferred from the second metal layer to the first metal layer in the second gate electrode. A diffusion step;
A method for manufacturing a semiconductor device, comprising:   And forming a second insulating film that transmits light of the lamp annealing on the third metal layer in the second recess after the third metal layer in the second recess is thinned. A method for manufacturing a semiconductor device according to claim 1.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal layer in each of the first gate electrode and the second gate electrode is formed to have the same thickness.   The first region and the second region of the semiconductor substrate have a fin shape, a first dummy gate is formed on the upper surface, the front surface, and the rear surface of the first region, and the upper surface and the front surface of the second region. The method of manufacturing a semiconductor device according to claim 1, wherein a second dummy gate is formed on the rear surface. A first gate having a first stacked structure including a first metal layer formed on a first region of a semiconductor substrate via a gate insulating film, a second metal layer containing a work function metal, and a third metal layer. Electrodes,
A second gate electrode having a stacked structure including the first metal layer, the second metal layer, and the third metal layer formed on a second region of the semiconductor substrate via a gate insulating film; And
The third metal layer in the second gate electrode is thinner than the third metal layer in the first gate electrode;
A concentration of the work function metal in the first metal layer in the second gate electrode is higher than a concentration of the work function metal in the first metal layer in the first gate electrode;
A semiconductor device.

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