SG10201803316YA - Three-dimensional semiconductor device - Google Patents
Three-dimensional semiconductor deviceInfo
- Publication number
- SG10201803316YA SG10201803316YA SG10201803316YA SG10201803316YA SG10201803316YA SG 10201803316Y A SG10201803316Y A SG 10201803316YA SG 10201803316Y A SG10201803316Y A SG 10201803316YA SG 10201803316Y A SG10201803316Y A SG 10201803316YA SG 10201803316Y A SG10201803316Y A SG 10201803316YA
- Authority
- SG
- Singapore
- Prior art keywords
- region
- electrode
- semiconductor device
- stacked structure
- dimensional semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000002955 isolation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
OF THE DISCLOSURE A three-dimensional semiconductor device includes: a substrate having a cell array region and a contact region; a stacked structure including a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region; vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string; and word line contact plugs, each penetrating an uppermost electrode among the plurality of electrodes in a region of each of tread portions of the stacked structure having the stepwise structure, being connected to another electrode under the penetrated uppermost electrode, and being electrically insulated from the penetrated uppermost electrode. FIG. 36
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170094960A KR102423766B1 (en) | 2017-07-26 | 2017-07-26 | Three dimensional semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201803316YA true SG10201803316YA (en) | 2019-02-27 |
Family
ID=65038763
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201803316YA SG10201803316YA (en) | 2017-07-26 | 2018-04-20 | Three-dimensional semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (2) | US10396035B2 (en) |
KR (1) | KR102423766B1 (en) |
CN (1) | CN109309095B (en) |
SG (1) | SG10201803316YA (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11765900B2 (en) | 2018-09-21 | 2023-09-19 | Samsung Electronics Co., Ltd. | Vertical-type memory device |
Families Citing this family (30)
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KR102423766B1 (en) * | 2017-07-26 | 2022-07-21 | 삼성전자주식회사 | Three dimensional semiconductor device |
US10777520B2 (en) * | 2017-11-08 | 2020-09-15 | SK Hynix Inc. | Semiconductor memory device |
KR102469334B1 (en) * | 2017-11-08 | 2022-11-23 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
KR102570901B1 (en) * | 2017-11-20 | 2023-08-25 | 삼성전자주식회사 | Three-dimensional semiconductor device |
JP2019160922A (en) * | 2018-03-09 | 2019-09-19 | 東芝メモリ株式会社 | Semiconductor device |
JP2019161042A (en) * | 2018-03-14 | 2019-09-19 | 東芝メモリ株式会社 | Semiconductor device |
KR20200007212A (en) * | 2018-07-12 | 2020-01-22 | 에스케이하이닉스 주식회사 | Semiconductor memry device and method for forming the same |
JP2020136644A (en) * | 2019-02-26 | 2020-08-31 | キオクシア株式会社 | Semiconductor storage device |
CN113035732B (en) * | 2019-06-11 | 2021-12-28 | 长江存储科技有限责任公司 | Three-dimensional memory and method for forming step area of three-dimensional memory |
KR102598774B1 (en) * | 2019-07-03 | 2023-11-07 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
KR20210012336A (en) * | 2019-07-24 | 2021-02-03 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of semiconductor device |
KR20210015422A (en) * | 2019-08-02 | 2021-02-10 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
US11063050B2 (en) * | 2019-09-25 | 2021-07-13 | Nanya Technology Corporation | Semiconductor device with air gaps and method for fabricating the same |
CN112786602B (en) * | 2019-11-06 | 2022-08-26 | 成都锐成芯微科技股份有限公司 | Single-layer polysilicon nonvolatile memory cell and memory thereof |
CN114600243A (en) * | 2019-12-12 | 2022-06-07 | 英特尔公司 | Dummy word line contact to improve etch margin of semi-isolated word lines in a staircase structure |
CN111106116B (en) * | 2020-01-02 | 2022-09-09 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
KR20210092363A (en) * | 2020-01-15 | 2021-07-26 | 삼성전자주식회사 | Three dimensional semiconductor memory device |
CN111640755A (en) * | 2020-03-23 | 2020-09-08 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
WO2021243703A1 (en) * | 2020-06-05 | 2021-12-09 | Yangtze Memory Technologies Co., Ltd. | Staircase structure in three-dimensional memory device and method for forming the same |
EP3953969A4 (en) | 2020-06-05 | 2022-08-03 | Yangtze Memory Technologies Co., Ltd. | Staircase structure in three-dimensional memory device and method for forming the same |
US11404091B2 (en) * | 2020-06-19 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array word line routing |
US11355516B2 (en) | 2020-07-16 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
US11647634B2 (en) | 2020-07-16 | 2023-05-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
US11423966B2 (en) | 2020-07-30 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array staircase structure |
US11715692B2 (en) | 2020-08-11 | 2023-08-01 | Micron Technology, Inc. | Microelectronic devices including conductive rails, and related methods |
US11574870B2 (en) | 2020-08-11 | 2023-02-07 | Micron Technology, Inc. | Microelectronic devices including conductive structures, and related methods |
US11456208B2 (en) * | 2020-08-11 | 2022-09-27 | Micron Technology, Inc. | Methods of forming apparatuses including air gaps between conductive lines and related apparatuses, memory devices, and electronic systems |
JP2022120425A (en) * | 2021-02-05 | 2022-08-18 | キオクシア株式会社 | semiconductor storage device |
US20230073372A1 (en) * | 2021-09-03 | 2023-03-09 | Micron Technology, Inc. | Microelectronic devices including staircase structures, and related memory devices, electronic systems, and methods |
WO2023163740A1 (en) * | 2022-02-28 | 2023-08-31 | Sandisk Technologies Llc | Three-dimensional memory device containing etch-stop structures and self-aligned insulating spacers and method of making the same |
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KR102423766B1 (en) * | 2017-07-26 | 2022-07-21 | 삼성전자주식회사 | Three dimensional semiconductor device |
-
2017
- 2017-07-26 KR KR1020170094960A patent/KR102423766B1/en active IP Right Grant
- 2017-12-27 US US15/855,289 patent/US10396035B2/en active Active
-
2018
- 2018-04-20 SG SG10201803316YA patent/SG10201803316YA/en unknown
- 2018-04-26 CN CN201810386727.6A patent/CN109309095B/en active Active
-
2019
- 2019-07-11 US US16/508,443 patent/US10615124B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11765900B2 (en) | 2018-09-21 | 2023-09-19 | Samsung Electronics Co., Ltd. | Vertical-type memory device |
Also Published As
Publication number | Publication date |
---|---|
US10396035B2 (en) | 2019-08-27 |
US20190035733A1 (en) | 2019-01-31 |
CN109309095B (en) | 2023-07-25 |
CN109309095A (en) | 2019-02-05 |
US10615124B2 (en) | 2020-04-07 |
US20190333855A1 (en) | 2019-10-31 |
KR102423766B1 (en) | 2022-07-21 |
KR20190012061A (en) | 2019-02-08 |
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