CN111640755A - Memory and forming method thereof - Google Patents

Memory and forming method thereof Download PDF

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Publication number
CN111640755A
CN111640755A CN202010208500.XA CN202010208500A CN111640755A CN 111640755 A CN111640755 A CN 111640755A CN 202010208500 A CN202010208500 A CN 202010208500A CN 111640755 A CN111640755 A CN 111640755A
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CN
China
Prior art keywords
word line
memory
contact plug
substrate
word lines
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Pending
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CN202010208500.XA
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Chinese (zh)
Inventor
赖惠先
童宇诚
林昭维
朱家仪
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Fujian Jinhua Integrated Circuit Co Ltd
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Fujian Jinhua Integrated Circuit Co Ltd
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Priority to CN202010208500.XA priority Critical patent/CN111640755A/en
Publication of CN111640755A publication Critical patent/CN111640755A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Abstract

The invention provides a memory and a forming method thereof. End portions of the word lines are extended into the peripheral region, and contact plugs are formed in the peripheral region to be electrically connected to the end portions of the word lines. Therefore, the space of the peripheral area can be fully utilized, the contact plugs are prepared in the peripheral area, the size of each contact plug is increased, the preparation difficulty of the contact plugs is effectively reduced, and the connection performance between the contact plugs and the word lines is correspondingly improved.

Description

Memory and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.
Background
A Memory (e.g., a Dynamic Random Access Memory) generally has a Memory cell array including a plurality of Memory cells arranged in an array. And the memory also comprises a plurality of word lines, and each word line is electrically connected with the corresponding memory unit respectively so as to apply corresponding signals to each memory unit.
In addition, for each word line, it is usually necessary to form a corresponding contact plug to electrically extract each word line. However, as the size of semiconductor devices is continuously reduced and the density of integrated circuits is increased, the size of contact plugs is also reduced, and the difficulty of fabricating the contact plugs is increased accordingly.
Disclosure of Invention
The present invention is directed to a memory device, which improves the process window of a contact plug connected to a word line and improves the quality of the contact plug connected to the word line.
To solve the above technical problem, the present invention provides a memory, including:
the substrate is provided with a memory area and a peripheral area, and the peripheral area is positioned at the periphery of the memory area;
a plurality of word lines buried in the substrate, and formed in the memory region and extending into the peripheral region such that ends of the word lines are located in the peripheral region; and the number of the first and second groups,
a contact plug formed in the peripheral region, and a bottom of the contact plug extending into the substrate to be electrically connected to an end of the word line.
Optionally, the word line has a first end and a second end opposite to each other, and the first end and the second end of the word line are respectively located in the peripheral region on two opposite sides of the memory region; and in two adjacent word lines, a contact plug connected with one of the word lines is formed on the first end portion, and a contact plug connected with the other word line is formed on the second end portion.
Optionally, the word line is formed in a word line trench of the substrate, and a top of the word line is lower than a top of the word line trench; and the memory also comprises a shielding layer, the shielding layer is filled in the space above the word line groove and higher than the word line, and the contact plug also penetrates through the shielding layer to extend to the word line.
Optionally, a dielectric layer is further formed on the substrate in the peripheral region, and the contact plug penetrates through the dielectric layer to extend into the substrate.
Optionally, the width of the upper contact portion in the dielectric layer in the contact plug is greater than the width of the lower contact portion in the substrate in the contact plug.
Optionally, the substrate in the peripheral region includes a base, and a first insulating layer, a second insulating layer, and a third insulating layer sequentially formed on the base, and the end of the word line extends in the third insulating layer.
Optionally, a width dimension of the contact plug is greater than a width dimension of the word line.
The present invention also provides another memory comprising:
the substrate is provided with a memory area and a peripheral area, and the peripheral area is positioned at the periphery of the memory area;
m word lines buried in the substrate, the M word lines being sequentially arranged along a predetermined direction, M being a positive integer greater than 1, the word lines being located in the memory region and extending into the peripheral region, and the word lines having opposite first and second ends, the first and second ends of the word lines being located in the peripheral region on opposite sides of the memory region, respectively;
a contact plug formed in the peripheral region, and a bottom of the contact plug extending into the substrate to be electrically connected to an end of the word line;
the contact plug connected with the Nth word line is formed on the second end part of the word line, the contact plug connected with the (N-1) th word line and the contact plug connected with the (N + 1) th word line are formed on the first end part of the word line, the contact plug connected with the (N-1) th word line and the contact plug connected with the (N + 1) th word line are staggered in the arrangement direction of the word lines, and N is a positive integer larger than 1 and smaller than M.
Based on the memory, the invention also provides a forming method of the memory, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a memory area and a peripheral area, and the peripheral area is positioned at the periphery of the memory area;
forming a plurality of word lines in the substrate, the word lines being formed in the memory region and extending into the peripheral region such that ends of the word lines are located in the peripheral region;
forming a contact plug formed in the peripheral region, a bottom of the contact plug extending into the substrate to be electrically connected to an end of the word line.
Optionally, the word line is formed in a word line trench of the substrate, and a top of the word line is lower than a top of the word line trench; after the word lines are formed, filling a shielding layer in the space above the word line grooves and higher than the word lines, and at least forming a dielectric layer on the substrate in the peripheral area;
and, the method of forming the contact plug includes: and sequentially etching the dielectric layer and the shielding layer to expose the word line, forming a contact window, and filling a conductive material in the contact window to form the contact plug.
In the memory provided by the invention, the word lines further extend from the memory area to the peripheral area, so that the contact plugs can be formed in the peripheral area to be electrically connected with the corresponding word lines. Because the contact plugs are formed in the peripheral area which is relatively open, on one hand, the space of the peripheral area can be fully utilized, the extra occupied space in the memory area is avoided, on the other hand, the size of each contact plug is favorably increased, the preparation difficulty of the contact plug is effectively reduced, and the connection performance between the contact plug and the word line can be favorably improved.
Furthermore, two contact plugs connecting two adjacent word lines can be distributed and formed on different sides of the memory region, so that the space between the adjacent contact plugs can be further increased, and the process window of the contact plugs can be increased to a greater extent.
Drawings
Fig. 1 is a layout structure of a memory according to a first embodiment of the present invention;
FIG. 2a is a cross-sectional view of the memory shown in FIG. 1 in the direction aa';
FIG. 2b is another cross-sectional view of the memory shown in FIG. 1 in the direction aa';
fig. 3 is a layout structure of a memory according to a second embodiment of the present invention;
FIG. 4 is a flow chart illustrating a method for forming a memory according to an embodiment of the invention;
wherein the reference numbers are as follows:
100-a substrate;
110-a substrate;
120-a first insulating layer;
130-a second insulating layer;
140-a third insulating layer;
100A-memory region;
100B-peripheral zone;
200-word line;
200 a-word line trench;
300/300' -contact plugs;
310-a first conductive layer;
320-a second conductive layer;
400-a shielding layer;
500-a dielectric layer;
AA-active region;
h1 — first height position;
h2-second elevation position.
Detailed Description
The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 1 is a layout structure of a memory according to a first embodiment of the present invention, and fig. 2a is a schematic cross-sectional view of the memory shown in fig. 1 in the aa' direction according to the first embodiment of the present invention.
As shown in fig. 1 and fig. 2a, the memory in this embodiment includes: a substrate 100; a plurality of word lines 200 buried in the substrate 100; and a contact plug 300 electrically connected to the word line 200.
The substrate 100 has a memory area 100A and a peripheral area 100B, and the peripheral area 100B is located at the periphery of the memory area 100A. And a plurality of active areas AA are formed in the memory area 100A of the substrate 100, and are arranged in an array to form a memory cell array.
With continued reference to fig. 1, a plurality of the word lines 200 are sequentially arranged along a first direction (X direction), and each of the word lines 200 extends along a second direction (Y direction). Specifically, the word lines 200 are formed in the memory region 100A and extend into the peripheral region 100B, so that the ends of the word lines 200 are located in the peripheral region 100B. Further, the word line 200 intersects the corresponding active area AA in the memory area 100A for applying an electrical signal to the corresponding memory cell.
And the end of the word line 200 extends into the peripheral region 100B, so that the electrical extraction of the word line 200 can be realized through the end of the word line 200. Specifically, a contact plug 300 electrically connected to the word line 200 for applying an electrical signal to the word line 200 may be formed in the peripheral region 100B so as to be electrically connected to an end of the word line 200.
It should be noted that, since the contact plugs 300 may be formed in the peripheral region 100B, a larger preparation space may be provided for the contact plugs 300, on one hand, the space of the peripheral region 100B is effectively utilized; on the other hand, the size of the contact plug 300 is increased, so that the contact area between the contact plug 300 and the word line 200 is increased; in addition, the process window of the contact plug 300 can be increased, and the precision of the formed contact plug 300 can be improved.
Further, the word line 200 has a first end portion and a second end portion opposite to each other, and the first end portion and the second end portion of the word line 200 extend to the peripheral region 100B on two opposite sides of the memory region 100A in opposite directions, respectively, so that the first end portion and the second end portion of the word line 200 are located in the peripheral region 100B on two opposite sides of the memory region 100A, respectively. At this time, the contact plug 300 may be formed on the first end and/or the second end of the word line 200.
In the present embodiment, of the two adjacent word lines 200, the contact plug 300 connected to one of the word lines 200 is formed on the first end portion, and the contact plug 300 connected to the other word line 200 is formed on the second end portion. That is, in this embodiment, the contact plugs 300 connected to the adjacent word lines 200 are formed on different ends of the word lines 200 and further located on different sides of the memory region 100A, so that the contact plugs 300 on the two adjacent word lines 200 are staggered from each other. Thus, the area of each contact plug 300 can be further increased.
Specifically, since the contact plugs 300 of the adjacent word lines 200 are respectively located on different ends of the word lines 200, the width of the contact plugs 300 may be further laterally extended along the arrangement direction (i.e., the X direction) of the word lines, so that the width dimension of the contact plugs 300 is greater than the width dimension of the word lines 200. In addition, the contact plug 300 is formed in the relatively open peripheral region 100B, so that the contact plug 300 may also be longitudinally expanded along the extending direction of the word line (i.e., the Y direction), thereby further increasing the width dimension of the contact plug 300 in the Y direction.
In this embodiment, the cross-sectional shape of the contact plug 300 perpendicular to the height direction may be rectangular, and both the width dimension and the length dimension of the contact plug 300 may be further expanded, so as to improve the process window of the contact plug 300.
With continued reference to fig. 1, in the present embodiment, the plurality of contact plugs 300 formed in the peripheral region 100B on the same side of the memory region 100A may be aligned in the word line arrangement direction (i.e., the X direction). That is, the plurality of contact plugs 300 formed on the first end portions of the different word lines are aligned in the arrangement direction of the word lines, and the plurality of contact plugs 300 formed on the second end portions of the different word lines are also aligned in the arrangement direction of the word lines.
Optionally, a trench isolation structure is further formed in the peripheral region 100B of the substrate 100, and the trench isolation structure may surround the memory region 100A to isolate the memory region 100A. At this time, the end of the word line 200 may extend into the trench isolation structure in the extending direction thereof, and the contact plug 300 may extend downward into the trench isolation structure to be connected to the end of the word line 200.
Alternatively, referring to fig. 2a, in another alternative, the substrate 100 in the peripheral area 100B includes, for example, a base 110, and a first insulating layer 120, a second insulating layer 130, and a third insulating layer 140 sequentially formed on the base 110. In this embodiment, for example, the end of the word line 200 may extend into the third insulating layer 140.
Wherein the first insulating layer 120 and the third insulating layer 140 may be formed of the same material, for example, the material of the first insulating layer 120 and the material of the third insulating layer 140 both include silicon oxide; and, the material of the second insulating layer 130 may be different from the first insulating layer 120 and the third insulating layer 140, for example, the material of the second insulating layer 130 includes silicon nitride.
With continued reference to fig. 2a, the word lines 200 are formed in the word line trenches 200A of the substrate 100, and in particular, the word line trenches 200A correspondingly extend from the memory region 100A into the peripheral region 100B. In this embodiment, the portion of the word line trench 200a located in the peripheral region 100B is opened in the third insulating layer 140 of the substrate.
Further, the word line 200 is filled in the word line trench 200a, and a top position of the word line 200 is lower than a top position of the word line trench 200 a. Based on this, the shielding layer 400 is further filled in the space above the word line trench 200a and above the word line 200, and the shielding layer 400 correspondingly covers the word line 200. And, the contact plug 300 connected to the word line 200 may correspondingly penetrate through the shielding layer 400 to extend to the word line 200.
In this embodiment, the contact plug 300 penetrates through the shielding layer 400 and may further extend into the word line 200, so that the contact plug 300 is partially embedded into the word line 200, thereby improving the electrical connection performance between the contact plug 300 and the word line 200. Specifically, the top position of the word line 200 corresponds to, for example, a first height position H1, and the bottom position of the contact plug 300 corresponds to, for example, a second height position H2, in the present embodiment, the second height position H2 is lower than the first height position H1.
However, it should be appreciated that in other embodiments (e.g., as shown with reference to fig. 2 b), the bottom of the contact plug 300 stops on the top surface of the word line 200, and at this time, the bottom position (the second height position H2) of the contact plug 300 and the top position (the first height position H1) of the word line 200 are at or near the same height position.
With continued reference to fig. 2a, in one embodiment, the contact plug 300 and the word line 200 are centrally aligned. However, in another embodiment (for example, as shown with reference to fig. 2 b), the contact plug 300 may also be offset with respect to the center of the word line 200. As described above, since the contact plugs 300 are formed in the peripheral region 100B, it is advantageous to realize the contact plugs 300 having a larger width, and even if there is an alignment deviation due to the limitation of the existing process when the contact plugs 300 are manufactured, the electrical connection between the contact plugs 300 and the word lines 200 can still be effectively ensured.
In this embodiment, a dielectric layer 500 is further formed on the substrate 100, and the contact plug 300 correspondingly further penetrates through the dielectric layer 500. That is, the contact plug 300 sequentially penetrates through the dielectric layer 500 and the shielding layer 400 to reach into the word line 200.
Further, the width dimension of the upper contact portion of the contact plug 300 in the dielectric layer 500 is greater than the width dimension of the lower contact portion of the contact plug 300 in the shielding layer 400. In this way, the width of the upper contact of the contact plug 300 is increased and the contact area of the upper contact is increased on the basis that the lower contact of the contact plug 300 can be connected to the word line 200.
Furthermore, in a specific embodiment, the contact plug 300 is received in a contact window, which penetrates the dielectric layer 500 and the shielding layer 400 in order to reach into the word line 200. And, the contact plug 300 may include a first conductive layer 310 and a second conductive layer 320, the first conductive layer 310 covering the bottom wall and the sidewall of the contact window, and the second conductive layer 320 formed on the first conductive layer 310 and filling the contact window. That is, the first conductive layer 310 wraps the bottom surface and the sidewalls of the second conductive layer 320.
Example two
The difference from the first embodiment is that in this embodiment, the contact plugs in the peripheral region on the same side of the memory region are staggered from each other in the arrangement direction of the word lines, rather than being arranged in perfect alignment.
Fig. 3 is a layout structure of a memory according to a second embodiment of the present invention, and as shown in fig. 3, the memory includes M word lines 200, where M is a positive integer greater than 1, and the M word lines 200 are sequentially arranged along a first direction (X direction).
Further, contact plugs connected to the nth word line are formed on the second end portion (not shown in the drawings), and contact plugs 300 'connected to the (N-1) th word line and contact plugs 300' connected to the (N + 1) th word line are formed on the first end portion, where N is a positive integer greater than 1 and less than M. That is, similar to the embodiment, the contact plugs 300' on two adjacent word lines 200 in the embodiment are also formed on different ends of the word lines 200, respectively.
However, unlike the first embodiment, in the present embodiment, the contact plugs 300 'located on the same end of the word line 200 (i.e., the contact plugs 300' located on the same side of the memory region 100A) are not aligned along the word line arrangement direction. Specifically, in the plurality of contact plugs 300 ' located on the same side of the memory region 100A, two adjacent contact plugs 300 ' are staggered from each other in the arrangement direction thereof, so that there is no mutually opposite portion in the arrangement direction of two adjacent contact plugs 300 ', and therefore the problem that the adjacent contact plugs 300 ' are easily bridged can be effectively improved, and the width dimension of the contact plugs 300 ' can be further increased.
In this embodiment, among the contact plugs 300 'located on the same side of the memory region 100A, the contact plugs 300' spaced apart from each other are aligned in the arrangement direction. That is, the contact plugs 300 ' on the same side are aligned in two rows, and the contact plugs 300 ' on one row are spaced from the adjacent contact plugs 300 ' on the other row.
As shown in fig. 3, the cross-sectional shape of the contact plug 300' perpendicular to the height direction may be circular, elliptical, or the like. Of course, the cross-sectional shape of the contact plug 300' may also be rectangular as shown in the first embodiment, for example.
Based on the memory as described above, a method of forming the memory will be described in detail below. Fig. 4 is a flowchart illustrating a method for forming a memory according to an embodiment of the invention, and as shown in fig. 4, the method for forming a memory according to the embodiment includes the following steps.
Step S100, a substrate is provided, where the substrate has a memory region and a peripheral region, and the peripheral region is located at the periphery of the memory region.
Referring specifically to fig. 1 to 3, a plurality of active regions AA may be formed in the memory region 100A of the substrate 100. In this embodiment, the substrate of the peripheral area 100B may include a base 110, and a first insulating layer 120, a second insulating layer 130, and a third insulating layer 140 sequentially formed on the base 110.
Step S200, forming a plurality of word lines in the substrate, wherein the word lines are formed in the memory region and extend into the peripheral region, so that end portions of the word lines are located in the peripheral region. In this embodiment, the end portion of the word line extends in the third insulating layer.
Referring to fig. 3 with emphasis, the method for forming the word line 200 includes: first, word line trenches 200A are formed in the substrate 100, and the word line trenches 200A are in the memory area 100A and pass through the corresponding active areas AA, and the end portions of the word line trenches 200A further extend into the peripheral area 100B; next, a conductive material is filled in the word line trench 200a to form the word line 200.
In this embodiment, the word line 200 does not fill the word line trench 200a, and based on this, after forming the word line 200, the method further includes: the shielding layer 400 is filled in the space above the word line trench 200a to cover the word line 200. Wherein, the material of the shielding layer 400 includes silicon nitride, for example.
Further, after the word line 200 is formed, the method further includes: a dielectric layer 500 is formed on the substrate 100, and the dielectric layer 500 correspondingly covers the shielding layer 400. The material of the dielectric layer 500 may be different from that of the shielding layer 400, for example, the material of the dielectric layer 500 may include silicon oxide.
Step S300, forming a contact plug formed in the peripheral region, wherein a bottom of the contact plug extends into the substrate to be electrically connected to an end of the word line.
As shown in fig. 3, the method for forming the contact plug includes the following steps.
Step one, forming a contact window in the peripheral region, wherein the bottom of the contact window extends into the substrate 100 to expose the word line 200.
The contact window can be formed by utilizing a photoetching process and an etching process. Firstly, defining the pattern of the contact window by utilizing a photoetching process, and then copying the pattern of the contact window into the substrate by utilizing an etching process. It should be noted that, since the contact window is formed in the open peripheral region, when the pattern of the contact window is defined by using the photolithography process, the process window of the contact window can be advantageously increased.
As described above, the two contact plugs connected to the two adjacent word lines 200 are respectively formed on different sides of the memory region 100A, and the two contact windows exposing the two adjacent word lines 200 are correspondingly respectively formed on different sides of the memory region 100A. At this time, a larger space can be reserved between two adjacent contact windows located on the same side of the memory region 100A, which is beneficial to increasing the opening size of the contact windows and further increasing the process window of the contact windows.
Further, copying the pattern of the contact window into the substrate comprises: the dielectric layer 500 and the shielding layer 400 are sequentially etched to expose the word line 200. In this embodiment, the dielectric layer 500 and the shielding layer 400 are made of different materials, so that different etching rates can be provided for the dielectric layer 500 and the shielding layer 400 during the etching process. Specifically, the etching rate of the dielectric layer 500 is greater than that of the shielding layer 400, so that the formed contact window is wide at the top and narrow at the bottom. That is, the opening size of the portion of the contact window located in the dielectric layer 500 is larger than the opening size of the portion of the contact window located in the shielding layer 400. Therefore, the width dimension of the top of the contact plug formed subsequently can be correspondingly increased.
Optionally, after exposing the top surface of the word line 200, the word line 200 may be further etched, so that the contact window further extends into the word line 200.
Step two, filling a conductive material in the contact window to form the contact plug 300.
Specifically, the method for filling the conductive material in the contact window comprises the following steps: first forming a first conductive layer 310 in the contact window, wherein the first conductive layer 310 covers the bottom wall and the side wall of the contact window; next, a second conductive layer 320 is formed on the first conductive layer 310, and the second conductive layer 320 fills the contact window.
In summary, in the memory provided in this embodiment, since the end portions of the word lines extend into the peripheral region, the contact plugs can be formed in the peripheral region to be electrically connected to the end portions of the corresponding word lines. Therefore, the space in the peripheral area can be fully utilized to make more space for the memory area to accommodate the capacitor assembly, and the contact plugs are prepared in the peripheral area, so that the size of each contact plug is increased, the preparation difficulty of the contact plug is effectively reduced, and the connection performance between the contact plug and the word line is correspondingly improved.
Furthermore, two contact plugs for connecting two adjacent word lines are respectively formed on different sides of the memory region, so that the distance between the adjacent contact plugs can be further increased, and the process window of the contact plugs can be further increased to a greater extent.
Furthermore, for a plurality of contact plugs located on the same side of the memory region, adjacent contact plugs may be staggered from each other, so that a greater size expansion of the contact plugs can be achieved.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (10)

1. A memory, comprising:
the substrate is provided with a memory area and a peripheral area, and the peripheral area is positioned at the periphery of the memory area;
a plurality of word lines buried in the substrate, and formed in the memory region and extending into the peripheral region such that ends of the word lines are located in the peripheral region; and the number of the first and second groups,
a contact plug formed in the peripheral region, and a bottom of the contact plug extending into the substrate to be electrically connected to an end of the word line.
2. The memory of claim 1, wherein the word line has opposite first and second ends, the first and second ends of the word line being located in the peripheral region on opposite sides of the memory region, respectively;
and in two adjacent word lines, a contact plug connected with one of the word lines is formed on the first end portion, and a contact plug connected with the other word line is formed on the second end portion.
3. The memory of claim 1, wherein the word line is formed in a word line trench of the substrate, and a top of the word line is lower than a top of the word line trench;
and the memory also comprises a shielding layer, the shielding layer is filled in the space above the word line groove and higher than the word line, and the contact plug also penetrates through the shielding layer to extend to the word line.
4. The memory of claim 1, wherein a dielectric layer is further formed on the substrate in the peripheral region, and the contact plugs extend through the dielectric layer to extend into the substrate.
5. The memory of claim 4, wherein a width dimension of an upper contact of the contact plug located in the dielectric layer is greater than a width dimension of a lower contact of the contact plug located in the substrate.
6. The memory according to claim 1, wherein the substrate of the peripheral region includes a base, and a first insulating layer, a second insulating layer, and a third insulating layer which are sequentially formed on the base, and wherein end portions of the word lines extend in the third insulating layer.
7. The memory of claim 1, wherein a width dimension of the contact plug is greater than a width dimension of the word line.
8. A memory, comprising:
the substrate is provided with a memory area and a peripheral area, and the peripheral area is positioned at the periphery of the memory area;
m word lines buried in the substrate, the M word lines being sequentially arranged along a predetermined direction, M being a positive integer greater than 1, the word lines being located in the memory region and extending into the peripheral region, and the word lines having opposite first and second ends, the first and second ends of the word lines being located in the peripheral region on opposite sides of the memory region, respectively;
a contact plug formed in the peripheral region, and a bottom of the contact plug extending into the substrate to be electrically connected to an end of the word line;
the contact plug connected with the Nth word line is formed on the second end part of the word line, the contact plug connected with the (N-1) th word line and the contact plug connected with the (N + 1) th word line are formed on the first end part of the word line, the contact plug connected with the (N-1) th word line and the contact plug connected with the (N + 1) th word line are staggered in the arrangement direction of the word lines, and N is a positive integer larger than 1 and smaller than M.
9. A method for forming a memory, comprising:
providing a substrate, wherein the substrate is provided with a memory area and a peripheral area, and the peripheral area is positioned at the periphery of the memory area;
forming a plurality of word lines in the substrate, the word lines being formed in the memory region and extending into the peripheral region such that ends of the word lines are located in the peripheral region;
forming a contact plug formed in the peripheral region, a bottom of the contact plug extending into the substrate to be electrically connected to an end of the word line.
10. The method of forming a memory of claim 9, wherein the word line is formed in a word line trench of the substrate, and a top of the word line is lower than a top of the word line trench; after the word lines are formed, filling a shielding layer in the space above the word line grooves and higher than the word lines, and at least forming a dielectric layer on the substrate in the peripheral area;
and, the method of forming the contact plug includes: and sequentially etching the dielectric layer and the shielding layer to expose the word line, forming a contact window, and filling a conductive material in the contact window to form the contact plug.
CN202010208500.XA 2020-03-23 2020-03-23 Memory and forming method thereof Pending CN111640755A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109309095A (en) * 2017-07-26 2019-02-05 三星电子株式会社 Three-dimensional semiconductor device
CN110021599A (en) * 2018-01-03 2019-07-16 三星电子株式会社 Semiconductor storage unit
CN211350647U (en) * 2020-03-23 2020-08-25 福建省晋华集成电路有限公司 Memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109309095A (en) * 2017-07-26 2019-02-05 三星电子株式会社 Three-dimensional semiconductor device
CN110021599A (en) * 2018-01-03 2019-07-16 三星电子株式会社 Semiconductor storage unit
CN211350647U (en) * 2020-03-23 2020-08-25 福建省晋华集成电路有限公司 Memory device

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Application publication date: 20200908