KR102122364B1 - Non-volatile memory device and manufacturing method thereof - Google Patents

Abstract

One aspect of the present invention, a channel region extending in a direction perpendicular to the upper surface of the substrate, a plurality of gate electrode layers stacked on the substrate to be adjacent to the channel region, the plurality of gate electrode layers having different lengths along one direction A plurality of pad regions extended to be provided, at least one etch stop layer disposed on the plurality of gate electrode layers spaced apart from the plurality of gate electrode layers in the plurality of pad regions, and a plurality of connected to the plurality of gate electrode layers It is possible to provide a non-volatile memory device including a contact plug.

Description

Non-volatile memory device and its manufacturing method{NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a nonvolatile memory device and a method of manufacturing the same.

As electronic products become smaller and smaller, they require high-capacity data processing. Accordingly, there is a need to increase the degree of integration of semiconductor memory devices used in such electronic products. As one of the methods for improving the degree of integration of a semiconductor memory device, a nonvolatile memory device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

The problem to be solved by the technical idea of the present invention is to provide a non-volatile memory device that is highly integrated and has improved reliability.

A nonvolatile memory device according to an embodiment of the present invention includes: a channel region extending in a direction perpendicular to an upper surface of a substrate; A plurality of gate electrode layers stacked on the substrate adjacent to the channel region; A plurality of pad regions in which the plurality of gate electrode layers extend in different lengths in one direction; At least one etch stop layer disposed on the plurality of gate electrode layers in the plurality of pad regions; And a plurality of contact plugs connected to the plurality of gate electrode layers. It includes.

A plurality of gate insulating layers provided between the plurality of gate electrode layers and the channel region; Further comprising, the etch stop layer may include the same material as at least one of the plurality of gate insulating films.

The thickness of the etch stop layer may be 2 times or less than the thickness of the gate insulating layer.

An insulating layer disposed between the plurality of gate electrode layers; Further, at least a portion of the plurality of gate insulating films may extend along the one direction to be disposed between the plurality of gate electrode layers and the insulating layer.

The etch stop layer may have a shape corresponding to a step between the plurality of pad regions.

The etch-stop layer may be a plurality of etch-stop layers, and the plurality of etch-stop layers may be disposed between the gate electrode layers.

Each of the plurality of etch stop layers may extend to the adjacent pad region along the one direction.

Different etch stop layers may be disposed between at least some of the plurality of gate electrode layers.

The at least one etch stop layer may be disposed on a portion of the gate electrode layer.

A method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention includes etching a plurality of sacrificial layers and insulating layers alternately stacked on a substrate to different lengths in one direction to form a plurality of pad regions having a step difference from each other Forming; Forming an etch-stop sacrificial layer on the plurality of pad regions; Removing the plurality of sacrificial layers and the etch-stop sacrificial layer; And depositing an insulating material on the regions where the plurality of sacrificial layers and the etch stop sacrificial layer are removed to form a gate insulating layer and an etch stop layer; It includes.

According to a non-volatile memory device and a method of manufacturing the same according to the technical spirit of the present invention, by forming an etch stop layer in an area where a stepped structure in which a contact plug is formed is provided, a bridge between upper and lower layers that may occur during contact plug formation ( bridge) can be prevented. Accordingly, a nonvolatile memory device with improved reliability can be provided.

1 is a schematic block diagram of a nonvolatile memory device according to an embodiment of the present invention.
2 is a circuit diagram illustrating a memory cell array of a nonvolatile memory device according to an embodiment of the present invention.
3 is a plan view illustrating a structure of a nonvolatile memory device according to an embodiment of the present invention.
4 to 6 are perspective views illustrating a structure of a nonvolatile memory device according to an embodiment of the present invention.
7A is an enlarged view of portion A in the nonvolatile memory device according to the embodiment illustrated in FIG. 4.
7B and 7C are enlarged views of a portion B in the nonvolatile memory device according to the embodiment shown in FIG. 6.
8A to 8M are cross-sectional views provided to describe a method of manufacturing a nonvolatile memory device according to the embodiment shown in FIG. 4.
9A to 9J are cross-sectional views provided to describe a method of manufacturing a nonvolatile memory device according to the embodiment shown in FIG. 5.
10A to 10I are cross-sectional views provided to describe a method of manufacturing a nonvolatile memory device according to the embodiment shown in FIG. 6.
11 to 13 are cross-sectional views illustrating a structure of a nonvolatile memory device according to another embodiment of the present invention.
14 and 15 are block diagrams illustrating an electronic device including a nonvolatile memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Embodiments of the present invention may be modified in various other forms or various embodiments may be combined, and the scope of the present invention is not limited to the embodiments described below. In addition, embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for a clearer description, and elements indicated by the same reference numerals in the drawings are the same elements.

1 is a schematic block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory device 10 according to an embodiment of the present invention includes a memory cell array 20, a driving circuit 30, a read/write circuit 40 and a control circuit ( 50).

The memory cell array 20 may include a plurality of memory cells, and the plurality of memory cells may be arranged along a plurality of rows and columns. The plurality of memory cells included in the memory cell array 20 includes a word line (WL), a common source line (CSL), a string select line (SSL), and a ground select line ( It may be connected to the driving circuit 30 through a ground select line (GSL), or the like, and may be connected to a read/write circuit 40 through a bit line (BL). In an embodiment, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

The plurality of memory cells included in the memory cell array 20 may be divided into a plurality of memory blocks. Each memory block includes a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of bit lines BL and at least one common source line CSL. Can be.

The driving circuit 30 and the read/write circuit 40 may be operated by the control circuit 50. In one embodiment, the driving circuit 30 receives address information from the outside, decodes the received address information, and connects word lines WL, common source lines CSL, and string selection lines connected to the memory cell array. At least some of the (SSL) and the ground selection line (GSL) may be selected. The driving circuit 30 may include driving circuits for each of the word line WL, the string selection line SSL, and the common source line CSL.

The read/write circuit 40 may select at least a portion of the bit line BL connected to the memory cell array 20 according to a command received from the control circuit 50. The read/write circuit 40 may read data stored in a memory cell connected to the selected at least some bit line BL, or write data to a memory cell connected to the selected at least some bit line BL. The read/write circuit 40 may include circuits such as a page buffer, an input/output buffer, and a data latch to perform the above operation.

The control circuit 50 may control operations of the driving circuit 30 and the read/write circuit 40 in response to a control signal CTRL transmitted from the outside. When reading data stored in the memory cell array 20, the control circuit 50 controls the operation of the driving circuit 30 to supply a voltage for a read operation to the word line WL in which the data to be read is stored. can do. When a voltage for a read operation is supplied to a specific word line WL, the control circuit 50 stores data stored in a memory cell in which the read/write circuit 40 is connected to a word line WL supplied with a voltage for a read operation. It can be controlled to read.

On the other hand, when writing data to the memory cell array 20, the control circuit 50 can control the operation of the driving circuit 30 to supply a voltage for a write operation to the word line WL to write data. have. When the voltage for the write operation is supplied to the specific word line WL, the control circuit 50 reads/writes the circuit 40 to write data to the memory cell connected to the word line WL to which the voltage for the write operation is supplied. ) Can be controlled.

2 is an equivalent circuit diagram of a memory cell array of a nonvolatile memory device according to an embodiment of the present invention.

2 is an equivalent circuit diagram illustrating a three-dimensional structure of a memory cell array included in the nonvolatile memory device 100'. Referring to FIG. 2, a memory cell array according to an embodiment includes n memory cell elements MC1 to MCn connected in series with each other and a ground selection transistor connected in series to both ends of the memory cell elements MC1 to MCn. A plurality of memory cell strings including (GST) and a string selection transistor (SST) may be included.

The n memory cell elements MC1 to MCn connected in series with each other may be respectively connected to word lines WL1 to WLn for selecting at least some of the memory cell elements MC1 to MCn.

The gate terminal of the ground selection transistor GST may be connected to the ground selection line GSL, and the source terminal may be connected to the common source line CSL. Meanwhile, the gate terminal of the string selection transistor SST may be connected to the string selection line SSL, and the source terminal may be connected to the drain terminal of the memory cell element MCn. 2 illustrates a structure in which the ground selection transistor GST and the string selection transistor SST are connected to the n memory cell elements MC1 to MCn connected in series with each other, but differently, a plurality of ground selection transistors GST ) Or a plurality of string selection transistors SST may be connected.

The drain terminal of the string select transistor SST may be connected to the bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, n memory cell elements MC1 to MCn in which signals applied through the bit lines BL1 to BLm are serially connected to each other. The data read or write operation can be executed by being transmitted to the. In addition, by applying a signal through the gate select line GSL to the gate terminal of the gate select transistor GST having the source terminal connected to the common source line CSL, the electric charges stored in the n memory cell elements MC1 to MCn are transferred. An erase operation that removes all may be performed.

3 is a plan view illustrating a structure of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, the nonvolatile memory device 100 according to an embodiment may include a cell array area C and a connection area D, and a peripheral circuit area may be provided outside the connection area D. Can be.

The cell array area C may include a plurality of memory cells, a plurality of bit lines 190 electrically connected to the memory cells, and a plurality of gate electrode layers 151-156: 150. Since the plurality of gate electrode layers 150 include a conductive material, it may also be referred to as a conductive line in this specification. The plurality of gate electrode layers 150 may extend in one direction, and FIG. 3 illustrates that the plurality of gate electrode layers 150 extend in the x-axis direction. The plurality of bit lines 190 may extend in a different direction that intersects one direction in which the plurality of gate electrode layers 150 extend, and in FIG. 3, the plurality of bit lines 190 in the y-axis direction intersecting the x-axis. It is shown as being extended.

The plurality of gate electrode layers 150 may be stacked in the z-axis direction to form a word line. Some of the gate electrode layers 150 disposed at the same height in the z-axis direction may be electrically connected to each other by a plurality of connection lines 221-226: 220. In order to connect some of the gate electrode layers 150 disposed at the same height in the z-axis direction to each other through the connection line 220, a plurality of contact plugs 201-206: 200 extending in the z-axis direction may be provided. .

A plurality of channel regions 130 may be disposed in a plurality of gate electrode layers 150 in a zig-zag shape, and each channel region 130 may be electrically connected to the bit line 190. By arranging the plurality of channel regions 130 in the zigzag form in the gate electrode layer 150, the number of channel regions 130 disposed in the gate electrode layer 150 can be increased.

The connection area D is disposed between the cell array area C and the peripheral circuit area. A plurality of gate electrode layers 150 extending from the cell array region C in one direction (x-axis direction) may be disposed in the connection region D. The length of each of the plurality of gate electrode layers 150 extending in one direction is gradually increased by a predetermined length from the gate electrode layer 151 positioned at the lowermost layer in the z-axis direction perpendicular to the xy plane to the gate electrode layer 156 of the uppermost layer. It can be shortened. As the length of extension in one direction becomes shorter from the lowermost gate electrode layer 151 to the uppermost gate electrode layer 156, each of the plurality of gate electrode layers 150 may form a step with another adjacent gate electrode layer 150. Can be.

A peripheral circuit region is disposed outside the connection region D. Circuits for driving memory cells and circuits for reading information stored in the memory cells may be disposed in the peripheral circuit area.

4 to 6 are perspective views illustrating a structure of a nonvolatile memory device according to an embodiment of the present invention.

4 is a perspective view showing a nonvolatile memory device 100 according to an embodiment of the present invention, and shows a portion cut along the I-I' direction of FIG. 3. 2 and 3, some of the components included in the memory cell may be omitted in FIG. 4. For example, the bit line 190 and the connection line 220 shown in FIG. 3 are omitted in FIG. 4.

Referring to FIG. 4, the nonvolatile memory device 100 is disposed between the plurality of gate electrode layers 151-156: 150 and the plurality of gate electrode layers 150 stacked on the upper surface of the substrate 105 along the z-axis direction. It may include a plurality of insulating layers (171-177: 170). The plurality of gate electrode layers 150 and the plurality of insulating layers 170 may extend along the x-axis direction. The cell array region C may further include a channel region 130 extending in the z-axis direction in addition to the plurality of gate electrode layers 150 and the insulating layer 170. The channel region 130 may be formed in a cavity having a cylindrical cross-section, and a buried insulating layer 120 may be disposed inside the channel region 130. A conductive layer 195 may be provided on the channel region 130, and the bit line 190 and the channel region 130 may be connected to each other through the conductive layer 195.

A gate insulating layer may be disposed between the channel region 130 and the gate electrode layer 150, and the gate insulating layer may include a tunneling layer, a charge storage layer, a blocking layer, and the like. Depending on the structure of the nonvolatile memory device 100, the tunneling layer, the charge storage layer, and the blocking layer are all disposed to surround the gate electrode layer 150, or some of them are in the z-axis direction parallel to the channel region 130 It may be disposed outside the channel region 130 to extend, and the rest may be disposed to surround the gate electrode layer 150. In FIG. 4, the tunneling layer and the charge storage layer are disposed outside the channel region 130 so as to extend in the z-axis direction in parallel with the channel region 130, and the blocking layer 162 is disposed to surround the gate electrode layer 150. As shown.

Each of the gate electrode layer 150 and the insulating layer 170 is connected to another gate electrode layer 150 and the insulating layer 170 stacked at different positions in the z-axis direction by different lengths along the x-axis direction. A plurality of stepped steps having a step shape can be formed in (D). A plurality of pad regions may be formed in the connection region D due to a step difference in which the plurality of gate electrode layers 150 and the insulating layers 170 are extended to different lengths along the x-axis direction, and the plurality of pad regions may be formed. An etch stop layer 110 may be disposed on each gate electrode layer 150. In FIG. 4, the insulating layer 170 is positioned above the gate electrode layer 150 along the z-axis direction in each pad region. On the contrary, the gate electrode layer 150 is positioned above the insulating layer 170. It might be.

In the connection area D, a plurality of contact plugs 201 to 206: 200 that are electrically connected to the gate electrode layer 150 through each of the connection area insulation layer 180 and the insulation layer 170 in each pad area may be provided. Can be. The plurality of contact plugs 200 may extend along the z-axis direction and may include a material having excellent conductivity similar to the gate electrode layer 150. For example, the plurality of contact plugs 200 may include the same material as the gate electrode layer 150, and the plurality of contact plugs 200 formed at the same location in the x-axis direction may include a connection line ( 221 ~ 226: 220) can be electrically connected to each other.

In order to form the plurality of contact plugs 200 in the connection region D, an etching process for the plurality of insulating layers 170 and the connection region insulating layers 180 is necessary after forming the plurality of pad regions. A plurality of vertical openings extending in the z-axis direction are formed by the etching process, and a contact plug 200 may be formed by filling a conductive material in the plurality of vertical openings.

Since the plurality of vertical openings formed by the etching process have different lengths in the z-axis direction, the gate electrode layer 156 positioned at the top in the z-axis direction contacts the contact plug 201 reaching the gate electrode layer 151 at the bottom. In order to form the plurality of insulating layers 170 and the connection region insulating layer 180 must not be penetrated by the etching process until the etching. Therefore, when the etch selectivity is not appropriate, a part of the gate electrode layer 150 located at the upper portion is penetrated by the vertical opening in the z-axis direction by an etching process, and some gate electrode layers 150 are electrically connected to each other after filling of the conductive material. A bad bridge may occur.

In the present invention, one or more etch stop layers 110 may be formed on the gate electrode 150 in a plurality of pad regions to prevent such defects. The etch stop layer 110 may have the same composition (for example, Al ₂ O ₃ ) as at least a portion of the gate insulating layer 160 surrounding each of the plurality of gate electrode layers 150. In forming the contact plug 200, after performing an etching process on the connection region insulating layer 180 to have a selectivity with a material included in the etch stop layer 110, the gate electrode layer 150 is included By applying an etching process having a conductive material and a selectivity to be used, the contact plug 200 may be formed so as not to cause a connection failure due to penetration of the gate electrode layer 150 and insufficient etching.

The etch stop layer 110 forms a contact plug 201 having a relatively long length in the z-axis direction, while the contact plug 206 having a relatively short length penetrates the gate electrode layer 156 positioned thereon. Can be prevented. Therefore, the etch stop layer 110 may be formed only on a portion of the plurality of gate electrode layers 150. For example, it may be formed only on the three gate electrode layers 154, 155, and 156 positioned above so as not to penetrate the gate electrode layer 150 during the process of forming the contact plug 200.

Meanwhile, FIG. 4 shows that four memory cells MC1 to MC4 and one string select transistor SST and a ground select transistor GST are provided, but this is only an example, and the number and string selection of the memory cells The number of transistors SST and the ground selection transistor GST may be more or less. In addition, although the memory cells MC1 to MC4 and the string select transistor SST and the ground select transistor GST have the same structure in FIG. 4, the string select transistor SST and the ground select transistor GST are memory. It may have a different structure from the cells MC1 to MC4.

5 is a perspective view illustrating a nonvolatile memory device 100A according to an embodiment different from FIG. 4. Referring to Figure 5, the channel region 130, the memory cells (MC1 ~ MC4), the string selection transistor (SST), the ground selection transistor (GST), the step provided in the connection area (D) and a plurality of pad regions and a plurality The plurality of contact plugs 200 connected to each of the plurality of gate electrode layers 150 in the pad region of FIG. 4 is the same as FIG. 4. However, in the embodiment illustrated in FIG. 5, a plurality of etch stop layers 110a and 110b having a shape corresponding to a step provided in the connection region D are provided. Between the plurality of etch stop layers 110a and 110b, an insulating layer AD2 that physically separates the etch stop layers 110a and 110b from each other may be additionally provided.

In the etching process of forming the plurality of contact plugs 200, the vertical opening in which the contact plug 206 is connected to the gate electrode layer 156 positioned at the top in the z-axis direction is formed with the gate electrode layer 151 positioned at the bottom. The uppermost gate electrode layer 156 should not be penetrated until the vertical opening in which the contact plug 201 to be connected is formed is etched. In the nonvolatile memory device 100A illustrated in FIG. 5, two or more etch stop layers 110a and 110b are formed, and an etch process is performed to have a material and selectivity included in the etch stop layers 110a and 110b. You can proceed.

Accordingly, during the long etching process of forming the vertical opening corresponding to the contact plug 201 connected to the lowermost gate electrode layer 151, the vertical opening corresponding to the contact plug 206 connected to the uppermost gate electrode layer 156 is formed. Since the etching process to be formed is temporarily stopped or slowed by the plurality of etch stop layers 110a and 110b, defects caused by the upper gate electrode layer 156 penetrating can be prevented. On the other hand, even in the nonvolatile memory device 100A illustrated in FIG. 5, the etch stop layers 110a and 110b may be formed only on a portion of the gate electrode layer 150 positioned in the z-axis direction. Alternatively, the first etch-stop layer 110a is formed to be positioned on all the gate electrode layers 150 as shown in FIG. 5, and the second etch-stop layer 110b is a portion of the gate electrode layer 150 positioned above the z-axis direction. ).

6 is a perspective view illustrating a nonvolatile memory device 100B according to an embodiment different from FIGS. 4 and 5. Referring to FIG. 6, the nonvolatile memory device 100B according to an embodiment includes a plurality of gate electrode layers 150 and a plurality of insulating layers 170 alternately stacked on the upper surface of the substrate 105 along the z-axis direction. It may include. A pupil penetrating the plurality of gate electrode layers 150 and the insulating layer 170 to the substrate 105 in the cell array region C along the z-axis direction may be provided, and the channel region 130 may be provided inside the penetrated pupil. ) May be provided.

Each of the plurality of gate electrode layers 150 and the plurality of insulating layers 170 may extend in different lengths along the x-axis direction to form a step with other adjacent gate electrode layers 150 and the insulating layer 170. A plurality of pad regions are provided in the connection region D by the step, and in each pad region, a contact plug 200 passing through the insulating layer 170 and electrically connected to the gate electrode layer 150 is formed. Hereinafter, the nonvolatile memory device 100B illustrated in FIG. 6 will be described with reference to structural features different from FIGS. 4 and 5.

Referring to FIG. 6, an etch-stop layer 110c extending parallel to the gate electrode layer 150 along the x-axis direction is provided between the gate electrode layers 150 adjacent to each other. Although FIG. 5 illustrates that one etch-stop layer 110c is provided in one insulating layer 170, a plurality of etch-stop layers 110c may be provided in one insulating layer 170. The etch stop layer 110c may include the same material as the gate insulating layer 160 ′ surrounding each of the gate electrode layers 150 and extends in the same length as the adjacent gate electrode layer 150 along the x-axis direction.

By providing the etch stop layer 110c in a structure as shown in FIG. 6, effects similar to those of the embodiments of FIGS. 4 and 5 can be obtained. After forming a plurality of pad regions by etching each of the plurality of gate electrode layers 150 and the insulating layer 170 to form a step with other gate electrode layers 150 and the insulating layer 170 adjacent in the z-axis direction, a contact plug is formed. In order to provide 200, an etching process may be performed to provide a plurality of vertical openings extending in the z-axis direction.

At this time, by applying an etching process having a selectivity with the etch-stop layer 110c, a plurality of vertical openings in which the contact plug 200 is provided may reach the etch-stop layer 110c. A portion of the vertical opening corresponding to the contact plug 200 connected to the gate electrode layer 150 located in the z-axis direction may pass through the etch stop layer 110c to reach the gate electrode layer 150. Therefore, by selectively etching the connection region insulating layer 180 with respect to the etch stop layer 110c, it is possible to control such that each vertical opening does not prevent defects passing through the gate electrode layer 150. Meanwhile, in order to electrically connect the gate electrode layer 150 and the contact plug 200, a vertical opening in which the contact plug 200 is formed may be formed to a depth that digs the gate electrode layer 150 by a predetermined depth.

4 and 5, in the nonvolatile memory device 100B of FIG. 6, the etch stop layer 110c may be formed only on a portion of the gate electrode layer 150 positioned in the z-axis direction. For example, the etch stop layer 110c is disposed only on the two gate electrode layers 155 and 156 positioned in the z-axis direction, and the etch stop layer 110c is disposed on the other four gate electrode layers 151 to 154. It may not be deployed. The number of gate electrode layers 150 on which the etch stop layer 110c is formed may be appropriately modified as necessary.

7A is an enlarged view of portion A in the nonvolatile memory device according to the embodiment shown in FIG. 4.

7A is a partially enlarged view of portion A of FIG. 4 to describe the channel region 130 and the gate insulating layer 160. Referring to FIG. 7A, a gate electrode layer 154 included in the memory cell MC3 and insulating layers 173 and 174 positioned above and below the gate electrode layer 154 are illustrated. The channel region 130 extends in the z-axis direction, and a buried insulating layer 120 including, for example, silicon oxide (SiO ₂ ) may be provided in the channel region 130. A tunneling layer 166 and a charge storage layer 164 may be sequentially stacked from the channel region 130 between the gate electrode layer 154 and the insulating layers 173 and 174 and the channel region 130.

The gate electrode layer 154 is surrounded by a blocking layer 162, and consequently, a tunneling layer 166, a charge storage layer 164 from the channel region 130 between the channel region 130 and the gate electrode layer 154, And the blocking layer 162 is sequentially stacked. The thickness of the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 included in the gate insulating layer 160 is not limited to that illustrated in FIG. 7A and may be variously changed. On the other hand, in this embodiment, the thickness of the etch-stop layer 110 is less than twice the thickness of the blocking layer 162 to prevent the material included in the gate electrode layer 154 from entering the etch-stop layer 110 Can be.

The tunneling layer 166 includes silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), aluminum oxide (Al ₂ O ₃ ), and at least one of zirconium oxide (ZrO ₂ ).

The charge storage layer 164 may be a charge trap layer or a floating gate conductive layer. When the charge storage layer 164 is a floating gate, it can be formed by depositing polysilicon, for example, by LPCVD (Low Pressure Chemical Vapor Deposition). When the charge storage layer 164 is a charge trap layer, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ) , Tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), hafnium aluminum oxide (HfAl _x O _y ), hafnium tantalum oxide (HfTa _x O _y ), hafnium silicon oxide (HfSi _x O _y ), aluminum nitride ( Al _x N _y ), and aluminum gallium nitride (AlGa _x N _y ).

The blocking layer 162 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a high dielectric constant dielectric material. The high dielectric constant dielectric material is aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon Oxide (ZrSi _x O _y ), Hafnium oxide (HfO ₂ ), Hafnium silicon oxide (HfSi _x O _y ), Lanthanum oxide (La ₂ O ₃ ), Lanthanum aluminum oxide (LaAl _x O _y ), Lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ). The dielectric constant of the material included in the blocking layer 162 may have a higher dielectric constant than the tunneling layer 166, and optionally, the blocking layer 162 may include a plurality of layers having different dielectric constants. In this case, by arranging a layer having a relatively low dielectric constant closer to the channel region 130 than a layer having a high dielectric constant, an energy band such as a barrier height is controlled to adjust characteristics of a nonvolatile memory device, such as erase. ) Can improve the characteristics.

7B and 7C are enlarged views of a portion B in the nonvolatile memory device according to the embodiment shown in FIG. 6.

First, referring to FIG. 7B, similar to FIG. 7A, the channel region 130 is provided in the z-axis direction, and the buried insulating layer 120 is provided inside the channel region 130. The gate electrode layer 154 and the insulating layers 173 and 174 may be alternately stacked outside the channel region 130, and between the gate electrode layer 154 and the insulating layers 173 and 174 and the channel region 130. The tunneling layer 166 and the charge storage layer 164 may be sequentially stacked from the channel region 130.

The gate electrode layer 154 is surrounded by a blocking layer 162, and consequently, a tunneling layer 166, a charge storage layer 164 from the channel region 130 between the channel region 130 and the gate electrode layer 154, And the blocking layer 162 may be sequentially stacked. The thickness of the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 included in the gate insulating layer 160 are not limited to those illustrated in FIG. 7B and may be variously modified.

Meanwhile, an etch-stop layer 110 may be provided in each of the insulating layers 173 and 174. The etch stop layer 110 may include the same material as the blocking layer 162 surrounding the gate electrode layer 154, and may include, for example, aluminum oxide (Al ₂ O ₃ ). Although FIG. 7B illustrates that one etch stop layer 110 is included in each of the insulating layers 173 and 174, differently, two or more etch stop layers 110 may be included in each of the insulating layers 173 and 174. have. In order to prevent the conductive material included in the gate electrode layer 154 from being included in the etch-stop layer 110, the thickness of the etch-stop layer 110 may be less than twice the thickness of the blocking layer 162.

7C is an enlarged view of a portion B in the nonvolatile memory device according to the embodiment illustrated in FIG. 6. 7C has a structure similar to that of FIG. 7B, and has a structure different from that of FIG. 7B only in the gate insulating layer 160. The buried insulating layer 120 is provided in the channel region 130 extending along the z-axis direction, and the gate electrode layer 154 and the insulating layers 173 and 174 are alternately stacked outside the channel region 130. .

However, unlike the embodiment of FIG. 7B in which the tunneling layer 166 and the charge storage layer 164 provided between the gate electrode layer 154 and the channel region 130 extend along the channel region 130 in the z-axis direction. In FIG. 7C, the tunneling layer 166' and the charge storage layer 164' may have a shape surrounding the gate electrode layer 154 together with the blocking layer 162'. Even in FIG. 7C, the thickness of the blocking layer 162 ′, the charge storage layer 164 ′, and the tunneling layer 166 ′ included in the gate insulating layer 160 ′ is not limited to those illustrated in FIG. 7C, and variously It can be transformed.

In the embodiment of FIG. 7C, the etch stop layer 110c may include the same material as the material included in at least one of the blocking layer 162 ′, the charge storage layer 164 ′, and the tunneling layer 166 ′. . In forming the channel region 130 as shown in FIG. 7C, prior to forming the gate electrode layer 154 with a conductive material, the tunneling layer 166', the charge storage layer 164', and the blocking layer 162' are formed. These can be stacked sequentially. Therefore, if the thickness of the etch-stop layer 110c is less than or equal to twice the thickness of the tunneling layer 166', the etch-stop layer 110c may include the same material as the tunneling layer 166', and the etch-stop layer ( If the thickness of 110c) is greater than twice the thickness of the tunneling layer 166' and less than twice the thickness sum of the tunneling layer 166' and the charge storage layer 164', the etch stop layer 110c is the tunneling layer 166 ') and the materials included in the charge storage layer 164'.

In addition, if the thickness of the etch stop layer 110c is less than twice the total thickness of the gate insulating layer 160', and if the thickness of the tunneling layer 166' and the charge storage layer 164' is greater than twice, the blocking layer ( 162'), the charge storage layer 164' and the tunneling layer 166', respectively. Since the etch stop layer 110c is penetrated by the contact plug 200, in order to prevent each of the plurality of contact plugs 200 from being electrically connected to each other, a conductive material must not be included in the etch stop layer 110. The thickness of the etch stop layer 110c may not be greater than twice the total thickness of the gate insulating layer 160 ′. Meanwhile, the structure of the gate insulating layer 160 ′ as illustrated in FIG. 7C includes the nonvolatile memory device 100B illustrated in FIG. 6, as well as the nonvolatile memory devices 100 and 100A illustrated in FIGS. 4 and 5. Can also be applied to

Hereinafter, a method of manufacturing the nonvolatile memory device illustrated in FIGS. 4 to 6 will be described with reference to FIGS. 8 to 10.

8A to 8M are cross-sectional views provided to describe a method of manufacturing a nonvolatile memory device according to the embodiment shown in FIG. 4. 8A to 8M are cross-sectional views of the perspective view of FIG. 4 in the y direction according to the process sequence.

Referring to FIG. 8A, a plurality of insulating layers 171-177: 170 and a plurality of sacrificial layers 141-146: 140 are alternately stacked on the substrate 105. The sacrificial layer 140 may be formed of a material that can be etched with an etch selectivity to the insulating layer 170. That is, the sacrificial layer 140 may be formed of a material that can be etched while minimizing the etching of the insulating layer 170 in the process of etching the sacrificial layer 140. The etch selectivity may be quantitatively expressed through a ratio of the etch rate of the sacrificial layer 140 to the etch rate of the insulating layer 170. For example, the insulating layer 170 may be at least one of a silicon oxide film and a silicon nitride film, and the sacrificial layer 140 is a material different from the insulating layer 170 selected from a silicon film, a silicon oxide film, a silicon carbide film, and a silicon nitride film. Can be

8A, the thickness of each of the plurality of insulating layers 170 may be different according to embodiments. For example, the insulating layer 171 positioned at the bottom of the plurality of insulating layers 170 in the z-axis direction may have a relatively thin thickness compared to other insulating layers 172-177, and the insulating layer located at the top The layer 177 may be relatively thick compared to other insulating layers 171-176. That is, the thickness of the insulating layer 170 and the sacrificial layers 140 is not limited to that shown in FIG. 8A and can be variously modified, and the number of layers of the films constituting the insulating layer 170 and the sacrificial layer 140 It can also be variously modified.

The first mask layer M1 is formed on the plurality of alternately stacked insulating layers 170 and the sacrificial layer 140. The first mask layer M1 may include a photoresist, and may be formed of a composite layer of a photosensitive material and a non-photosensitive material.

8A, the plurality of insulating layers 170 and the sacrificial layer 140 exposed by the first mask layer M1 may be etched and removed. The etching process may be performed by anisotropic etching using a dry etching method or a wet etching method. When using the dry etching method, a removal process may be performed in a plurality of steps to sequentially etch the stacked insulating layer 170 and the sacrificial layer 140.

When the plurality of insulating layers 170 and the sacrificial layer 140 exposed by the first mask layer M1 are removed by etching, the first mask layer M1 may be trimmed. A dry etching method or a wet etching method may be applied to the trimming process, and a second mask layer M2 in which a portion of the edge of the first mask layer M1 is removed as shown in FIG. 8B is formed by the trimming process. At this time, the length of the first mask layer M1 in the x-axis direction as well as the height in the z-axis direction may be reduced by the trimming process.

Referring to FIG. 8C, a plurality of insulating layers 170 and sacrificial layers 140 exposed by the second mask layer M2 may be etched in the same manner as in FIG. 8B. At this time, the etching process of FIG. 8C may proceed from the bottom to the second insulating layer 172, from which a first pad region may be formed. When the etching process is completed, a trimming process may be performed on the second mask layer M2 to form a third mask layer M3 that covers a smaller area than the second mask layer M2. The second pad region may be formed by etching the plurality of insulating layers 173-177 and the sacrificial layers 142-146 exposed by the third mask layer M3.

By repeating the etching process and the trimming process for the plurality of insulating layers 170 and the sacrificial layer 140 according to the method described with reference to FIGS. 8B and 8C, a structure as shown in FIG. 8D can be finally formed. have. Referring to FIG. 8D, each insulating layer 170 and the sacrificial layer 140 form a pair, and the insulating layer 170 and the sacrificial layer 140 included in one pair have one direction-an x-axis direction. -It can be extended to the same length with each other. As an exception, the sacrificial layer 141 positioned at the lowermost portion in the z-axis direction may be provided with insulating layers 171 and 172 extending in the upper and lower portions by the same length in each direction.

In addition, the insulating layer 170 and the sacrificial layer 140 included in one pair are extended in the x-axis direction by different lengths from the insulating layer 170 and the sacrificial layer 140 included in another adjacent pair, and thus FIG. 8d As shown in the figure, a plurality of steps can be formed. The area exposed by the plurality of steps may be defined as a plurality of pad areas P1-P6.

Referring to FIG. 8E, an insulating layer AD may be additionally formed on the plurality of insulating layers 170 and the sacrificial layer 140 provided with the plurality of pad regions P1-P6. The insulating layer AD may be formed to cover ends of the plurality of insulating layers 170, and hereinafter, the plurality of insulating layers 170 may be disposed between the plurality of sacrificial layers 140. -177) may be used as a term referring to the insulating layer AD formed in FIG. 8E. The insulating layer AD formed in FIG. 8E may have a relatively thin thickness compared to the insulating layers 171-177 disposed between the plurality of sacrificial layers 140, and the etch-stopping sacrificial layer formed in FIG. 8F ( 115) may be physically separated from the plurality of sacrificial layers 140. The insulating layer AD may include the same material as the insulating layers 171-177 provided between the plurality of sacrificial layers 140, and thus, in the drawings after FIG. 8F, the insulating layer AD may include a plurality of sacrifices. The insulating layers 171-177 provided between the layers 140 will be collectively referred to as the insulating layer 170 without distinction.

8F, an etch-stop sacrificial layer 115 is formed on the insulating layer 170. The etch-stop sacrificial layer 115 may include the same material as the plurality of sacrificial layers 140, and may have a thickness smaller than twice the thickness of the gate insulating layer 160 formed later. The thickness limit is an etch-stop layer when the etch-stop sacrificial layer 115 and the plurality of sacrificial layers 140 are removed by an etching process and the etch-stop layer 110 and the plurality of gate electrode layers 150 are formed. It may be to prevent the conductive material is introduced into the (110). 7A or 7B, when only the blocking layer 162 is provided in the first side opening T1, the etch-stopping sacrificial layer 115 may be less than or equal to twice the thickness of the blocking layer 162, in the case of FIG. 7C Here, the gate insulating layer 160 ′ including all of the blocking layer 162 ′, the charge storage layer 164 ′, and the tunneling layer 166 ′ may be 2 times or less.

When the etch-stopping sacrificial layer 115 is provided, a connection region insulating layer 180 may be formed on the visual-stopping sacrificial layer 115 as illustrated in FIG. 8G. The connection region insulating layer 180 may include the same material as the plurality of insulating layers 170. In the manufacturing method according to an embodiment of the nonvolatile memory device, the peripheral circuit region may be formed first, and then the cell array region C and the connection region D may be formed. In this case, the heights of the cell array regions C, the connection regions D, and the peripheral circuit regions may be the same by the formation and planarization of the connection region insulating layer 180.

When the connection region insulating layer 180 is formed, the channel region 130 may be formed as illustrated in FIG. 8H. In order to form the channel region 130, a plurality of openings penetrating the plurality of insulating layers 170 and the sacrificial layer 140 in the z-axis direction may be formed. The plurality of openings may be arranged in a zigzag shape in the x-y plane, and the plurality of openings may be isolated from each other in the x-y plane. The plurality of openings may be formed by exposing only the areas where the plurality of openings are provided by the mask layer and anisotropically etching the exposed areas, similar to the method in which the plurality of pad areas P1-P6 are formed. Each of the plurality of openings may expose an upper surface of the substrate 105 or may have a depth that digs the substrate 105 by a predetermined depth.

The charge storage layer 164 and the tunneling layer 166 may be formed on the inner and lower surfaces of each of the plurality of openings by using ALD or CVD. The charge storage layer 164 and the tunneling layer 166 are sequentially stacked from regions adjacent to the plurality of sacrificial layers 140 and the insulating layer 170, and the channel region 130 is formed inside the tunneling layer 166. do. The channel region 130 may be formed to a predetermined thickness, for example, a thickness in a range of 1/50 to 1/5 of each width of the plurality of openings, similar to the charge storage layer 164 and the tunneling layer 166. It can be formed by ALD or CVD. On the other hand, the channel region 130 at the bottom of each opening may be in direct contact with the substrate 105 to be electrically connected.

The inside of the channel region 130 may be filled with a buried insulating layer 120. Optionally, before forming the buried insulating layer 120, a hydrogen annealing step of heat-treating the structure in which the channel region 130 is formed in a gas atmosphere containing hydrogen or deuterium may be further performed. Many of the crystal defects present in the channel region 130 may be cured by the hydrogen annealing step.

Although the structure is according to the embodiment illustrated in FIG. 7A, it is needless to say that the channel region 130 may be formed in another structure. For example, after forming a plurality of openings, the channel region 130 is immediately formed without a process of forming the charge storage layer 164 and the tunneling layer 166, and the buried insulating layer (inside the channel region 130) is formed. 120). At this time, the tunneling layer 166 and the charge storage layer 164 are formed before the process of forming the blocking layer 162 and the gate electrode layer 150 as shown in the embodiment shown in FIG. 7C and placed outside the blocking layer 162 Can be.

Next, a planarization process may be performed to remove unnecessary semiconductor material and insulating material covering the uppermost connection region insulating layer 180. Thereafter, the upper portion of the buried insulating layer 120 may be partially removed using an etching process or the like, and a material forming the conductive layer 195 may be deposited at the removed location. Again, by performing a planarization process, the conductive layer 195 may be formed.

When the channel region 130 is formed, side openings T1 and T2 may be formed by removing the plurality of sacrificial layers 140 and the etch-stop sacrificial layer 115 as illustrated in FIG. 8I. As the plurality of sacrificial layers 140 are removed, a plurality of first side openings T1 are provided between the plurality of insulating layers 170 and between the plurality of insulating layers 170 and the connection region insulating layers 180. The second side opening T2 may be provided by removing the provided etch-stop sacrificial layer 115.

Referring to FIG. 8J, a blocking layer 162 and a gate electrode layer 151-156: 150 may be formed in side openings T1 and T2. As illustrated in FIG. 8F, the thickness of the etch-stop sacrificial layer 115 may be less than or equal to twice the thickness of the blocking layer 162 formed in the first side opening T1 to prevent the conductive material from flowing in, Therefore, the thickness of the second side opening T2 may also be less than twice the thickness of the blocking layer 162.

The blocking layer 162 and the gate electrode layer 150 are sequentially formed in the first side opening T1, and the blocking layer 162, like the charge storage layer 164 and the tunneling layer 166, is ALD, CVD, or physical. It may be formed by a vapor deposition (Physical Vapor Deposition, PVD) process. In this case, the same material as the blocking layer 162 may be introduced into the second side opening T2 to form the etch stop layer 110, and the thickness of the second side opening T2 is limited. 2 The inner space of the side opening T2 may be filled with the same material as the blocking layer 162.

That is, the conductive material included in the gate electrode layer 150 may not flow into the second side opening T2 but may enter only the first side opening T1. The blocking layer 162 and the etch stop layer 110 may include aluminum oxide (Al ₂ O ₃ ), and the gate electrode layer 150 may include a conductive material such as tungsten (W).

When the blocking layer 162, the etch stop layer 110, and the gate electrode layer 150 are formed, as shown in FIG. 8K, an etching process is performed in the z-axis direction parallel to the channel region 130 to form a contact plug 200 ) May form a plurality of vertical openings 211-216: 210. The etching process of forming the plurality of vertical openings 210 may include a process of selectively etching a material included in the connection region insulating layer 180 with respect to the etch stop layer 110, from which a plurality of gate electrode layers It is possible to prevent a problem that at least a part of the 150 is penetrated or not connected to the vertical opening 210. Hereinafter, it demonstrates in detail.

In the etching process of simultaneously forming the plurality of vertical openings 210, the first vertical opening 211 connected to the gate electrode layer 151 positioned at the bottom in the z-axis direction is relatively compared to other vertical openings 212-216. Long etch process times may be required. In addition, in the case of the sixth vertical opening 216, it may be formed during a relatively short etching process time compared to other vertical openings 211-215. Accordingly, when the etching is performed under a certain condition without any change in process conditions or the etch stop layer 110, the etch process continues for a time required to form the first vertical opening 211, so that the sixth vertical opening 216 The gate electrode layer 156 may be penetrated to be connected to another gate electrode layer 155.

In the present invention, by providing an etch stop layer 110 on the gate electrode layer 150 in the pad regions P1-P6 defined by the step created by each gate electrode layer 150 extending in the x-axis direction, as described above, You can solve the same problem.

When forming the vertical opening 210, an etching process may be performed to have a predetermined selectivity with a material included in the etch stop layer 110, and each vertical opening 210 formed by the etching process is in the z-axis direction As the etch stop layer 110 is reached, the speed of the etching process may be slowed down. While the etching process continues to form other vertical openings 211-215, the sixth vertical opening 216 first reaches the etch stop layer 110 and etching is performed at a slow speed, so the sixth vertical The opening 216 does not penetrate the gate electrode layer 156.

The etching process of forming the plurality of vertical openings 210 includes a first etching process for selectively etching the plurality of insulating layers 170 with respect to the etch stop layer 110, and a plurality of insulation with respect to the gate electrode layer 150 A second etching process for selectively etching the layer 170 may be included. While some vertical openings 210 reaching the etch stop layer 110 are slowly etched using the first etching process, other vertical openings 210 may be formed to a desired depth. When the vertical opening 210 reaches the etch stop layer 110 by the first etching process, the vertical opening 210 of the vertical opening 210 is dug into the gate electrode layer 150 by a predetermined depth using the second etching process. The length in the z-axis direction can be extended.

When a plurality of vertical openings 210 are provided, a plurality of contact plugs 201-206: 200 may be formed by filling each vertical opening 210 with a conductive material, as shown in FIG. 8L. The conductive material filling the vertical opening 210 may be the same as the conductive material included in the gate electrode layer 150, and may be, for example, tungsten (W). A plurality of connection lines 221-226: 220 may be formed on the plurality of contact plugs 200 as shown in FIG. 8M. The plurality of connection lines 220 may be formed in a direction parallel to the bit line 190 or in a direction crossing the direction in which the plurality of gate electrode layers 150 extend, and the gate electrode layers formed at the same height in the z-axis direction ( 150) may be electrically connected to each other.

9A to 9J are cross-sectional views provided to describe a method of manufacturing a nonvolatile memory device according to the embodiment shown in FIG. 5.

9A to 9J are cross-sectional views of the perspective view of FIG. 5 in the y-axis direction, and the manufacturing process in the connection region D may be mainly described.

Referring to FIG. 9A, a plurality of pad regions P1-P6 are provided by etching the plurality of insulating layers 170 and the sacrificial layer 140 alternately stacked on the upper surface of the substrate 105. Each of the plurality of insulating layers 170 and the sacrificial layer 140 is formed by the plurality of pad regions P1 to P6 to form a step with the other insulating layer 170 and the sacrificial layer 140. In addition, a portion of the top surface of each insulating layer 170 may be exposed by the plurality of pad regions P1-P6, and as shown in FIG. 9A, each sacrificial layer 140 may be provided in the plurality of pad regions P1-P6. Some of the top surface may be exposed.

When a plurality of pad regions P1-P6 are provided, an insulating layer AD is additionally formed on the pad regions P1-P6 as shown in FIGS. 9B and 9C, and the etch-stop sacrificial layer 115a, 115b). At this time, between the first etch-stop sacrificial layer 115a and the second etch-stop sacrificial layer 115b, an insulating layer for physically separating the first etch-stop sacrificial layer 115a and the second etch-stop sacrificial layer 115b (AD2) may be further provided. When the etch-stop sacrificial layers 115a and 115b are provided, a connection region insulating layer 180 may be applied on the second etch-stop sacrificial layer 115b and a planarization process may be performed, and a structure as illustrated in FIG. 9D Can form.

Next, referring to FIG. 9E, a channel region 130 may be formed. The method of forming the channel region 130 may be the same as described above with reference to FIG. 8H. When the channel region 130 is formed, as shown in FIG. 9F, side openings T1 and T2 may be provided by removing the etch-stopping sacrificial layers 115a and 115b and the plurality of sacrificial layers 140. The first side opening T1 may correspond to a space in which the plurality of sacrificial layers 140 are provided, and the second side opening T2 may correspond to a space in which the etch stop sacrificial layers 115a and 115b are provided.

A predetermined material may be introduced into the side openings T1 and T2 as shown in FIG. 9G. At this time, the blocking layer 162 is first deposited on the first side opening T1 to form the gate insulating layer 160 together with the charge storage layer 164 and the tunneling layer 166 provided outside the channel region 130, , The gate electrode layer 150 may be formed of a conductive material such as tungsten (W) inside the blocking layer 162. The same material as the blocking layer 162 may be deposited on the second side opening T2 to form the etch stop layers 110a and 110b.

At this time, the thickness of the second side opening T2 may be less than twice the thickness of the blocking layer 162 formed in the first side opening T1. By limiting the thickness of the second side opening T2 to the above conditions, the conductive material forming the gate electrode layer 150 is introduced into the second side opening T2 in addition to the material forming the gate insulating layer 160. Can be prevented.

In addition, the tunneling layer 166 and the charge storage layer 164 are not provided outside the channel region 130, and the tunneling layer 166 included in the gate insulating layer 160 in the first side opening T1 is charged. The storage layer 164 and the blocking layer 162 may both be provided. At this time, the thickness of the second side opening T2 may be less than twice the total thickness of the gate insulating layer 160 including the tunneling layer 166, the charge storage layer 164, and the blocking layer 162.

When the blocking layer 162 and the gate electrode layer 150 and the etch stop layers 110a and 110b are formed, a plurality of vertical openings 211 connected to each pad region P1 to P6 by performing an etching process in the z-axis direction -216: 210). The plurality of vertical openings 210 may have a narrowing width as it approaches the substrate 105 according to the etching conditions, and the etching process of forming the plurality of vertical openings 210 may include etching blocking layers 110a and 110b. It may have a predetermined etch selectivity.

That is, the vertical opening 210 may be formed using an etching process of selectively etching the connection region insulating layer 180 and the plurality of insulating layers 170 with respect to the etch stop layers 110a and 110b. By using the etching process under the above conditions, while the vertical opening 211 connected to the gate electrode layer 151 located at the bottom is formed, the vertical opening 216 connected to the gate electrode layer 156 located at the top is formed at the top. It can be prevented from passing through the gate electrode layer 156 located in.

A conductive plug-for example, tungsten (W)-may be filled in the plurality of vertical openings 210 as shown in FIG. 9I to form contact plugs 201-206: 200, and as shown in FIG. 9J A plurality of connection lines 221-226: 220 may be provided on the plug 200. The plurality of connection lines 220 may electrically connect some of the plurality of gate electrode layers 150 provided at the same height in the z-axis direction, and may extend in the y-axis direction. Since the plurality of connection lines 220 must be electrically connected to the plurality of gate electrode layers 150 through the plurality of contact plugs 200, the etching process of forming the vertical opening 210 is performed with respect to the gate electrode layer 150 It may include an etching process to selectively etch the insulating layer 170 of.

10A to 10I are cross-sectional views provided to describe a method of manufacturing a nonvolatile memory device according to the embodiment shown in FIG. 6.

10A to 10I are cross-sectional views of the perspective view of FIG. 6 in the y-axis direction, and the manufacturing process in the connection region D will be mainly described.

Referring to FIG. 10A, a plurality of insulating layers 171-177: 170 and a plurality of sacrificial layers 141-146: 140 are alternately stacked on the upper surface of the substrate 105, and the plurality of insulating layers 170 and A mask M is provided on a structure in which a plurality of sacrificial layers 140 are alternately stacked. A plurality of etch-stop sacrificial layers 115c may be formed of the same material as the plurality of sacrificial layers 140 in the plurality of insulating layers 170.

The etch-stop sacrificial layer 115c may be parallel to the x-y plane like the plurality of sacrificial layers 140. 10A illustrates a structure in which one etch-stopping sacrificial layer 115 is formed between the adjacent sacrificial layers 140 in the stacking direction, but a plurality of etch-stopping sacrificial layers 115c between the adjacent sacrificial layers 140. It may be formed. In addition, a different number of etch-stop sacrificial layers 115c may be formed between adjacent sacrificial layers 140.

Referring to FIG. 10B, similar to that described with reference to FIGS. 8A to 8D, a process of etching an area exposed by the mask M and trimming the mask M is repeated to repeat a plurality of pad areas as shown in FIG. 10B. (P1-P6) can be formed. A connection region insulating layer 180 may be formed on the plurality of pad regions P1-P6 as shown in FIG. 10C. After forming the connection region insulating layer 180, the heights of the cell array region C, the connection region D, and the peripheral circuit region may be the same by a planarization process.

Next, a channel region 130 is formed as shown in FIG. 10D. The method of forming the channel region 130 may be the same as described above with reference to FIG. 8H, the buried insulating layer 120 inside the channel region 130, and the tunneling layer (outside the channel region 130). 166) and the charge storage layer 164 may be provided in order. A conductive layer 195 may be provided on the channel region 130, and the conductive layer 195 may be electrically connected to the bit line 190.

When the channel region 130 is formed, the plurality of side openings T1 and T2' may be formed by removing the plurality of sacrificial layers 140 and the etch-stop sacrificial layer 115c provided in the insulating layer 170. . The plurality of first side openings T1 may correspond to a space in which the gate electrode layer 150 is provided, and the plurality of second side openings T2' may correspond to a space in which the etch stop layer 110c is provided.

The plurality of first side openings T1 are filled with a blocking layer 162 and a conductive material as shown in FIG. 10F, and the plurality of second side openings T2' are formed with a material included in the blocking layer 162. The same material can be filled. In one embodiment, when the blocking layer 162 includes aluminum oxide (Al ₂ O ₃ ), aluminum oxide is also applied to the plurality of second side openings T2 ′ to form the etch stop layer 110c. have. The thickness of the second side opening T2' may be less than or equal to twice the thickness of the blocking layer 162, so that only the material included in the blocking layer 162 may be filled in the second side opening T2'. . That is, the second side opening T2' may not include a conductive material. A gate electrode layer 150 may be further formed of a conductive material-for example, tungsten (W)-inside the blocking layer 162 formed in the first side opening T1.

Meanwhile, when the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 are both formed in the first side opening T1, as shown in the embodiment shown in FIG. 7C, the second side opening T2' ) May be less than or equal to twice the thickness of the gate insulating layer 160 including the blocking layer 162, the charge storage layer 164, and the tunneling layer 166. The inside of the second side opening T2' is filled with a material included in at least one of the blocking layer 162, the charge storage layer 164, and the tunneling layer 166, and thus the conductive material included in the gate electrode layer 150 Does not flow into the second side opening T2'.

When the etch stop layer 110c, the blocking layer 162, and the gate electrode layer 150 are formed, as shown in FIG. 10G, an etch process is performed in the z-axis direction to form a plurality of vertical openings 211-216: 210. Can form. In the etching process of forming the vertical opening 210, the material included in the etch stop layer 110c may have a predetermined etching selectivity, from which the vertical opening 216 located in the z-axis direction is located at the gate electrode layer 156 ) To solve the problem of defects.

A conductive plug, for example, the same material as the gate electrode layer 150 may be injected into the vertical opening 210 to form contact plugs 201-206: 200 as illustrated in FIG. 10H. Referring to FIG. 10I, a plurality of connection lines 221-226: 220 extending in the y-axis direction are disposed on the contact plug 200, and each connection line 220 is a gate disposed at the same position in the z-axis direction. Some of the electrode layers 150 may be electrically connected to each other.

11 to 13 are cross-sectional views illustrating a structure of a nonvolatile memory device according to another embodiment of the present invention. 11 to 13, only the connection area D is shown in the nonvolatile memory device for convenience of description.

First, referring to FIG. 11, a plurality of gate electrode layers 151-158: 150 and a plurality of insulating layers 171-179: 170 may be alternately stacked on the substrate 105. Each of the plurality of gate electrode layers 150 and the insulating layer 170 is extended by different lengths in one direction-in the x-axis direction in FIG. 11 by an etching process using a mask layer, and the other gate electrode layer 150 and the insulating layer ( 170), and a plurality of pad regions may be formed due to the step.

The etch stop layers 110a and 110b are provided on the gate electrode layer 150 in the plurality of pad regions. At this time, the etch-stop layers 110a and 110b may have a shape corresponding to a plurality of pad regions and a step, and may have a stair shape as illustrated in FIG. 11. The etch-stop layers 110a and 110b may include the same material as at least a portion of the gate insulating layer 160 surrounding the plurality of gate electrode layers 150.

The plurality of connection lines 221-228: 220 may be electrically connected to the gate electrode layer 150 by the contact plugs 201-208: 200 passing through the etch stop layers 110a and 110b and the gate insulating layer 160. have. The connection line 220 may extend in the y-axis direction and electrically connect some of the plurality of gate electrode layers 150 stacked at the same height in the z-axis direction.

In the process of forming the vertical opening to form the contact plug 200, the etch stop layers 110a and 110b may function as a stopper for the etching process. That is, the etching process may be performed with process conditions for selectively etching the connection region insulating layer 180 and the plurality of insulating layers 170 with respect to the etch stop layers 110a and 110b. That is, when the connection region insulating layer 180 is etched and reaches the etch stop layers 110a and 110b, the etch rate may be slowed by the etch stop layers 110a and 110b. Therefore, during the etching process of simultaneously forming a plurality of vertical openings, a defect in which some vertical openings are excessively etched to penetrate a portion of the gate electrode layer 150 may be prevented.

In FIG. 11, one etch stop layer 110a is provided on four pad regions located in the z-axis direction, and two etch stop layers 110a and 110b are disposed on four pad regions located in the z-axis direction. ) Is provided, but the number of the etch stop layers 110a and 110b is not necessarily limited to such a form. The etch stop layers 110a and 110b may be provided in plural in some pad regions located at the top or only one in some pad regions located at the bottom, and the same number of etch stop layers 110a may be provided on all pad regions regardless of upper and lower portions. 110b) may be provided.

Referring to FIG. 12, a plurality of gate electrode layers 151-158: 150 and a plurality of insulating layers 171-179: 170 are alternately stacked on the substrate 105. Most of the components of the nonvolatile memory device 100 illustrated in FIG. 12 are the same as the embodiment of FIG. 11, but the structure of the etch stop layer 110c may be different from that of FIG. 11. In FIG. 12, the etch stop layer 110c has a shape extending in one direction-in the x-axis direction-as in the plurality of gate electrode layers 150, not in a step shape corresponding to a plurality of pad regions and steps as shown in FIG. 11. . That is, the plurality of etch stop layers 110c may extend in one direction to have different lengths, and may extend in one direction as long as the adjacent gate electrode layer 150.

As described with reference to FIG. 11, as the etch stop layer 110c is provided in the plurality of pad regions in FIG. 12, an etch process of forming a plurality of vertical openings to form the contact plugs 201-208: 200 In the at least a portion of the plurality of gate electrode layers 150, it is possible to suppress the occurrence of defects through the etching process. By performing an etching process of forming the contact plug 150 to have a selectivity with a material included in the etch-stop layer 110c, the speed of the etch process can be relatively slowed when the etch-stop layer 110c is reached. Accordingly, even if an etching process of simultaneously forming a plurality of vertical openings is performed, a defect problem caused by a part of the gate electrode layer 150 being penetrated or a vertical opening not extending to some of the gate electrode layers 150 may be solved. .

13 is a view showing a modified form of the embodiment shown in FIG. Referring to FIG. 13, a plurality of etch stop layers 110c and 110d are provided adjacent to the plurality of gate electrode layers 151 to 158: 150, and the etch stop layers 110c and 110d disposed between the gate electrode layers 150 are provided. ) Is selectively arranged differently. The etch stop layer 110c adjacent to the first, second, seventh, and eighth gate electrode layers 151, 152, 157, and 158 includes only one layer, and the third to sixth gate electrode layers 153-156 The etch-stop layer 110d adjacent to may include two layers. However, unlike FIG. 13, it is needless to say that the etch stop layers 110c and 110d may be formed by a combination of more various numbers.

14 is a block diagram illustrating a storage device including a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 14, the storage device 1000 according to an embodiment may include a controller 1010 communicating with a host HOST and memory 1020-1, 1020-2, and 1020-3 storing data. Can be. Each of the memories 1020-1, 1020-2, and 1020-3 may include a nonvolatile memory device according to various embodiments of the present invention as described above with reference to FIGS.

The host (HOST) communicating with the controller 1010 may be various electronic devices in which the storage device 1000 is mounted, for example, a smart phone, a digital camera, a desktop, a laptop, or a media player. The controller 1010 receives a data write or read request transmitted from the host (HOST) and stores the data in the memories 1020-1, 1020-2, and 1020-3, or the memory 1020-1, 1020-2, 1020-3) A command (CMD) for fetching data may be generated.

As illustrated in FIG. 14, one or more memories 1020-1, 1020-2, and 1020-3 in the storage device 1000 may be connected to the controller 1010 in parallel. By connecting a plurality of memories 1020-1, 1020-2, and 1020-3 in parallel to the controller 1010, a storage device 1000 having a large capacity such as a solid state drive (SSD) may be implemented.

15 is a block diagram illustrating an electronic device including a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 15, the electronic device 2000 according to an embodiment may include a communication unit 2010, an input unit 2020, an output unit 2030, a memory 2040, and a processor 2050.

The communication unit 2010 may include a wired/wireless communication module, and may include a wireless Internet module, a short-range communication module, a GPS module, and a mobile communication module. The wired/wireless communication module included in the communication unit 2010 may be connected to an external communication network according to various communication standard standards to transmit and receive data.

The input unit 2020 is a module provided for a user to control the operation of the electronic device 2000, and may include a mechanical switch, a touch screen, and a voice recognition module. In addition, the input unit 2020 may include a mouse or a finger mouse device that operates in a track ball or laser pointer method, or may further include various sensor modules through which a user can input data.

The output unit 2030 outputs information processed by the electronic device 2000 in the form of audio or video, and the memory 2040 can store a program or data for processing and control of the processor 2050. . The memory 2040 may include one or more nonvolatile memory devices according to various embodiments of the present invention as described above with reference to FIGS. 1 to 13, and the processor 2050 may store the memory 2040 according to necessary operations. You can store or retrieve data by passing the command to.

The memory 2040 may be embedded in the electronic device 2000 or communicate with the processor 2050 through a separate interface. When communicating with the processor 2050 through a separate interface, the processor 2050 may store or retrieve data in the memory 2040 through various interface standards such as SD, SDHC, SDXC, MICRO SD, and USB. .

The processor 2050 may control the operation of each part included in the electronic device 2000. The processor 2050 may perform control and processing related to voice calls, video calls, data communication, etc., or may perform control and processing for multimedia playback and management. Also, the processor 2050 may process input transmitted from the user through the input unit 2020 and output the result through the output unit 2030. Also, as described above, the processor 2050 may store data necessary for controlling the operation of the electronic device 2000 in the memory 2040 or withdraw the data from the memory 2040.

100: non-volatile memory device 105: substrate
110: etch stop layer 115: etch stop sacrificial layer
120: buried insulating layer 130: channel region
140: sacrificial layer 150: gate electrode layer
160: gate insulating film 162: blocking layer
164: charge storage layer 166: tunneling layer
170: insulating layer 180: connecting region insulating layer
190: bit line 195: conductive layer
200: contact plug 210: vertical opening
220: connection line P1-P6: pad area

Claims (10)

A channel region extending in a direction perpendicular to the upper surface of the substrate;
A plurality of gate electrode layers stacked on the substrate adjacent to the channel region;
A plurality of pad regions in which the plurality of gate electrode layers extend in different lengths in one direction;
A plurality of etch stop layers spaced apart from the plurality of gate electrode layers on the pad region provided in the gate electrode layers connected to memory cells among the plurality of gate electrode layers;
A separation insulating layer disposed between the plurality of etch stop layers; And
A plurality of contact plugs connected to the plurality of gate electrode layers; Non-volatile memory device comprising a. According to claim 1,
A plurality of gate insulating layers provided between the plurality of gate electrode layers and the channel region; Further comprising,
Each of the plurality of etch-stop layers includes the same material as at least one of the plurality of gate insulating layers. According to claim 2,
The thickness of the etch stop layer is less than twice the thickness of the gate insulating film. According to claim 2,
An insulating layer disposed between the plurality of gate electrode layers; Further comprising,
At least a portion of the plurality of gate insulating films extends along the one direction to be disposed between the plurality of gate electrode layers and the insulating layer. According to claim 1,
The etch-stop layer has a shape corresponding to a step between the plurality of pad regions. According to claim 1,
The thickness of each of the plurality of etch stop layers is less than the thickness of the isolation insulating layer. According to claim 1,
Each of the plurality of etch stop layers is a non-volatile memory device that continuously extends from the lowest pad area to the uppermost pad area among the plurality of pad areas. delete According to claim 1,
The plurality of etch-stop layers include a first etch-stop layer and a second etch-stop layer over the first etch-stop layer, wherein the first etch-stop layer is disposed on all of the plurality of gate electrode layers, and 2 The etch stop layer is a non-volatile memory device disposed only on a portion of the plurality of gate electrode layers. Etching a plurality of sacrificial layers and a plurality of insulating layers alternately stacked on a substrate to different lengths in one direction to form a plurality of pad regions having a step difference with each other;
Forming a plurality of etch-stopping sacrificial layers and a separation insulating layer between the plurality of etch-stopping sacrificial layers on a portion of the plurality of pad regions;
Forming a connection region insulating layer on the plurality of pad regions;
Removing the plurality of sacrificial layers and the plurality of etch stop sacrificial layers; And
Depositing an insulating material on the regions where the plurality of sacrificial layers and the plurality of etch stop sacrificial layers are removed to form a gate insulating layer and a plurality of etch stop layers; Method of manufacturing a non-volatile memory device comprising a.

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