KR102565717B1 - Memory device - Google Patents

Abstract

A memory device according to an embodiment of the present invention includes a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel layers passing through the plurality of gate electrode layers, and provided between the plurality of channel layers and the plurality of gate electrode layers. First and second regions adjacent to a gate insulating layer and the plurality of gate electrode layers and alternately disposed along a first direction parallel to the upper surface of the substrate and having different heights in a direction perpendicular to the upper surface of the substrate Include a common source line containing

Description

Memory device {MEMORY DEVICE}

The present invention relates to a memory device.

Electronic products require high-capacity data processing even though their volume is getting smaller. Accordingly, it is necessary to increase the degree of integration of semiconductor memory devices used in such electronic products. As one of methods for improving the degree of integration of a semiconductor memory device, a memory device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a memory device capable of increasing the degree of integration by reducing the size of a channel region.

A memory device according to an embodiment of the present invention includes a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel layers passing through the plurality of gate electrode layers, and provided between the plurality of channel layers and the plurality of gate electrode layers. a gate insulating layer, and first and second regions alternately disposed along a first direction parallel to the upper surface of the substrate and having different heights in a direction perpendicular to the upper surface of the substrate; and a common source line adjacent to an electrode layer, wherein the gate insulating layer extends parallel to a plurality of vertical regions surrounding each of the plurality of channel layers and an upper surface of the substrate and is disposed below the plurality of gate electrode layers. contains the horizontal area.

A memory device according to an embodiment of the present invention includes a plurality of gate structures each having a plurality of gate electrode layers and a plurality of insulating layers stacked on an upper surface of a substrate, extending in a direction perpendicular to the upper surface of the substrate, and including the plurality of gate structures. A plurality of channel layers penetrating the gate structure, a plurality of vertical regions disposed outside the plurality of channel layers of each gate structure, and a horizontal region extending from the plurality of vertical regions and disposed below each gate structure. A charge storage layer having a region, and a horizontal channel layer connecting the plurality of channel layers under the charge storage layer and contacting the substrate.

A memory device according to an embodiment of the present invention includes a plurality of gate structures each including a plurality of gate electrode layers disposed on the upper surface of the substrate, and extending in a direction perpendicular to the upper surface of the substrate to form the plurality of gate structures of the respective gate structures. A plurality of channel layers passing through the gate electrode layer of and connected to the substrate by a horizontal channel layer disposed under the plurality of gate electrode layers, between the plurality of channel layers and the plurality of gate electrode layers and between the horizontal channel layers a charge storage layer disposed on an upper surface thereof, and a common source line disposed between the plurality of gate structures and extending in a first direction parallel to the upper surface of the substrate, wherein the substrate is disposed under the horizontal channel layer; and a first impurity region and a second impurity region disposed between the common source line and the horizontal channel layer, wherein the first and second impurity regions include carbon.

According to the memory device according to the technical idea of the present invention, the substrate and the channel layer are directly connected without an epitaxial layer formed between the plurality of channel layers and the substrate, and the plurality of channel layers are connected to each other within the substrate, thereby increasing the diameter of the channel layer. can reduce Accordingly, open defects of the substrate and the channel that may occur during the manufacturing process may be prevented, and the degree of integration of the memory device may be improved.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a schematic block diagram of a memory device according to an embodiment of the present invention.
2 is a circuit diagram illustrating a memory cell array of a memory device according to an exemplary embodiment of the present invention.
3 is a plan view schematically illustrating a memory device according to an exemplary embodiment of the present invention.
4 and 5 are perspective views illustrating a partial area of the memory device shown in FIG. 3 .
FIG. 6 is an enlarged view of area A of FIG. 4 .
FIG. 7 is a cross-sectional view of the memory device shown in FIG. 3 viewed from the direction II'.
FIG. 8 is a cross-sectional view of the memory device shown in FIG. 3 viewed from the II-II' direction.
FIG. 9 is a cross-sectional view of the memory device shown in FIG. 3 viewed from the direction II'.
FIG. 10 is a cross-sectional view of the memory device shown in FIG. 3 viewed from the II-II' direction.
11 is a perspective view illustrating a memory device according to an exemplary embodiment of the present invention.
12 to 59 are diagrams provided to describe a method of manufacturing a memory device according to an embodiment of the present invention.
60 is a block diagram illustrating an electronic device including a memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1 , a memory device 1 according to an embodiment of the inventive concept may include a memory cell array 2 , a row decoder 3 and a core logic circuit 6 . The core logic circuit 6 may include a read/write circuit 4 and a control circuit 5 .

The memory cell array 2 may include a plurality of memory cells arranged along a plurality of rows and columns. A plurality of memory cells included in the memory cell array 2 include a word line (WL), a common source line (CSL), a string select line (SSL), and a ground select line ( It can be connected to the row decoder 3 through a Ground Select Line (GSL), etc., and can be connected to the read/write circuit 4 through a bit line (Bit Line, BL). In one embodiment, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

A plurality of memory cells included in the memory cell array 2 may be divided into a plurality of memory blocks. Each memory block may include a plurality of word lines (WL), a plurality of string select lines (SSL), a plurality of ground select lines (GSL), a plurality of bit lines (BL), and at least one common source line (CSL). can

The row decoder 3 receives address information ADDR from the outside and decodes the received address information ADDR to select a word line WL, a common source line CSL, and a string connected to the memory cell array 2. A voltage supplied to at least some of the line SSL and the ground select line GSL may be determined.

The read/write circuit 4 may select at least some of the bit lines BL connected to the memory cell array 2 according to a command received from the control circuit 5 . The read/write circuit 4 may read data stored in memory cells connected to at least some selected bit lines BL or write data to memory cells connected to at least some selected bit lines BL. The read/write circuit 4 may include circuits such as a page buffer, an input/output buffer, and a data latch in order to perform the above operations.

The control circuit 5 may control operations of the row decoder 33 and the read/write circuit 4 in response to a control signal CTRL transmitted from the outside. When data stored in the memory cell array 2 is read, the control circuit 5 controls the operation of the row decoder 3 to supply voltage for a read operation to the word line WL in which the data to be read is stored. can do. When a voltage for a read operation is supplied to a specific word line WL, the control circuit 5 allows the read/write circuit 4 to store data stored in a memory cell connected to the word line WL to which the voltage for a read operation is supplied. can be controlled to read.

Meanwhile, when data is written to the memory cell array 2, the control circuit 5 may control the operation of the row decoder 3 to supply voltage for a write operation to a word line WL on which data is to be written. there is. When a voltage for a write operation is supplied to a specific word line WL, the control circuit 5 writes data to a memory cell connected to the word line WL to which the voltage for a write operation is supplied. ) can be controlled.

2 is an equivalent circuit diagram illustrating a memory cell array of a memory device according to an exemplary embodiment of the present invention. A semiconductor device according to an embodiment of the present invention may be a vertical NAND flash device.

Referring to FIG. 2 , the memory cell array includes n memory cells MC1 to MCn connected in series with each other, a ground select transistor GST connected in series with both ends of the memory cells MC1 to MCn, and a string select transistor. It may include a plurality of memory cell strings (S) including (SST). The n number of memory cells MC1 to MCn serially connected to each other may be respectively connected to n number of word lines WL1 to WLn for selecting the memory cells MC1 to MCn. Meanwhile, dummy cells may be further disposed between the ground select transistor GST and the first memory cell MC1 and between the string select transistor SST and the nth memory cell MCn.

A gate terminal of the ground select transistor GST may be connected to the ground select line GSL, and a source terminal of the ground select transistor GST may be connected to the common source line CSL. Meanwhile, a gate terminal of the string select transistor SST may be connected to the string select line SSL, and a source terminal may be connected to the drain terminal of the memory cell MCn. 2 shows a structure in which a ground selection transistor (GST) and a string selection transistor (SST) are connected one by one to n memory cells (MC1 to MCn) connected in series with each other, but unlike the plurality of ground selection transistors (GST) Alternatively, a plurality of string select transistors SST may be connected.

A drain terminal of the string select transistor SST may be connected to a plurality of bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, the signal applied through the bit lines BL1 to BLm is applied to n memory cells MC1 to MCn connected in series with each other. By passing it, data reading and writing operations can be executed. Also, an erase operation for erasing data written in the memory cells MC1 to MCn may be performed by applying a predetermined erase voltage through a well region formed on the substrate.

Meanwhile, referring to FIG. 2 , a memory device according to an embodiment of the present invention may include at least one dummy string DS. The dummy string DS may be a string including a dummy channel electrically separated from the bit lines BL1 to BLm.

3 is a plan view schematically illustrating a memory device according to an exemplary embodiment of the present invention.

First of all, referring to FIG. 3 , a memory device 100 according to an embodiment of the present invention may include a plurality of channel structures CH and dummy channel structures DCH that are separated from each other and disposed on a plane. Unlike the channel structure CH, the dummy channel structure DCH may not be electrically connected to the bit line BIT LINE. The plurality of channel structures CH and the dummy channel structure DCH extend along a direction (Z-axis direction) perpendicular to the top surface (X-Y plane) of the substrate to form a plurality of gate electrode layers and an interlayer insulating layer 170 disposed thereon. It can penetrate your back.

The plurality of gate electrode layers may be divided into a plurality of regions by the common source line 150 . A spacer 109 may be provided on a side surface of the common source line 150 to separate the common source line 150 from the plurality of gate electrode layers. An isolation insulating layer 155 may be provided between the common source lines 150 , and in an embodiment, the isolation insulating layer 155 may divide at least one of the plurality of gate electrode layers. The plurality of dummy channel structures DCH may pass through the isolation insulating layer 155 .

The common source line 150 may extend along a direction perpendicular to the top surface (XY plane) of the substrate (Z-axis direction) and a first direction (X-axis direction). A lower portion of the common source line 150 may be connected to a source region provided on a substrate. In an embodiment of the present invention, a plurality of support regions 105 may be provided in at least a portion of a substrate, and a plurality of support regions 105 may allow a common source line 150 to have a plurality of different heights. area can be included. Hereinafter, it will be described with reference to FIG. 4 .

4 and 5 are perspective views illustrating a partial area of the memory device shown in FIG. 3 .

4 and 5 , a memory device 100 according to an embodiment of the present invention includes a substrate 101 and a plurality of gate electrode layers 131-138 stacked on an upper surface (X-Y plane) of the substrate 101: 130), a plurality of insulating layers (141-149: 140), and a plurality of channel layers 110 penetrating the plurality of gate electrode layers 130. A gate insulating layer 160 may be provided between the plurality of gate electrode layers 130 and the plurality of channel layers 110 .

The gate insulating layer 160 includes a blocking layer 162, a charge storage layer 164, and a tunneling layer 166 sequentially disposed in a direction from the gate electrode layer 130 toward the channel layer 110. can do. The gate insulating layer 160 may further include an additional blocking layer 168 between the blocking layer 162 and the gate electrode layer 130 . In some embodiments, the additional blocking layer 168 may be omitted. The plurality of gate electrode layers 130, the plurality of channel layers 110, and the gate insulating layer 160 provide a ground select transistor (GST), a plurality of memory cells (MC1-MCn), and a string select transistor (SST). can do. The number of ground select transistors GST and string select transistors SST may be changed differently from those shown in FIGS. 4 and 5 and may have structures different from those of the memory cells MC1 -MCn.

Each of the plurality of channel layers 110 may be disposed in a plurality of channel structures CH or a dummy channel structure DCH. The plurality of channel structures CH and the plurality of dummy channel structures DCH may have structures similar to each other. In one embodiment, the channel structure and the dummy channel structure (CH, DCH) are disposed on the outer surface of the channel layer 110, the buried insulating layer 115 provided in the inner space of the channel layer 110, and the channel layer 110. A gate insulating layer 160 and a drain region 113 provided on the channel layer 110 may be included.

In the embodiment shown in FIGS. 4 and 5 , the channel layer 110 is shown as having a cylindrical shape having a space therein, however, unlike the channel layer 110, there may be no space inside. In this case, the buried insulating layer 115 may be omitted. Meanwhile, in the embodiment shown in FIGS. 4 and 5, the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 surround the outer surface of the channel layer 110, and the additional blocking layer 168 Although illustrated to surround each of the plurality of gate electrode layers 130 , otherwise, the additional blocking layer 168 may be omitted and the gate insulating layer 160 may be formed to surround the outer surface of the channel layer 110 . The buried insulating layer 115 may extend more deeply into the substrate 101 than the gate insulating layer 160 and the plurality of channel layers 110 .

The common source line 150 is along a direction (Z-axis direction) perpendicular to the top surface (X-Y plane) of the substrate 101 and along a first direction (X-axis direction) parallel to the top surface (X-Y plane) of the substrate 101. may be extended. The common source line 150 may be connected to the source region 108 provided therebelow. The source region 108 may be a region formed by implanting impurities, in one embodiment, N-type impurities into a partial region of the substrate 101 .

Referring to FIG. 4 , the common source line 150 may include first and second regions 151 and 152 having different heights in a direction perpendicular to the upper surface of the substrate 101 . The height of the second area 152 may be greater than that of the first area 151 . In the lower portion of the first region 151 having a relatively smaller height than the second region 152, the substrate 101 may have a plurality of support regions 105 protruding upward toward the common source line CSL. there is. As shown in FIG. 5 , the plurality of support regions 105 may be separately disposed along the first direction (X-axis direction). In the manufacturing process, a plurality of support regions 105 are first formed and then a common source line 150 is formed, and the first region 151 is defined as a region located above the plurality of support regions 105. can That is, the lower surface of the first region 151 may contact the upper surface of the plurality of support regions 105 . Due to the plurality of support regions 105 , the thickness of the substrate 101 in the lower portion of the first region 151 may be greater than the thickness of the substrate 101 in the lower portion of the second region 152 .

Meanwhile, referring to FIGS. 4 and 5 , at least a portion of the gate insulating layer 160 may be disposed on the upper surface of the substrate 101 . That is, at least a portion of the gate insulating layer 160 may be located between the upper surface of the substrate 101 and the insulating layer 141 positioned at the lowermost part in the stacking direction (Z-axis direction). Referring to FIG. 5 in which portions of the plurality of gate electrode layers 130 and the plurality of insulating layers 140 are cut, partial regions of the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 are shown. It may be placed on the upper surface of the substrate 101 . This is because the additional blocking layer 168 is formed to surround the plurality of gate electrode layers 130 in the embodiment shown in FIGS. 4 and 5 .

That is, in the embodiment of the present invention, at least one of a plurality of layers included in the gate insulating layer 160 is placed on the upper surface of the substrate 101 in each unit region defined as the region between the common source lines 150. It may include a horizontal area to be placed. The horizontal area may be defined as an area formed parallel to the upper surface of the substrate 101 . The horizontal area may have a plate shape. At least one of a plurality of layers included in the gate insulating layer 160, for example, the charge storage layer 164, surrounds the outside of the channel layers 110 and is vertical regions perpendicular to the upper surface of the substrate 101. And, it may include the horizontal area. 4 and 5, the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 may have horizontal areas parallel to the upper surface of the substrate 101, and thus have different Vertical regions of the blocking layer 162 , the charge storage layer 164 , and the tunneling layer 166 surrounding the channel layer 110 may be connected to each other by the respective horizontal regions.

In an embodiment of the present invention, the plurality of channel layers 110 disposed inside the gate insulating layer 160 may be directly connected to the substrate 101 . In one embodiment, due to characteristics of a manufacturing process, each of the plurality of channel layers 110 may be connected to each other by a horizontal channel layer provided in the substrate 101 . Hereinafter, it will be described with reference to FIG. 6 .

FIG. 6 is an enlarged view of area A of FIG. 4 .

Referring to FIG. 6 , a substrate 101 included in a memory device 100 according to an exemplary embodiment may include first to third regions 102 , 103 , and 104 . The first to third regions 102, 103, and 104 may have the same or different crystal structures, and in one embodiment, all of the first to third regions 102, 103, and 104 may include polysilicon. can

As described above, at least one of a plurality of layers included in the gate insulating layer 160 may be connected to each other on the upper surface of the substrate 101 . Referring to FIG. 6 , the blocking layer 162 , the charge storage layer 164 , and the tunneling layer 166 surround the channel layers 110 and extend in a direction perpendicular to the upper surface of the substrate 101 . and a horizontal area disposed parallel to the upper surface of the substrate 101 . Vertical regions of the charge storage layer 164 and the tunneling layer 166 disposed on outer surfaces of the different channel layers 110 may be connected to each other by the horizontal regions.

Meanwhile, at least a portion of the gate insulating layer 160 may be disposed below the buried insulating layer 115 as the remaining regions 162a, 164a, and 166a. The number of layers included in the remaining regions 162a, 164a, and 166a may be equal to or smaller than the number of layers included in the horizontal region. In the embodiment shown in FIG. 6 , the remaining regions 162a, 164a, and 166a are partially formed by the blocking layer 162, the charge storage layer 164, and the tunneling layer 166 in the manufacturing process. ) can be formed by remaining under

The plurality of channel layers 110 may extend in a direction (Z-axis direction) perpendicular to the upper surface of the substrate 101 . Also, the memory device 100 according to an embodiment of the present invention may include a horizontal channel layer 110h connecting the plurality of channel layers 110 to each other. The horizontal channel layer 110h may connect the plurality of channel layers 110 to each other under the plurality of gate electrode layers 130 and the insulating layer 140 . In one embodiment, the horizontal channel layer 110h may directly contact the second region 103 of the substrate 101, similarly to the first to third regions 102, 103, and 104 of the substrate 101. It may contain polysilicon. The horizontal channel layer 110h is present in a horizontal region of the gate insulating layer 160 parallel to the upper surface of the substrate 101, for example, below the horizontal region of the charge storage layer 164, and can come into direct contact with Therefore, in the memory device 100 according to an embodiment of the present invention, each of the plurality of channel layers 110 may be connected to the substrate 101 through the horizontal channel layer 110h. Meanwhile, the horizontal region of the gate insulating layer 160 may be formed so as not to extend to the lower surface of the horizontal channel layer 110h.

7 is a cross-sectional view showing a cross-section in a direction II-I' of FIG. 3, and FIG. 8 is a cross-sectional view showing a cross-section in a direction II-II' of FIG.

Referring to FIGS. 7 and 8 , a memory device 100 according to an exemplary embodiment of the present invention includes a plurality of gate structures (GS) each having a plurality of gate electrode layers 131 to 138 and a plurality of insulating layers 141 to 149 . ) may be included. The plurality of gate structures GS are disposed on the substrate 101 to be separated from each other by a common source line, and the plurality of gate electrode layers 131 to 138 included in each of the plurality of gate structures GS and the plurality of insulation layers Layers 141-149 may be stacked alternately with each other.

An interlayer insulating layer 170 may be disposed on the plurality of gate structures GS. The interlayer insulating layer 170 is formed of an insulating material such as silicon nitride or silicon oxide, and may also be formed over the peripheral circuit element 180 provided in the peripheral circuit area. The peripheral circuit element 180 may be covered by the lower interlayer insulating layer 171 , and the interlayer insulating layer 170 may be disposed on the lower interlayer insulating layer 171 .

The peripheral circuit element 180 may include a horizontal transistor, and may include a peripheral source/drain region 181, a peripheral gate electrode 182, a peripheral gate insulating layer 183, a peripheral spacer 184, and the like. . The peripheral gate electrode 182 and the peripheral source/drain region 181 may be connected to the contact 185 .

The plurality of channel layers 110 may pass through each of the plurality of gate structures GS and may be connected to each other by a horizontal channel layer 110h provided under each of the plurality of gate structures GS. The plurality of channel layers 110 may be directly connected to the substrate 101 under the gate structure GS.

Horizontal regions of the blocking layer 162 , the charge storage layer 164 , and the tunneling layer 166 may be positioned between the horizontal channel layer 110h and the gate structure GS. The horizontal region may not extend to a lower portion of the horizontal channel layer 110h. In some embodiments, the horizontal channel layer 110h may not exist below the horizontal area.

The substrate 101 may include first to third regions 102 , 103 , and 104 . As described above, the first to third regions 102 , 103 , and 104 may be regions formed at different stages in the process, and may include the same or different materials. In one embodiment, all of the first to third regions 102, 103, and 104 may include polysilicon.

In the memory device 100 according to an embodiment of the present invention, the substrate 101 may include a plurality of support regions 105 protruding from the bottom of the common source line 150 . The plurality of support regions 105 may be provided to prevent the gate structure GS from collapsing during a manufacturing process. The plurality of support regions 105 may have a larger width than the common source line 150 in a second direction (Y-axis direction) perpendicular to the first direction (X-axis direction), as shown in FIGS. 4 and 5 . As shown, it may be disposed separately from each other along the first direction (X-axis direction). The plurality of support regions 105 may be disposed between the first region 102 and the third region 104 of the substrate 101 .

Meanwhile, the substrate 101 may have an impurity region containing carbon. In one embodiment, a partial upper region of the first region 102 adjacent to the interface with the second region 103 may include carbon. (That is, a partial upper region of the first region 102 may be a carbon doped region.) Also, the third region 104 may include carbon. (That is, the third region 104 may be a carbon doped region.) The width of the third region 104 in the second direction (Y-axis direction) is the second region of the carbon doped region of the first region 102. It may be smaller than the width in the direction (Y-axis direction). By including carbon in a partial region of the substrate 101, it is possible to prevent the substrate 101 from being etched unintentionally during a manufacturing process.

7 and 8, due to the support region 105 having a plurality of regions disposed along the X-axis direction, the common source line 150 ) can have different heights. The bottom of the common source line 150 in the II-II' direction cross section may be located at a higher level than the bottom surface of the common source line 150 in the II' direction cross section. Accordingly, the common source line 150 may have a plurality of regions having different heights in a direction perpendicular to the top surface of the substrate 101 (Z-axis direction), and the plurality of regions may have different heights in a first direction (X-axis direction). can be arranged alternately along A region having a relatively small height among the plurality of regions may be a region disposed on the plurality of support regions 105 . Meanwhile, the source region 108 may also have a curved upper surface along the first direction (X-axis direction) due to the plurality of support regions 105 .

9 is a cross-sectional view showing a cross-section in a direction II-II' in FIG. 3, and FIG. 10 is a cross-sectional view showing a cross-section in a direction II-II' in FIG.

In the embodiment shown in FIGS. 9 and 10 , the substrate 101' may include at least one void Vo formed therein. A void Vo may be formed in the second region 103'. 6 to 8, the remaining regions 162a, 164a, and 166a of the gate insulating layer 160 provided between the buried insulating layer 115 and the first region 102 are shown in Figs. In the embodiment shown in FIG. 10, it may not exist. This may be a structural difference that occurs in the manufacturing process of forming the second region 103'. The void Vo may be formed in the horizontal channel layer 110h as well as in the second region 103'.

11 is a perspective view illustrating a memory device according to an exemplary embodiment of the present invention.

In the embodiment shown in FIG. 11 , the memory device 200 may have a Cell-On-Peri (COP) structure. A peripheral circuit area including the peripheral circuit element 280 may be disposed below a cell area including memory cells MC1 -MCn. In the peripheral circuit area, the peripheral circuit element 280 is disposed on the second substrate 207 and may be buried in the second interlayer insulating layer 271 . The source/drain region 281 and the horizontal gate electrode layer 282 included in the peripheral circuit element 280 may be connected to the wiring pattern 285 . The second interlayer insulating layer 271 may be formed of silicon oxide, silicon nitride, or the like.

The cell region includes a first substrate 201 , and the first substrate 201 may be disposed on a top surface of the second interlayer insulating layer 271 . The cell region may include a plurality of gate electrode layers 231 to 238 (230), a plurality of channel layers 210, and the like, and may provide a plurality of memory cells MC1 to MCn. The plurality of gate electrode layers 230 are divided into a plurality of unit regions by a common source line 250 , and the common source line 250 may include first and second regions 251 and 252 .

Referring to FIG. 11 , the first area 251 may have a height smaller than that of the second area 252, and the first area 251 and the second area 252 travel in the first direction (X-axis direction). can be arranged alternately. The first region 251 is provided on the plurality of support regions 205 protruding from the lower part of the common source line 250, and has a height smaller than that of the second region 252 by the thickness of the plurality of support regions 205. can have The common source line 250 may be connected to a source region 208 provided in the substrate 201, and the source region 208 may have a curved upper surface along the first direction due to the plurality of support regions 205. there is.

12 to 59 are diagrams provided to describe a method of manufacturing a memory device according to an embodiment of the present invention. 12, 14, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 42, 45, 48, 51, 54, and 57 are steps of a method of manufacturing a memory device according to the present invention. These are floor plans provided for illustrative purposes. 13, 15, 17, 19, 21, and 25 are cross-sections in a direction IV-IV' of FIGS. 12, 14, 16, 18, 20, and 22, respectively, and FIG. 26 is a view in a direction V-V' of FIG. It is a drawing showing cross-sections of. 28. 31, 34, 37, 40, 43, 46, 49, 52, 55 and 58 are IV-IV' of FIGS. 7, 30, 33, 36, 39, 42, 45, 48, 51, 54 and 57 These are drawings each showing a cross section in the direction. 29, 32, 35, 38, 41, 44, 47, 50, 53, 56 and 59 are VI-VI' of FIGS. 7, 30, 33, 36, 39, 42, 45, 48, 51, 54 and 57 These are drawings each showing a cross section in the direction.

Referring first to FIGS. 12 and 13 , a peripheral circuit element 380 may be formed on the first region 302 in the peripheral circuit region P. The peripheral circuit element 380 may include a peripheral source/drain region 381 , a peripheral gate electrode layer 382 , a peripheral gate insulating layer 383 , a peripheral spacer 384 , and the like. The peripheral circuit element 380 may be covered by the lower interlayer insulating layer 371, and in one embodiment, the lower interlayer insulating layer 371 includes a high density plasma (HDP) oxide film having excellent gap filling characteristics. can do.

The first region 302 may be a partial region of a substrate for manufacturing a memory device and may include a semiconductor material. In one embodiment, the first region 302 may include polysilicon. Referring to FIGS. 12 and 13 , a first impurity region C1 may be formed by implanting carbon into a portion of the upper surface of the first region 302 . The first impurity region C1 implanted with carbon may have a lower etch rate in the wet etching process than other regions.

Next, referring to FIGS. 14 and 15 , first and second sacrificial layers 303A and 303B may be formed on the first region 302 . The first and second sacrificial layers 303A and 303B may be formed of an insulating material, and in an embodiment, the first sacrificial layer 303A may include silicon oxide and the second sacrificial layer 303B may include silicon nitride. there is. Meanwhile, the second sacrificial layer 303B may have a greater thickness than the first sacrificial layer 303A, but is not necessarily limited to such a structure.

Referring to FIGS. 16 and 17 , a first mask layer M1 having a plurality of first openings OP1 may be formed on an upper surface of the second sacrificial layer 303B. As shown in FIG. 16 , the plurality of first openings OP1 may be separated from each other. After the first mask layer M1 is formed, the first and second sacrificial layers 303A and 303B exposed in the plurality of first openings OP1 are removed to form the first region in the plurality of first openings OP1. (302) can be exposed.

Referring to FIGS. 18 and 19 , after the first mask layer M1 is removed, polysilicon may be deposited to form a first polysilicon layer 305A. Regions from which the first and second sacrificial layers 303A and 303B are removed in the process described with reference to FIGS. 16 and 17 may be filled with the first polysilicon layer 305A. Thereafter, by performing a polishing process (CMP) on the first polysilicon layer 305A, a plurality of support regions 305 may be formed as shown in FIGS. 20 and 21 . As shown in FIG. 20 , the plurality of support regions 305 may be separated from each other on the upper surface (X-Y plane) of the first region 302 . As described with reference to FIGS. 16 to 19 , a position of each of the plurality of support regions 305 may correspond to a position of each of the plurality of first openings OP1 of the first mask layer M1 . Meanwhile, upper surfaces of the plurality of support regions 305 and upper surfaces of the second sacrificial layer 303B may form a co-planar surface.

Referring to FIGS. 22 and 23 , a second polysilicon layer 304A may be formed on upper surfaces of the plurality of support regions 305 and the second sacrificial layer 303B. In one embodiment, the second polysilicon layer 304A may have a thickness of several hundred angstroms.

Next, referring to FIGS. 24 to 26 , a second mask layer M2 having a plurality of second openings OP2 may be formed on the upper surface of the second polysilicon layer 304A. Then, the second impurity region C2 may be formed by implanting carbon as an impurity through the plurality of second openings OP2 .

Referring to FIG. 25 , the second impurity region C2 may be positioned above the plurality of support regions 305 . Also, referring to FIG. 26 , the second impurity region C2 may extend along the first direction (X-axis direction). That is, unlike the plurality of support regions 305 that are separated and disposed along the first direction, the second impurity region C2 may be a region that continuously extends along the first direction.

27 to 29, a plurality of sacrificial layers (321-328: 320) and a plurality of insulating layers (341-347: 340) may be alternately stacked on the upper surface of the second polysilicon layer (304A). . In one embodiment, before forming the plurality of sacrificial layers 320 and the plurality of insulating layers 340, the first and second sacrificial films 303A and 303B and the second polysilicon layer are formed in the peripheral circuit region P. (304A) may be eliminated. The number and thickness of the plurality of sacrificial layers 120 and the insulating layer 140 may be variously modified according to embodiments, and in one embodiment, the number of sacrificial layers 320 may be a ground selection transistor included in a memory device, It may be equal to the sum of the numbers of string select transistors, memory cells, and dummy transistors.

The plurality of sacrificial layers 320 and the insulating layer 340 extend in different lengths along directions parallel to the upper surface of the second polysilicon layer 304A (X-axis and Y-axis directions in FIGS. 27 to 29), A step structure having a step difference may be formed. The step structure may be formed adjacent to the peripheral circuit area P. After the step structure is formed, an interlayer insulating layer 370 may be formed on the plurality of sacrificial layers 320 and the insulating layer 340 . In the peripheral circuit region P, the interlayer insulating layer 370 may be provided on the lower interlayer insulating layer 371 . The interlayer insulating layer 370 includes an insulating material such as silicon oxide or silicon nitride, and may include a high density plasma (HDP) oxide film or a tetra-ethyl-ortho-silicate (TEOS) oxide film.

Meanwhile, an isolation insulating layer 355 may be provided in the cell region C. The isolation insulating layer 355 may extend along the first direction (X-axis direction), extend from the upper surface of the interlayer insulating layer 370 in the cell region C to form a portion of the sacrificial layer 328 in a plurality of regions. can be separated by The sacrificial layer 328 separated into a plurality of regions by the isolation insulating layer 355 may be replaced with a gate electrode layer of a string select transistor later.

Next, referring to FIGS. 30 to 32 , a plurality of channel holes (CHH) and a plurality of dummy channel holes (DCHH) penetrating the plurality of sacrificial layers 320, the insulating layer 340, and the interlayer insulating layer 370. ) can be formed. The plurality of channel holes CHH and the plurality of dummy channel holes DCHH may be formed in a channel structure and a region for forming the dummy channel structure, and as shown in FIGS. 31 and 32, the second polysilicon layer ( 304A) and the first and second sacrificial layers 303A and 303B. Accordingly, the first region 302 may be exposed through the plurality of channel holes CHH and the plurality of dummy channel holes DCHH. As the number of sacrificial layers 320 and insulating layers 340 increases, each of the plurality of channel holes CHH and the plurality of dummy channel holes DCHH is formed along the depth direction (Z-axis direction) of the second poly It may have a tapered shape having a narrower width as it approaches the silicon layer 304A.

Referring to FIG. 30 , the plurality of channel holes CHH may be arranged to be separated from each other in an area in which the plurality of support areas 305 included in the substrate 101 are not formed. Meanwhile, the plurality of dummy channel holes DCHH may be formed at positions penetrating the isolation insulating layer 355 . A dummy channel structure may be formed in the dummy channel hole DCHH passing through the isolation insulating layer 355 in a subsequent process.

Next, referring to FIGS. 33 to 35 , a wet etching process may be performed through a plurality of channel holes CHH and a plurality of dummy channel holes DCHH. A partial region of the second polysilicon layer 304A exposed by the plurality of channel holes CHH and the plurality of dummy channel holes DCHH may be removed by the wet etching. Referring to FIGS. 34 and 35 , a portion remaining in the second polysilicon layer 304A that is not removed by the wet etching may serve as a third region 304 . A plurality of support regions 305 or first and second sacrificial layers 303A and 303B may be disposed between the third region 304 and the first region 302 .

The remaining third region 304 that is not removed by the wet etching may correspond to the second impurity region C2 formed by implanting carbon. That is, the width (length in the Y-axis direction) of the third region 304 may be substantially equal to the width of the second impurity region C2. When carbon is implanted into polysilicon, it may have a relatively slow etch rate compared to polysilicon in which carbon is not implanted. Therefore, by implanting carbon into the region to be left as the third region 304 in advance to form the second impurity region C2, at least a portion of the second polysilicon layer 304A is removed during the wet etching process. The third region 304 may be formed by remaining.

Meanwhile, the third opening OP3 may be formed by removing the second polysilicon layer 304A from the area other than the third area 304 . The plurality of channel holes CHH may be connected to each other by the third opening OP3 formed between the plurality of sacrificial layers 320 and the second sacrificial film 303B.

Next, referring to FIGS. 36 to 38 , a channel structure CH and a dummy channel structure DCH may be formed in the plurality of channel holes CHH and the plurality of dummy channel holes DCHH, respectively. As described above, the dummy channel structure DCH may be formed in the dummy channel hole DCHH passing through the isolation insulating layer 355 . However, the number and location of the dummy channel structures DCH and channel structures CH are not limited to those shown in FIGS. 36 to 38 and may be variously modified.

37 and 38, the gate insulating layer 360, the channel layer 310, the filling insulating layer 315, and the drain region 313 are filled in the plurality of channel holes CHH, thereby filling the channel structure CH. ) can be formed. The dummy channel structure (DCH) may also have a structure similar to that of the channel structure (CH).

The process of forming the channel structure CH and the dummy channel structure DCH may begin with forming the plurality of channel holes CHH and the gate insulating layer 360 in the plurality of dummy channel holes DCHH. The gate insulating layer 360 may include a blocking layer 362, a charge storage layer 364, and a tunneling layer 366 that are sequentially formed, and may include a plurality of channel holes (CHH) and a plurality of channel holes (CHH) by an ALD or CVD process. Part of the space inside the plurality of dummy channel holes DCHH may be filled. Referring to FIGS. 37 and 38 , the gate insulating layer 360 may also be formed in the third opening OP3 connecting the plurality of channel holes CHH to each other. Accordingly, a portion of the gate insulating layer 360 may contact the first region 302 under the plurality of channel holes CHH.

In one embodiment, the blocking layer 362 may include a high-k dielectric. Here, the high-k dielectric may mean a dielectric material having a higher dielectric constant than the silicon oxide layer. The tunneling layer 366 may transfer charges to the charge storage layer 364 by F-N tunneling. The tunneling layer 366 may include, for example, silicon oxide.

In one embodiment, the blocking layer 362 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a high-k dielectric material. The high-k dielectric material includes aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon. Oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ). 36 to 38, the blocking layer 362 is illustrated as including one layer, but may include a high dielectric constant layer and a low dielectric constant layer having different dielectric constants. In this case, a low dielectric constant layer may be disposed close to the charge storage layer 364 . The high-permittivity layer may be made of a material having a higher permittivity than the tunneling layer 366, and the low-permittivity layer may be made of a material having a relatively smaller dielectric constant than the high-permittivity layer. By disposing the low-permittivity layer on the side of the high-permittivity layer, it is possible to improve characteristics of the nonvolatile memory device, such as erase characteristics, by controlling an energy band such as a barrier height.

The charge storage layer 364 may be a charge trap layer or a floating gate conductive layer. When the charge storage layer 364 is a floating gate conductive film, it may be formed by depositing polysilicon by, for example, LPCVD (Low Pressure Chemical Vapor Deposition). When the charge storage layer 164 is a charge trap layer, a dielectric material such as silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), Zirconium oxide (ZrO ₂ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), hafnium aluminum oxide (HfAl _x O _y ), hafnium tantalum oxide (HfTa _x O _y ), hafnium silicon oxide (HfSi _x O _y ), aluminum nitride (Al _x N _y ), and aluminum gallium nitride (AlGa _x N _y ). In some embodiments, the charge storage layer 364 may include quantum dots or nanocrystals. Here, quantum dots or nanocrystals may be composed of fine particles of a conductor, for example, a metal or semiconductor.

The tunneling layer 366 includes silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), aluminum oxide (Al). ₂ O ₃ ), and zirconium oxide (ZrO ₂ ).

The channel layer 310 may be formed inside the gate insulating layer 360 and may include polysilicon. In one embodiment, the channel layer 310 may be formed inside the tunneling layer 366 formed last among the plurality of layers included in the gate insulating layer 360 . The channel layer 310 may have a thickness of about 1/50 to 1/5 the diameter of the channel hole (CHH), and may be formed by an ALD or CVD process similar to the gate insulating layer 360 .

The channel layer 310 may have a cylindrical shape with an empty inside, and a filling insulating layer 315 may be formed inside the channel layer 310 . Optionally, before forming the filling insulating layer 315, a hydrogen annealing step of heat-treating the structure on which the channel layer 310 is formed in a gas atmosphere containing hydrogen or deuterium may be further performed. Many of the crystal defects existing in the channel layer 310 may be healed by the hydrogen annealing step. Next, a drain region 313 may be formed on the channel layer 310 with a conductive material such as polysilicon.

As shown in FIGS. 37 and 38 , a horizontal channel layer 310h may be formed while partially filling the space of the third opening OP3 that is not yet filled by the gate insulating layer 360 . The horizontal channel layer 310h is a region extending from the channel layer 310 and may include polysilicon like the channel layer 310 . Accordingly, the plurality of channel layers 310, which appear to be separated from each other on the X-Y plane, may actually be provided as one area connected to each other by the horizontal channel layer 310h.

Referring to FIGS. 39 to 41 , word line cuts WC may be formed. The word line cut WC may be formed in a region where a common source line is formed in a subsequent process. In particular, as shown in FIGS. 39 to 41 , the third region 304 may be exposed on the lower surface of the word line cut WC, and the plurality of sacrificial layers 320 on the inner side of the word line cut WC. ) and the plurality of insulating layers 340 may be exposed.

Next, referring to FIGS. 42 to 44 , after forming the poly spacer 306 with polysilicon on the inner side of the word line cut WC, an additional etching process may be performed in the inner space of the word line cut WC. there is. The additional etching process may be performed by dry etching, and a trench RCS may be additionally formed under the word line cut WC. The trench RCS may extend from the word line cut WC and be formed to a depth capable of exposing the plurality of support regions 305 and the second sacrificial layer 303B. In some embodiments, the trench RCS may be formed without forming the poly spacer 306 .

Referring to FIGS. 45 to 47 , the substrate opening OPS may be formed by removing the first and second sacrificial layers 303A and 303B through the word line cut WC and the trench RCS. The second sacrificial layer 303B exposed through the word line cut WC and the trench RCS may be first removed, and then the first sacrificial layer 303A may be removed. By removing the first and second sacrificial layers 303A and 303B, some surfaces of the first region 302, the third region 304, and the plurality of support regions 305 are exposed within the substrate opening OPS. can When the substrate opening OPS is formed, the plurality of sacrificial layers 320 and the insulating layer 340 may be supported without collapsing by the plurality of support regions 305 .

Meanwhile, a gate disposed below the horizontal channel layer 310h in a process of removing the first and second sacrificial films 303A and 303B or in an etching process additionally performed after removing the second sacrificial film 303B. The insulating layer 360 may be removed. At this time, the gate insulating layer 360 may also be removed from the sidewall of the horizontal channel layer 310h. In an embodiment, when the second sacrificial layer 303B is first removed by the first etching process performed through the word line cut WC and the trench RCS, the region from which the second sacrificial layer 303B is removed Through this, the gate insulating layer 360 may be exposed to the outside. The first sacrificial layer 303A and some layers of the gate insulating layer 360, for example, the blocking layer 362, may be removed together by a second etching process performed after the first etching process is completed. The blocking layer 362 may be removed from the lower portion of the horizontal channel layer 310h by the secondary etching process. At this time, the blocking layer 362 may also be removed from the sidewall of the horizontal channel layer 310h.

After the secondary etching process is completed, the charge storage layer 364 and the tunneling layer 366 disposed under the horizontal channel layer 310h may be removed by performing a third etching process. At this time, the charge storage layer 364 and the tunneling layer 366 may also be removed from the sidewall of the horizontal channel layer 310h. Since at least some of the blocking layer 362, the charge storage layer 364, and the tunneling layer 366 may include different materials, the horizontal channel layer 310h is formed by performing a plurality of etching processes as illustrated above. ), the gate insulating layer 360 may be removed. When the gate insulating layer 360 is removed from the lower portion of the horizontal channel layer 310h, a portion of the gate insulating layer 360 may remain between the first region 302 and the horizontal channel layer 310h. That is, a portion of the gate insulating layer 360 (ie, the blocking layer 362, the charge storage layer ( 364) and each part of the tunneling layer 366) may remain. Meanwhile, the gate insulating layer 360 may remain on the upper surface of the horizontal channel layer 310h to serve as a horizontal region. Vertical regions of the gate insulating layer 360 disposed to surround the outside of the channel layer 310 may be connected to each other by the horizontal region.

Next, referring to FIGS. 48 to 50 , the substrate opening OPS may be filled with polysilicon through the word line cut WC. The polysilicon layer 303C formed to fill the substrate opening OPS fills not only the substrate opening OPS but also the trench RCS and may be partially formed inside the word line cut WC. Meanwhile, as described above with reference to FIGS. 9 and 10 , in the process of filling the substrate opening OPS with polysilicon, a void Vo may be formed inside the polysilicon layer 303C. By filling the substrate opening OPS with polysilicon, the first region 302 and the third region 304, the channel layer 310, and the horizontal channel layer 310h may be connected to each other. The polysilicon filling the substrate opening OPS may be polysilicon that is not doped with impurities.

Referring to FIGS. 51 to 53 , an etching process may be performed through the word line cut WC. The etching process may be a process for selectively removing polysilicon. Through the etching process, the polysilicon layer 303C and the poly spacer 306 formed inside the word line cut WC may be removed. At this time, the polysilicon layer 303C under the word line cut WC may also be removed. Meanwhile, since the first region 302 and the third region 304 contain carbon as an impurity, they may not be removed during the etching process. By removing the polysilicon layer 303C formed inside and below the word line cut WC and the poly spacer 306 formed inside the word line cut WC by the etching process, a plurality of pluralities are formed on the inner side of the word line cut WC. The sacrificial layer 320 and the insulating layer 340 may be exposed, and the plurality of support regions 305 and/or the first region 302 may be exposed on the bottom surface of the trench RCS. In addition, the polysilicon layer 303C may remain in the substrate opening OPS to form the second region 303 . For example, the second region 303 may be a region formed by filling the substrate opening OPS formed by removing the first and second sacrificial layers 303A and 303B with polysilicon.

As a result, the substrate 301 including the first to third regions 302 , 303 , and 304 and a plurality of support regions 305 may be formed. The first region 302 and the third region 304 may be connected to the channel layer 310 and the horizontal channel layer 310h by the second region 303 .

When forming a channel layer by a general process, a channel hole is formed, an epitaxial layer is grown therein, and then a gate insulating layer is formed. At this time, since the upper surface of the epitaxial layer is covered by the gate insulating layer, an etching process may be performed to expose the upper surface of the epitaxial layer, and then a channel layer may be formed again. However, if the top surface of the epitaxial layer is not sufficiently exposed, a defect in which the epitaxial layer and the channel layer are not connected may occur. Therefore, a sufficient diameter of the channel hole must be secured. This may degrade the overall degree of integration of the memory device.

In the present invention, the channel layer 310 may be directly connected to the substrate 301 without a process of growing an epitaxial layer. In particular, in forming the channel layer 310 , a process of forming the channel layer 310 after removing a portion of the gate insulating layer 360 formed in the channel hole CHH may be omitted. In an embodiment of the present invention, as described with reference to FIGS. 36 to 38 , the gate insulating layer 360 may be formed in the channel hole CHH, and then the channel layer 310 may be directly formed. In a subsequent process, a portion of the gate insulating layer 360 surrounding the channel layer 310 is removed, and the region from which the gate insulating layer 360 is removed is filled with polysilicon, thereby forming a horizontal area of the gate insulating layer 360. At the bottom, the horizontal channel layer 310h may directly contact the substrate 301 . Accordingly, by reducing the diameter of the channel hole CHH, the degree of integration of the memory device may be increased and reliability may be secured.

Next, referring to FIGS. 54 to 56, the plurality of gate electrode layers 331-338: 330 are formed by selectively removing the plurality of sacrificial layers 320 exposed through the word line cut WC and filling them with a conductive material. ) can be formed. The gate electrode layer 330 may include a metal, polycrystalline silicon, or metal silicide material. The metal silicide material may be, for example, a silicide material of a metal selected from CoSi, NiSi, HfSi, PtSi, WSi, and TiSi, or a combination thereof. When the gate electrode layer 330 is made of a metal silicide material, silicon (Si) is buried in the region from which the plurality of sacrificial layers 320 are removed, and then a separate metal layer is formed to perform a silicidation process, thereby forming the gate electrode layer ( 330) can be formed. Meanwhile, in one embodiment, the gate electrode layer 330 may include a plurality of metal layers, such as a TiN layer and a W layer. According to some embodiments, before the gate electrode layer 330 is formed, an additional blocking layer similar to the additional blocking layer 168 shown in FIG. 6 may be formed in a region from which the sacrificial layer 320 is removed. Accordingly, the additional blocking layer may cover the gate electrode layer 330 .

When the plurality of gate electrode layers 330 are formed, spacers 309 are formed on the inner side surfaces of the word line cut WC as shown in FIGS. 57 to 59, and the substrate 301, for example, the first region ( 302 ) and the plurality of support regions 305 may be implanted with impurities to form the source region 308 . Source region 308 may include N-type impurities in one embodiment. After forming the source region 308 , the common source line 350 may be formed by filling the space between the spacers 309 with a conductive material.

60 is a block diagram illustrating an electronic device including a memory device according to an embodiment of the present invention.

Referring to FIG. 60 , an electronic device 1000 according to an embodiment may include a communication unit 1010, an input unit 1020, an output unit 1030, a memory 1040, and a processor 1050.

The communication unit 1010 may include a wired/wireless communication module, and may include a wireless Internet module, a short-distance communication module, a GPS module, a mobile communication module, and the like. The wired/wireless communication module included in the communication unit 1010 may transmit/receive data by being connected to an external communication network according to various communication standards.

The input unit 1020 is a module provided for the user to control the operation of the electronic device 1000, and may include a mechanical switch, a touch screen, a voice recognition module, and the like. In addition, the input unit 1020 may include a mouse or finger mouse device operating in a track ball or laser pointer method, and may further include various sensor modules through which a user may input data.

The output unit 1030 outputs information processed by the electronic device 1000 in the form of audio or video, and the memory 1040 may store a program or data for processing and control of the processor 1050. . The memory 1040 may include one or more of the memory devices 100, 200, and 300 according to various embodiments described above, and the processor 1050 transmits a command to the memory 1040 according to a necessary operation to store data. Or you can withdraw.

The memory 1040 may be embedded in the electronic device 1000 or may communicate with the processor 1050 through a separate interface. When communicating with the processor 1050 through a separate interface, the processor 1050 may store or retrieve data from the memory 1040 through various interface standards such as SD, SDHC, SDXC, MICRO SD, and USB. .

The processor 1050 may control the operation of each part included in the electronic device 1000 . The processor 1050 may perform control and processing related to voice calls, video calls, and data communications, or control and processing for multimedia reproduction and management. Also, the processor 1050 may process input transmitted from the user through the input unit 1020 and output the result through the output unit 1030 . Also, as described above, the processor 1050 may store data necessary for controlling the operation of the electronic device 1000 in the memory 1040 or retrieve it from the memory 1040 .

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

100, 200, 300: memory device
102, 202, 302: first area
103, 203, 303: second region
104, 204, 304: third region
105, 205, 305: support area
110, 210, 310: channel layer
130, 230, 330: gate electrode layer
140, 240, 340: insulating layer
160, 260, 360: gate insulating layer

Claims (20)

a plurality of gate electrode layers stacked on an upper surface of the substrate;
a plurality of channel layers passing through the plurality of gate electrode layers;
a gate insulating layer provided between the plurality of channel layers and the plurality of gate electrode layers;
a horizontal channel layer extending from the plurality of channel layers, disposed below the plurality of gate electrode layers, and extending parallel to the upper surface of the substrate, and connecting at least a portion of the plurality of channel layers to each other; and
A common source including first and second regions alternately disposed along a first direction parallel to the upper surface of the substrate, having different heights in a direction perpendicular to the upper surface of the substrate, and adjacent to the plurality of gate electrode layers. line; including,
The gate insulating layer includes a plurality of vertical regions surrounding each of the plurality of channel layers, and a horizontal region extending parallel to the upper surface of the substrate and disposed below the plurality of gate electrode layers,
The memory device of claim 1 , wherein an upper surface of at least a partial region of the horizontal channel layer contacts the horizontal region and a lower surface of the at least partial region contacts the substrate.
According to claim 1,
The memory device of claim 1 , further comprising a source region disposed under the common source line and having a curved surface along the first direction.
According to claim 1,
The substrate includes a plurality of support regions protruding toward the common source line under the first region, the plurality of support regions being separated from each other in the first direction.
According to claim 3,
The first region of the common source line is disposed on the plurality of support regions, and the plurality of support regions have a width greater than that of the common source line in a second direction perpendicular to the first direction.
According to claim 4,
The first area has a height smaller than that of the second area.
According to claim 3,
Upper surfaces of the plurality of support regions contact lower surfaces of the first region.
According to claim 1,
A horizontal region of the gate insulating layer extends from the plurality of vertical regions of the gate insulating layer to connect at least a portion of the plurality of vertical regions to each other.
delete According to claim 1,
The plurality of channel layers are connected to the substrate by the horizontal channel layer.
delete According to claim 1,
The substrate includes at least one void formed under the horizontal channel layer.
According to claim 1,
The substrate is disposed adjacent to the horizontal channel layer and has an impurity region containing carbon.
According to claim 1,
Further comprising a buried insulating layer surrounded by each of the plurality of channel layers and extending in a direction perpendicular to the upper surface of the substrate,
The buried insulating layer extends deeper into the substrate than the plurality of channel layers.
a plurality of gate structures each having a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on an upper surface of the substrate;
a plurality of channel layers extending in a direction perpendicular to the upper surface of the substrate and penetrating the plurality of gate structures;
a charge storage layer having a plurality of vertical regions respectively disposed outside the plurality of channel layers of each gate structure and a horizontal region extending from the plurality of vertical regions and disposed below each of the gate structures; and
a horizontal channel layer connecting the plurality of channel layers to each other under the charge storage layer and contacting the substrate; Including,
The horizontal area is present only on the upper surface of the horizontal channel layer.
According to claim 14,
The plurality of vertical regions are connected to each other by the horizontal region.
delete According to claim 14,
The memory device of claim 1 , further comprising a common source line disposed between the plurality of gate structures, wherein the common source line extends along a first direction parallel to an upper surface of the substrate.
According to claim 17,
The common source line has first and second regions having different heights, and the first and second regions are alternately disposed along the first direction.
a plurality of gate structures each including a plurality of gate electrode layers disposed on an upper surface of the substrate;
A plurality of channel layers extending in a direction perpendicular to the upper surface of the substrate, passing through the plurality of gate electrode layers of each gate structure, and connected to the substrate by a horizontal channel layer disposed under the plurality of gate electrode layers. ;
a charge storage layer including a vertical area disposed between the plurality of channel layers and the plurality of gate electrode layers and a horizontal area contacting an upper surface of the horizontal channel layer; and
a common source line disposed between the plurality of gate structures and extending along a first direction parallel to the upper surface of the substrate; Including,
The substrate includes a first impurity region disposed under the horizontal channel layer and a second impurity region disposed between the common source line and the horizontal channel layer, the first and second impurity regions comprising carbon ( A memory device comprising carbon).
According to claim 19,
Further comprising a buried insulating layer surrounded by each of the plurality of channel layers and extending in a direction perpendicular to the upper surface of the substrate,
The buried insulating layer extends deeper into the substrate than the plurality of channel layers.

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