KR102450572B1 - Memory device - Google Patents

Abstract

A memory device according to an embodiment of the present invention includes a cell region having a channel region extending in a direction perpendicular to a top surface of a substrate, and a plurality of gate electrode layers stacked on a substrate so as to be adjacent to the channel region, and A first active region disposed around and a second active region having an area larger than the first active region, a plurality of first contacts connected to the first active region, and a plurality of first contacts connected to the second active region and a peripheral circuit region having two contacts, wherein a spacing between the plurality of first contacts is smaller than a spacing between the plurality of second contacts.

Description

memory device {MEMORY DEVICE}

The present invention relates to a memory device.

Electronic products require high-capacity data processing while their volume is getting smaller. Accordingly, it is necessary to increase the degree of integration of semiconductor memory devices used in such electronic products. As one of methods for improving the degree of integration of a semiconductor memory device, a memory device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to improve reliability by preventing breakage of an interlayer insulating layer in a memory device having a vertical structure.

A memory device according to an embodiment of the present invention includes a cell region including a channel region extending in a direction perpendicular to a top surface of a substrate, and a plurality of gate electrode layers stacked on a substrate to be adjacent to the channel region, and the cell region a first active region disposed on the periphery of the , a second active region having an area larger than the first active region, a plurality of first contacts connected to the first active region, and a plurality of contacts connected to the second active region and a peripheral circuit region having a second contact, wherein a spacing between the plurality of first contacts is smaller than a spacing between the plurality of second contacts.

A memory device according to an embodiment of the present invention includes a plurality of memory cell devices stacked on a top surface of a substrate, first and second active regions disposed around the plurality of memory cell devices, and connected to the first active region and a plurality of first contacts disposed along a predetermined first interval, and a plurality of second contacts connected to the second active region and disposed along a second interval greater than the first interval.

A memory device according to an embodiment of the present invention includes a substrate, a channel region extending in a direction perpendicular to a top surface of the substrate, a plurality of gate electrode layers adjacent to the channel region and stacked on the substrate, and the plurality of gate electrode layers a plurality of peripheral circuit elements disposed on the periphery, and an interlayer insulating layer disposed on the plurality of gate electrode layers and the plurality of peripheral circuit elements, wherein the plurality of peripheral circuit elements have a first peripheral size smaller than a predetermined reference size. a circuit element and a second peripheral circuit element having a larger size than the reference size, wherein an interval between the plurality of first contacts connected to the first peripheral circuit element is a distance between the plurality of second contacts connected to the second peripheral circuit element. smaller than the gap between

According to the memory device according to the inventive concept, in forming the contact connected to the active region of the peripheral circuit element, the distance between the contacts is differently adjusted according to the size of the active region. For an active region larger than a certain reference value, by increasing the distance between the contacts, it is possible to prevent breakage of the interlayer insulating layer occurring in the space between the contacts and increase the reliability of the memory device.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic block diagram of a memory device according to an embodiment of the present invention.
2 is a circuit diagram illustrating a memory cell array of a memory device according to an embodiment of the present invention.
3 is a plan view illustrating a memory device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a cross section in a direction II′ of the memory device shown in FIG. 3 .
FIG. 5 is a partial perspective view illustrating a region A of the memory device shown in FIG. 3 .
6 is a plan view illustrating a memory device according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating a cross section in a direction II-II′ of the memory device shown in FIG. 6 .
8 to 23 are diagrams provided to explain a method of manufacturing the memory device illustrated in FIGS. 3 to 5 .
24 and 25 are block diagrams illustrating an electronic device including a memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Throughout the specification, when it is stated that one component, such as a film, region, or wafer (substrate), is located "on," "connected to," or "coupled to," another component, one of the components described above It may be construed that an element may be directly in contact with, “on,” “connected to,” or “coupled with,” another element, or that there may be other elements intervening therebetween. On the other hand, when it is stated that one element is located "directly on", "directly connected to," or "directly coupled to" another element, it is construed that there are no other elements interposed therebetween. do. Like numbers refer to like elements. As used herein, the term “and/or” includes any one and any combination of one or more of those listed items.

Although the terms first, second, etc. are used herein to describe various members, components, regions, layers, and/or portions, these members, components, regions, layers and/or portions are limited by these terms and thus It is self-evident that These terms are used only to distinguish one member, component, region, layer or portion from another region, layer or portion. Accordingly, a first member, component, region, layer, or portion discussed below may refer to a second member, component, region, layer or portion without departing from the teachings of the present invention.

Also, relative terms such as "above" or "above" and "below" or "below" may be used herein to describe the relationship of certain elements to other elements as illustrated in the drawings. It may be understood that relative terms are intended to include other orientations of the element in addition to the orientation depicted in the drawings. For example, if an element is turned over in the figures, elements depicted as being on the face above the other elements will have orientation on the face below the other elements described above. Thus, the term “top” by way of example may include both “bottom” and “top” directions depending on the particular orientation of the drawing. If the component is oriented in a different orientation (rotated 90 degrees relative to the other orientation), the relative descriptions used herein may be interpreted accordingly.

The terminology used herein is used to describe specific embodiments, not to limit the present invention. As used herein, the singular form may include the plural form unless the context clearly dictates otherwise. Also, as used herein, “comprise” and/or “comprising” refers to the presence of the recited shapes, numbers, steps, actions, members, elements, and/or groups of those specified. and does not exclude the presence or addition of one or more other shapes, numbers, movements, members, elements and/or groups.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically illustrating ideal embodiments of the present invention. In the drawings, variations of the illustrated shape can be envisaged, for example depending on manufacturing technology and/or tolerances. Accordingly, embodiments of the inventive concept should not be construed as limited to the specific shape of the region shown in the present specification, but should include, for example, changes in shape caused by manufacturing. The following embodiments may be configured by combining one or a plurality of them.

The content of the present invention described below may have various configurations, and only the necessary configurations are presented here as examples, and the content of the present invention is not limited thereto.

Referring to FIG. 1 , a semiconductor device 10 according to an exemplary embodiment may include a memory cell array 20 , a row decoder 30 , and a core logic circuit 55 . The core logic circuit 55 may include a read/write circuit 40 and a control circuit 50 .

The memory cell array 20 may include a plurality of memory cells arranged along a plurality of rows and columns. A plurality of memory cells included in the memory cell array 20 include a word line (WL), a common source line (CSL), a string select line (SSL), and a ground select line ( It may be connected to the row decoder 30 through a ground select line (GSL) or the like, and may be connected to the read/write circuit 40 through a bit line (BL). In an embodiment, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

A plurality of memory cells included in the memory cell array 20 may be divided into a plurality of memory blocks. Each memory block may include a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of bit lines BL, and at least one common source line CSL. can

The row decoder 30 receives the address information ADDR from the outside, decodes the received address information ADDR, and selects the word line WL, the common source line CSL, and the string connected to the memory cell array 20 . At least a portion of the line SSL and the ground selection line GSL may be selected.

The read/write circuit 40 may select at least a portion of the bit lines BL connected to the memory cell array 20 according to a command received from the control circuit 50 . The read/write circuit 40 may read data stored in memory cells connected to at least some of the selected bit lines BL or write data to memory cells connected to at least some of the selected bit lines BL. The read/write circuit 40 may include circuits such as a page buffer, an input/output buffer, and a data latch to perform the above operations.

The control circuit 50 may control operations of the row decoder 30 and the read/write circuit 40 in response to the control signal CTRL transmitted from the outside. When data stored in the memory cell array 20 is read, the control circuit 50 controls the operation of the row decoder 30 to supply a voltage for a read operation to the word line WL in which data to be read is stored. can do. When the voltage for the read operation is supplied to the specific word line WL, the control circuit 50 controls the read/write circuit 40 to store data stored in the memory cell connected to the word line WL to which the voltage for the read operation is supplied. can be controlled to read.

Meanwhile, when data is written to the memory cell array 20 , the control circuit 50 may control the operation of the row decoder 30 to supply a voltage for a write operation to the word line WL to which data is to be written. have. When the voltage for the write operation is supplied to the specific word line WL, the control circuit 50 writes data to the memory cell connected to the word line WL to which the voltage for the write operation is supplied, the read/write circuit 40 writes data. ) can be controlled.

2 is an equivalent circuit diagram illustrating a memory cell array of a memory device according to an embodiment of the present invention. The semiconductor device according to an embodiment of the present invention may be a vertical NAND flash device.

Referring to FIG. 2 , the memory cell array includes n memory cells MC1 to MCn connected in series to each other, a ground select transistor GST and a string select transistor connected in series to both ends of the memory cells MC1 to MCn. A plurality of memory cell strings S including SST may be included.

The n memory cells MC1 to MCn connected in series may be respectively connected to the n word lines WL1 to WLn for selecting the memory cells MC1 to MCn.

The gate terminal of the ground select transistor GST may be connected to the ground select line GSL, and the source terminal may be connected to the common source line CSL. Meanwhile, a gate terminal of the string select transistor SST may be connected to the string select line SSL, and a source terminal may be connected to a drain terminal of the memory cell MCn. 3 illustrates a structure in which the ground select transistor GST and the string select transistor SST are connected one by one to the n memory cells MC1 to MCn connected in series with each other. Alternatively, a plurality of string select transistors SST may be connected.

A drain terminal of the string select transistor SST may be connected to the plurality of bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, the signal applied through the bit lines BL1 to BLm is applied to the n memory cells MC1 to MCn connected in series with each other. By passing, a data read or write operation can be executed. In addition, by applying a signal through the gate selection line GSL to the gate terminal of the gate selection transistor GST whose source terminal is connected to the common source line CSL, all the charges stored in the n memory cells MC1 to MCn are removed. An erase operation to remove may be performed.

3 is a plan view illustrating a memory device according to an embodiment of the present invention.

Referring to FIG. 3 , the memory device 100 according to an embodiment of the present invention may include a cell region C and a peripheral circuit region P adjacent to the cell region C. Referring to FIG. The cell region C includes a channel region CH extending in a direction perpendicular to the upper surface of the substrate 101 and a plurality of gate electrode layers stacked on the substrate 101 adjacent to the channel region CH. of cell contacts 181-186, and the like. Meanwhile, the peripheral circuit region P may include a plurality of peripheral contacts 220 and 240 connected to the peripheral circuit elements 210 and 230 formed on the substrate 101 . In the cell region C, the channel region CH and the gate electrode layer may be divided into a plurality of regions by the isolation insulating layer 102 .

The upper surface of the substrate 101 may correspond to the X-Y plane, and the channel region CH and the plurality of contacts 180 may extend along a direction perpendicular to the upper surface of the substrate 101 (the Z-axis direction of FIG. 3 ). have. Meanwhile, the plurality of gate electrode layers connected to the plurality of cell contacts 181-186 may be stacked on the upper surface of the substrate 101 corresponding to the X-Y plane along the Z-axis direction.

The channel regions CH may be disposed to be spaced apart from each other in the X-Y plane. The number and arrangement of the channel regions CH may vary according to embodiments, and for example, may be arranged in a zig-zag shape as shown in FIG. 3A . Also, the arrangement of the adjacent channel regions CH with the isolation insulating layer 102 interposed therebetween may be symmetrical as illustrated, but is not necessarily limited to such a shape.

The plurality of gate electrode layers and the channel region CH may be divided into a plurality of regions by the common source line 103 and the isolation insulating layer 102 disposed around the common source line 103 . Each of the plurality of regions defined by the common source line 103 and the isolation insulating layer 102 may be provided as a unit cell of the memory device 100 . A source region may be provided below the common source line 103 in the Z-axis direction.

An interlayer insulating layer may be provided on the substrate 101 over the cell region C and the peripheral circuit region P. The interlayer insulating layer is an insulating layer covering the plurality of gate electrode layers and the peripheral circuit elements 210 and 230 , and may include silicon oxide or silicon nitride. In FIG. 3 , in order to describe the internal structure of the memory device 100 in more detail, the interlayer insulating layer is excluded.

The peripheral circuit devices 210 and 230 may include horizontal transistors, and may include active regions 212 and 232 serving as drain or source regions, and horizontal gate electrode layers 211 and 231 . The active regions 212 and 232 may be formed by implanting impurities into a partial region of the substrate 101 , and the active regions 212 and 232 and the horizontal gate electrode layers 211 and 231 may cross each other. A plurality of peripheral contacts 210 and 230 may be respectively connected to the active regions 212 and 232 and the horizontal gate electrode layers 211 and 231 .

The plurality of peripheral contacts may include a first peripheral contact 220 connected to the first peripheral circuit element 210 and a second peripheral contact 240 connected to the second peripheral circuit element 230 . The first peripheral contact 220 may include a first gate contact 221 connected to the first horizontal gate electrode layer 211 and a first active contact 222 connected to the first active region 212 . . In addition, the second peripheral contact 240 may include a second gate contact 241 connected to the second horizontal gate electrode layer 231 and a second active contact 242 connected to the second active region 232 . can

In the memory device 100 according to the embodiment of the present invention, the distance and the number of active contacts 222 and 242 connected to the active regions 212 and 232 of the peripheral circuit region P are, 232) can be determined according to the size of the 3 , the size of the first active region 212 may be smaller than the size of the second active region 232 . Also, the distance P1 between the first active contacts 222 connected to the first active region 212 may be smaller than the distance P2 between the second active contacts 242 connected to the second active region 232 .

In general, in the case of a peripheral circuit device having a large active region, the number of contacts connected to one active region increases. On the other hand, an interval between contacts connected to one active region may be constant regardless of the size of the active region. In this case, cracks may occur in the interlayer insulating layer between the active contacts due to stress applied to the space between the active contacts connected to the relatively large active regions.

In an embodiment of the present invention, in order to solve this problem, the interval between the active contacts 222 and 242 may be set differently according to the size of the active regions 212 and 232 . In the embodiment shown in FIG. 1 , the active contacts 222 and 242 may be formed such that the gap P2 between the second active contacts 242 is greater than the gap P1 between the first active contacts 222 . Accordingly, cracks that may occur in the interlayer insulating layer positioned between the second active contacts 242 may be prevented.

Meanwhile, the widths W1 and W2 of each of the first and second active contacts 222 and 242 may be substantially equal to each other. Since the spacing between the first and second active contacts 222 and 242 having the same width is different, P2, which is the spacing between the centers of the first active contacts 222 , is also the distance between the centers of the second active contacts 242 . It may be smaller than the interval P4. In an embodiment, the width W2 of the second active contact 242 formed while having a relatively wide interval may be greater than the width W1 of the first active contact 222 due to a difference that may occur during a process.

When determining the distance between the second active contacts 242 connected to the second peripheral circuit element 230 , which is relatively larger than the first peripheral circuit element 210 , the current characteristics of the second peripheral circuit element 230 are considered. can be The current characteristic of the second peripheral circuit element 230 becomes better as the number of second active contacts 242 connected to the second active region 232 increases, but the number of second active contacts 242 increases as the number of second active contacts 242 increases. When the gap between the second active contacts 242 is reduced, cracks may easily occur in the interlayer insulating layer.

Accordingly, while securing a gap between the second active contacts 242 enough to suppress the occurrence of cracks in the interlayer insulating layer, the number of the second active contacts 242 is excessively reduced to prevent the second peripheral circuit element 230 from occurring. The number and spacing of the second active contacts 242 may be determined so that the current characteristic of the ? In one embodiment, a predetermined reference size of the plurality of peripheral circuit elements 210 and 230 disposed in the peripheral circuit region P is determined and connected to the peripheral circuit elements 210 and 230 exceeding the reference size. By relatively increasing the distance between the active contacts 222 and 242, the occurrence of cracks in the interlayer insulating layer can be prevented.

Hereinafter, the memory device 100 according to an embodiment of the present invention will be described with reference to FIG. 4 together.

FIG. 4 is a cross-sectional view illustrating a cross section of the memory device shown in FIG. 3 in a direction I-I′.

Referring to FIG. 4 , the memory device 100 according to the embodiment of the present invention includes a plurality of peripheral circuit elements 210 and 230 formed in the peripheral circuit region P, and the peripheral circuit elements 210 and 230 . active contacts 222 , 242 connected to active regions 212 , 232 , and the like. The peripheral circuit devices 210 and 230 may include horizontal gate electrode layers 211 and 231 , active regions 212 and 232 , and horizontal gate insulating layers 213 and 233 . A device isolation layer 104 may be formed outside.

The active regions 212 and 232 may be formed by implanting impurities into regions other than the isolation layer 104 . The horizontal gate electrode layers 211 and 231 may be formed of a conductive material such as polysilicon or metal silicide, and horizontal gate insulating layers 213 and 233 may be disposed between the horizontal gate electrode layers 211 and 231 and the substrate 101 . can

An interlayer insulating layer 150 including first and second interlayer insulating layers 151 and 153 may be provided on the substrate 101 in the peripheral circuit region P. The first interlayer insulating layer 151 may fill a space between the peripheral circuit elements 210 and 230 and may include a high density plasma (HDP) oxide layer. The second interlayer insulating layer 153 may be formed over the peripheral circuit region P and the cell region C, and may include a Tetra-Ethly-Ortho-Silicate (TEOS) oxide layer.

Active contacts 222 and 242 may be connected to each of the active regions 212 and 232 of the peripheral circuit elements 210 and 230 . The active contacts 222 and 242 may pass through the interlayer insulating layer 150 to be connected to the active regions 212 and 232 . Although the active contacts 222 and 242 are shown to have a constant width along the depth direction in the embodiment shown in FIG. 4 , in reality, the active contacts 222 and 242 may have a shape that becomes narrower as they get closer to the substrate 101 . The first active region 212 may have a size relatively smaller than that of the second active region 232 , and the interval P1 between the first active contacts 222 connected to the first active region 212 is the second active region 232 . The distance P3 between the second active contacts 242 connected to the region 232 may be less than the interval P3 .

As described above, when the active contacts 222 and 242 are formed at equal intervals in the first and second active regions 212 and 232, respectively, without adjusting the spacing between the active contacts 222 and 242, the second active contact A crack may occur in the interlayer insulating layer 150 between the 242 . In an embodiment of the present invention, the spacing P3 between the second active contacts 242 is greater than the spacing P1 between the first active contacts 222, and thus an interlayer insulating layer ( 150) can be prevented from cracking.

In an embodiment, a ratio of the width W2 of the second active contact 242 to the interval P3 between the second active contact 242 may be determined within a range of 1:1.5 to 1:3. Meanwhile, a ratio of the width W1 of the first active contact 222 to the interval P1 between the first active contact 222 may be determined within a range of 1:0.5 to 1:1.5. By determining the spacing P3 between the second active contacts 242 in the numerical range as described above, cracks in the interlayer insulating layer 150 that may occur between the second active contacts 242 are suppressed and at the same time, the second active contacts 242 are suppressed. Deterioration of current characteristics of the second peripheral circuit element 230 due to a decrease in the number of contacts 242 may also be minimized.

FIG. 5 is a partial perspective view illustrating a region A of the memory device shown in FIG. 3 .

Referring to FIG. 5 , the memory device 100 includes a plurality of gate electrode layers 131 to 136 ( 130 ) and a plurality of insulating layers 141 to 147 that are alternately stacked on the upper surface of the substrate 101 along the Z-axis direction. 140) may be included. The plurality of gate electrode layers 130 and the plurality of insulating layers 140 may extend in one direction (X-axis direction of FIG. 5 ). The plurality of gate electrode layers 130 and the plurality of insulating layers 140 may be disposed adjacent to the channel layer 110 extending in a direction perpendicular to the top surface of the substrate 101 in the cell region C.

The channel layer 110 may be formed in a cavity having a circular cross-section, and may have an annular shape with an empty center. A space formed in the middle of the channel layer 110 may be filled by the buried insulating layer 113 , and a conductive layer 115 may be formed on the channel layer 110 . The conductive layer 115 may be provided as a drain region of a plurality of memory cell devices that are connected to a bit line and formed in the cell region C. Referring to FIG.

Each gate electrode layer 130 may provide a gate electrode of the ground select transistor GST, the plurality of memory cell transistors MC1 to MCn, and the string select transistor SST. The gate electrode layer 130 may extend to form the word lines WL1 to WLn, and may be common among adjacent memory cell strings of a predetermined unit arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). can be connected to In an embodiment, the total number of the gate electrode layers 130 constituting the memory cell transistors MC1 to MCn may be 2 ^N (N is a natural number).

The gate electrode layer 131 of the ground select transistor GST may be connected to the ground select line GSL. Although one gate electrode layer 136 of the string select transistor SST and one gate electrode layer 131 of the ground select transistor GST are illustrated in FIG. 5 , the number is not necessarily limited thereto. Meanwhile, the gate electrode layers 131 and 136 of the ground select transistor GST and the string select transistor SST may have different structures from the gate electrodes 132 - 135 of the memory cell transistors MC1 to MCn.

The plurality of gate electrode layers 130 may include polysilicon or a metal silicide material. The metal silicide material may be, for example, a silicide material of a metal selected from Co, Ni, Hf, Pt, W, and Ti. In some embodiments, the plurality of gate electrode layers 130 may include a metal material, for example, tungsten (W). Also, although not shown, the plurality of gate electrode layers 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN). ) may include at least one of. Each of the plurality of gate electrode layers 130 may be electrically connected to the plurality of cell contacts 181-186 in the pad region. The cell contacts 181-186 may pass through some of the interlayer insulating layer 150 and the plurality of insulating layers 140 to be connected to the gate electrode layer 130 .

The plurality of insulating layers 140 alternately stacked with the plurality of gate electrode layers 130 may be separated from each other by the isolation insulating layer 102 in the Y-axis direction, like the plurality of gate electrode layers 130 . The plurality of insulating layers 140 may include an insulating material such as silicon oxide or silicon nitride.

A gate insulating layer 160 including a blocking layer 162 , a charge storage layer 164 , a tunneling layer 166 , and the like may be disposed between the channel layer 110 and the plurality of gate electrode layers 130 . According to the structure of the memory device 100 , the blocking layer 162 , the charge storage layer 164 , and the tunneling layer 166 may all be disposed to surround the gate electrode layer 130 . Alternatively, a portion of the gate insulating layer 160 may extend in the Z-axis direction parallel to the channel layer 110 to be disposed outside the channel layer 110 , and the remainder may be disposed to surround the gate electrode layer 130 . In the embodiment shown in FIG. 3B , the charge storage layer 164 and the tunneling layer 166 are disposed on the outside of the channel layer 110 so as to extend in the Z-axis direction parallel to the channel layer 110, and the blocking layer ( 162 may be disposed to surround the gate electrode layer 130 .

The blocking layer 162 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a high-k dielectric material. The high-k dielectric material is, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ) may be any one. When the blocking layer 162 includes a high-k dielectric material, the term “high permittivity” means that the dielectric constant of the blocking layer 162 is higher than that of the tunneling layer 166 or higher than that of silicon oxide. can be defined as

Meanwhile, the blocking layer 162 may optionally include a plurality of layers having different dielectric constants. In this case, by arranging the layer having a relatively low dielectric constant closer to the channel layer 110 than the layer having a high dielectric constant, an energy band such as a barrier height is adjusted to control characteristics of the memory device, for example, an erase characteristic. can improve

The charge storage layer 164 may be a charge trap layer or a floating gate conductive layer. When the charge storage layer 164 is a floating gate, the charge storage layer 164 may be formed by depositing polysilicon by LPCVD (Low Pressure Chemical Vapor Deposition). When the charge storage layer 164 is a charge trap layer, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ) , tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), hafnium aluminum oxide (HfAl _x O _y ), hafnium tantalum oxide (HfTa _x O _y ), hafnium silicon oxide (HfSi _x O _y ), aluminum nitride ( Al _x N _y ), and aluminum gallium nitride (AlGa _x N _y ) may include at least one.

Tunneling layer 166 is silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), aluminum oxide (Al) ₂ O ₃ ), and at least one of zirconium oxide (ZrO ₂ ).

A peripheral circuit element 230 may be provided in the peripheral circuit region P. The peripheral circuit device 230 includes an active region 232 formed by implanting impurities into the substrate 101 , a horizontal gate electrode layer 231 intersecting the active region 232 , and a horizontal gate electrode layer 231 and the substrate 101 . It may include a horizontal gate insulating layer 233 disposed therebetween. The active region 232 may serve as a source or drain region of the peripheral circuit device 230 , and an isolation layer 250 may be disposed outside the active region 232 . At least a portion of the active region 232 may be shared by two or more peripheral circuit elements 230 adjacent to each other.

A cover layer 260 may be formed on the peripheral circuit element 230 . The cover layer 260 may include the interlayer insulating layer 150 and a material having a predetermined etch selectivity. For example, when the interlayer insulating layer 150 includes a silicon oxide layer, the cover layer 260 may include a silicon nitride layer. The cover layer 260 may prevent the active region 232 from being excessively recessed in the process of forming the plurality of peripheral contacts 242 . Meanwhile, the cover layer 260 may be selectively removed from a partial region on the horizontal gate electrode layer 231 . Accordingly, the gate contact 241 may be connected to the horizontal gate electrode layer 231 without contacting the cover layer 260 .

A plurality of active contacts 242 may be connected to one active region 232 . An interval between the plurality of active contacts 242 connected to one active region 232 may be determined according to the size of the active region 232 . In an embodiment, when the active area 232 is larger than a predetermined threshold size, the active contact 242 may be formed to have a larger interval than an interval between active contacts connected to an active area smaller than the threshold size. By forming the active contact 242 according to the above conditions, it is possible to prevent cracks in the interlayer insulating layer 150 that may occur between the active contacts 242 .

Each of the plurality of gate electrode layers 130 and the insulating layer 140 extends by different lengths along the X-axis direction from the other gate electrode layers 130 and the insulating layer 140 stacked at different positions in the Z-axis direction. A plurality of steps having a step shape may be formed. A plurality of pad regions may be provided due to a step difference in which the plurality of gate electrode layers 130 and the insulating layer 140 extend to have different lengths along the X-axis direction. 5 shows that the insulating layer 140 is positioned above the gate electrode layer 130 in the Z-axis direction in each pad region. may be

Meanwhile, the memory device 100 according to an embodiment of the present invention may include an interlayer insulating layer 150 disposed on the substrate 101 over the cell region C and the peripheral circuit region P. . The interlayer insulating layer 150 may include a first interlayer insulating layer 151 and a second interlayer insulating layer 153 . The first and second interlayer insulating layers 151 and 153 may include the same material, for example, silicon oxide or silicon nitride. The first interlayer insulating layer 151 may be disposed only in the peripheral circuit region P to cover the peripheral circuit element 190 . In particular, the first interlayer insulating layer 151 may be formed only in the region where the peripheral circuit elements 210 and 230 are formed. As described above, the first interlayer insulating layer 151 may include an HDP oxide layer, and the second interlayer insulating layer 153 may include a TEOS oxide layer. The second interlayer insulating layer 153 may be formed of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Sub-Atmospheric Chemical Vapor Deposition (SACVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD). It may be formed by a process such as

6 is a plan view illustrating a memory device according to an embodiment of the present invention.

Referring to FIG. 6 , the memory device 300 according to an embodiment of the present invention may include a cell region C and a peripheral circuit region P. Referring to FIG. The cell region C may include a plurality of gate electrode layers, a channel region CH, and a plurality of cell contacts 381-386 ( 380 ) connected to each of the plurality of gate electrode layers. The plurality of gate electrode layers and the channel region CH may be divided into a plurality of unit cell regions by the isolation insulating layer 302 and the common source line 303 .

A plurality of peripheral circuit elements 410 and 430 may be disposed in the peripheral circuit region P. The plurality of peripheral circuit elements 410 and 430 may be horizontal transistors, and may include horizontal gate electrode layers 411 and 431 and active regions 412 and 432 . A plurality of peripheral contacts 420 and 440 may be connected to the horizontal gate electrode layers 411 and 431 and the active regions 412 and 432 of the peripheral circuit elements 410 and 430 , respectively.

The first active region 412 may have a smaller size than the second active region 432 . A distance P3 between the second active contacts 442 connected to the second active region 432 having a relatively large area is a distance P1 between the first active contacts 422 connected to the first active region 412 . can be larger

In particular, in the embodiment illustrated in FIG. 6 , the width W2 of the second active contact 442 is equal to the width W2 of the first active contact 442 , unlike the embodiment of FIG. 3 in which the widths of the first and second active contacts 222 and 242 are equal to each other. It may be smaller than the width W1 of the contact 422 . The spacing P4 between the centers of the second active contacts 442 and the spacing P2 between the centers of the first active contacts 422 may be equal to each other.

FIG. 7 is a cross-sectional view illustrating a cross section in a direction II-II′ of the memory device shown in FIG. 6 .

Referring to FIG. 7 , a memory device 300 according to an embodiment of the present invention may include a substrate 301 and peripheral circuit elements 410 and 430 formed on the substrate 301 . The peripheral circuit devices 410 and 430 may include active regions 412 and 432 , horizontal gate electrode layers 411 and 431 , and horizontal gate insulating layers 413 and 433 , etc., and are located outside the active regions 412 and 432 . A device isolation layer 404 may be disposed. An interlayer insulating layer 450 including silicon oxide or silicon nitride may be provided on the peripheral circuit elements 410 and 430 .

In the first active contact 422 connected to the first active region 412 having a relatively small area, the width W1 of the first active contact 422 and the gap P1 between the first active contact 422 are The ratio may be from 1:0.5 to 1:1.5. On the other hand, in the second active contact 442 connected to the second active region 432 having a relatively large area, a gap between the width W2 of the second active contact 442 and the second active contact 442 . The ratio of P3 may be 1:1.5 to 1:3. That is, the interval P3 between the second active contacts 442 may be greater than the interval P1 between the first active contacts 422 .

Unlike the embodiment illustrated in FIGS. 3 and 4 , in the embodiment illustrated in FIG. 6 , the width of the first active contact 422 and the second active contact 442 may be different. That is, the width W2 of the second active contact 442 may be smaller than the width W1 of the first active contact 422 . On the other hand, the spacing P4 between the centers of the second active contacts 442 may be substantially the same as the spacing P2 between the centers of the first active contacts 422 . Comparing the embodiment shown in FIG. 6 with the embodiment shown in FIG. 4 , instead of reducing the width W2 of the second active contact 442 , the number of second active contacts 442 is relatively increased, so that the second Current characteristics of the peripheral circuit element 430 may be secured.

8 to 23 are diagrams provided to explain a method of manufacturing the memory device illustrated in FIGS. 3 to 5 .

Referring first to FIG. 8 , in the method of manufacturing a memory device according to an embodiment of the present invention, peripheral circuit elements 210 and 230 may be formed on a substrate 101 . The peripheral circuit elements 210 and 230 may be formed in the peripheral circuit region P defined on the substrate 101 . The peripheral circuit region P may be defined as a region adjacent to the cell region C in which the memory cell element is formed.

The peripheral circuit elements 210 and 230 may include horizontal transistors, and each of the peripheral circuit elements 210 and 230 may include active regions 212 and 232 , horizontal gate electrode layers 211 and 231 , and the like. The active regions 212 and 232 may be regions formed by implanting impurities into the substrate 101 through an ion implantation process or the like, and may be provided as source or drain regions of the peripheral circuit devices 210 and 230 . The horizontal gate electrode layers 211 and 231 may include a conductive material such as metal or polysilicon, and may cross the active regions 212 and 232 .

The peripheral circuit elements 210 and 230 may include a first peripheral circuit element 210 and a second peripheral circuit element 230 having different sizes. The first peripheral circuit element 210 may be smaller than the second peripheral circuit element 230 , and the first active region 212 may have a smaller area than the second active region 232 .

9 is a cross-sectional view illustrating a cross-section in the II′ direction of FIG. 8 , and FIG. 10 may be a cross-sectional view illustrating a cross-section in the III-III′ direction of FIG. 8 . 9 and 10 , a device isolation layer 250 and active regions 212 and 232 may be provided on a substrate 101 . The device isolation layer 250 may be a layer for electrically separating the peripheral circuit devices 210 and 230 from each other. Horizontal gate electrode layers 211 and 231 may be provided on the substrate 101 to intersect the active regions 212 and 232 , and a horizontal gate insulating layer 213 may be disposed between the horizontal gate electrode layers 211 and 231 and the substrate 101 . , 233) may be provided. The first active region 212 may have a smaller area than the second active region 232 .

Next, referring to FIG. 11 , a first interlayer insulating layer 151 may be formed on the peripheral circuit devices 210 and 230 in the peripheral circuit region P. The first interlayer insulating layer 151 may include silicon oxide or silicon nitride, and a space defined by the upper surface of the substrate 101 and the horizontal gate electrode layers 211 and 231 of the peripheral circuit elements 210 and 230, etc. can be filled In an embodiment, the first interlayer insulating layer 151 may include an HDP oxide layer having excellent gap filling characteristics.

Referring to FIG. 12 showing a cross section in the direction I-I′ of FIG. 11 , a cover layer 260 may be formed on the peripheral circuit elements 210 and 230 . The cover layer 260 may be formed of a material having a predetermined etch selectivity to the first interlayer insulating layer 151 . In an embodiment, the first interlayer insulating layer 151 may include silicon oxide, and the cover layer 260 may include silicon nitride. When the cover layer 260 forms a plurality of contacts connected to the horizontal gate electrode layers 211 and 231 and the active regions 212 and 232 , the horizontal gate electrode layers 211 and 231 and the active regions 212 and 232 are formed. Excessive recessing can be prevented. In some embodiments, the cover layer 260 may be formed only on the active regions 212 and 232 and may not be present on the horizontal gate electrode layers 211 and 231 .

Referring to FIG. 13 showing a cross-section in the III-III′ direction of FIG. 11 , the cover layer 260 and the first interlayer insulating layer 151 may be formed only in the peripheral circuit region P. Referring to FIG. In the manufacturing process, after sequentially forming the cover layer 260 and the first interlayer insulating layer 151 on the substrate 101 , the cover layer 260 and the first interlayer insulating layer 151 only in the cell region C ) to expose the upper surface of the substrate 101 . A plurality of sacrificial layers and a plurality of insulating layers may be alternately stacked on the upper surface of the substrate 101 exposed in the cell region C, and the plurality of sacrificial layers and the insulating layers are subjected to a plurality of etching processes to form a step structure. can be formed Hereinafter, it will be described with reference to FIG. 14 .

Referring to FIG. 14 , a plurality of sacrificial layers and a plurality of insulating layers having a step structure may be formed in the cell region (C). The plurality of sacrificial layers and the plurality of insulating layers may be alternately stacked. When the plurality of sacrificial layers and the plurality of insulating layers are formed, the second interlayer insulating layer 153 may be formed over the cell region C and the peripheral circuit region P. The second interlayer insulating layer 153 may be formed of the same material as the first interlayer insulating layer 151 , and may have a relatively larger volume than the first interlayer insulating layer 151 . Accordingly, the second interlayer insulating layer 153 may include a TEOS oxide film having a high deposition rate.

Referring to FIG. 15 showing a cross section in the I-I′ direction of FIG. 14 and FIG. 16 showing a cross section in the III-III′ direction, the second interlayer insulating layer 153 is disposed on the first interlayer insulating layer 151 . can The second interlayer insulating layer 153 may be disposed on the plurality of sacrificial layers 121-126: 120 and the plurality of insulating layers 141-147:140 in the cell region C. Referring to FIG.

In order to form a step as shown in FIG. 16 between the sacrificial layer 120 and the insulating layer 140 adjacent in the Z-axis direction, a plurality of sacrificial layers 130 and insulating layers alternately stacked on the substrate 101 are formed. A predetermined mask layer may be formed on the layer 140 , and the sacrificial layer 130 and the insulating layer 140 exposed by the mask layer may be etched. By performing the process of etching the sacrificial layer 120 and the insulating layer 140 exposed by the mask layer a plurality of times while trimming the mask layer, the sacrificial layer 120 and the insulating layer 140 are sequentially etched Thus, a step structure having a step difference can be formed.

In one embodiment, each insulating layer 140 and the sacrificial layer 120 form a pair, and the insulating layer 140 and the sacrificial layer 120 included in the plurality of pairs are aligned in one direction (X in FIG. 15 ). axial direction) may extend the same length as each other. Exceptionally, insulating layers 141 and 142 extending as much as the same length may be disposed below the sacrificial layer 121 located at the lowermost portion in the Z-axis direction. In this case, the insulating layer 141 located at the lowermost portion in the Z-axis direction may have a relatively thin thickness compared to the other insulating layers 142 to 147 .

The plurality of sacrificial layers 120 may be formed of a material that can be selectively etched by having a high etch selectivity with respect to the plurality of insulating layers 140 . The etch selectivity may be quantitatively expressed through a ratio of the etch rate of the sacrificial layer 120 to the etch rate of the insulating layer 140 . For example, the insulating layer 140 may be at least one of a silicon oxide film and a silicon nitride film, and the sacrificial layer 120 is a material selected from a silicon film, a silicon oxide film, a silicon carbide and a silicon nitride film, and the insulating layer 140 . and may be a different material. For example, when the insulating layer 140 is a silicon oxide layer, the sacrificial layer 120 may be a silicon nitride layer.

Next, referring to FIG. 17 , a channel region CH, an isolation insulating layer 102 , and a common source line 103 may be formed. To form the channel region CH, a channel opening extending from the top surface of the second interlayer insulating layer 153 to the top surface of the substrate 101 may be formed. A channel layer 110 , a buried insulating layer 113 , a conductive layer 115 , and the like may be formed inside the channel opening. The channel layer 110 may have a shape that digs into a portion of the substrate 101 from the top surface of the substrate 101 . In another embodiment, an epitaxial layer formed by selective epitaxial growth may be further provided between the channel layer 110 and the substrate 101 . The structure and shape of the channel region CH may be understood in detail with reference to FIG. 18 showing a cross-section in the III-III′ direction of FIG. 17 .

Referring to FIG. 18 , the channel region CH may include a channel layer 110 , a buried insulating layer 113 , a conductive layer 115 , and an epitaxial layer 117 . The epitaxial layer 117 may be prepared by applying a selective epitaxial growth process to the upper surface of the substrate 101 exposed by the channel opening for forming the channel region CH. The epitaxial layer 117 may extend to a height adjacent to the gate electrode layer 131 of the ground select transistor GST located at the bottom.

Meanwhile, at least a portion of the gate insulating layer, for example, the charge storage layer 164 and the tunneling layer 166 may be formed outside the channel layer 110 . The charge storage layer 164 and the tunneling layer 166 may be formed by a process such as ALD or CVD, and tunnel with the charge storage layer 164 from a region adjacent to the plurality of sacrificial layers 120 and the insulating layer 140 . Layers 166 may be stacked in order. The channel layer 110 may be formed to a predetermined thickness, for example, a thickness in the range of 1/50 to 1/5 of the width of the channel opening, similar to the charge storage layer 164 and the tunneling layer 166, ALD or It can be formed by CVD.

An inner space of the channel layer 110 may be filled with a buried insulating layer 113 . Optionally, before forming the buried insulating layer 113 , a hydrogen annealing step of heat-treating the structure in which the channel layer 110 is formed in a gas atmosphere containing hydrogen or deuterium may be further performed. Many of the crystal defects existing in the channel layer 110 may be healed by the hydrogen annealing step. Next, a conductive layer 115 may be formed on the channel layer 110 using a conductive material such as polysilicon. The conductive layer 115 may be connected to a bit line and serve as a drain region of the memory cell device.

After the channel region CH is formed, an opening for forming the isolation insulating layer 102 and the common source line 103 may be provided. The plurality of sacrificial layers 120 and the insulating layer 140 may be divided into a plurality of regions by the opening, and the plurality of sacrificial layers 120 may be selectively removed through the opening. In the space where the plurality of sacrificial layers 120 are removed, a plurality of gate electrode layers 131 - 136 ( 130 ) may be formed of a conductive material such as metal, metal silicide, or polysilicon.

The metal silicide material may be, for example, a silicide material of a metal selected from Co, Ni, Hf, Pt, W, and Ti, or a combination thereof. When the gate electrode layer 130 is made of a metal silicide material, the gate electrode layer 130 may be formed by burying silicon (Si) in the side openings and then performing a silicidation process by forming a separate metal layer. Before forming the plurality of gate electrode layers 130 , the blocking layer 162 may be first formed in the space where the plurality of sacrificial layers 120 are removed. After the plurality of gate electrode layers 130 are formed, the isolation insulating layer 102 and the common source line 103 may be provided.

Next, referring to FIG. 19 , a plurality of peripheral contacts 220 and 240 connected to the plurality of peripheral circuit elements 210 and 230 may be provided. The plurality of peripheral contacts 220 and 240 include a plurality of gate contacts 221 and 241 connected to the horizontal gate electrode layers 211 and 231 and a plurality of active contacts 222 and 242 connected to the active regions 212 and 232 . ) may be included.

As described above, the first peripheral circuit element 210 may have a relatively smaller size than the second peripheral circuit element 230 , and the first active region 212 may also be smaller than the second active region 232 . have. The spacing P1 between the plurality of first active contacts 222 connected to the first active region 212 may be less than the spacing P3 between the plurality of second active contacts 242 connected to the second active region 232 . can Meanwhile, the width W1 of the first active contact 222 may be substantially the same as the width W2 of the second active contact 242 . However, due to characteristics of the second active contact 242 formed to have a larger width P3 , the width W2 of the second active contact 242 is greater than the width W1 of the first active contact 222 within a process error range. may be

If the interval P3 of the second active contact 242 is equal to the interval P1 of the first active contact 222 , the number of second active contacts 242 connected to one second active region 232 may increase. . In this case, cracks may occur in a portion of the interlayer insulating layer 150 positioned between the second active contacts 242 due to stress generated during the process of forming the second active contacts 242 . In the embodiment of the present invention, in order to prevent the occurrence of cracks as described above, the second active contact 242 is formed such that the interval P3 of the second active contact 242 is greater than the interval P1 of the first active contact 222 . can do.

Referring to FIG. 20 showing a cross section in the II′ direction of FIG. 19 and FIG. 21 showing a cross section in the III-III′ direction, the ratio of the width W1 of the first active contact 222 to the interval P1 is 1:0.5 to It may be determined within the range of 1:1.5, and in one embodiment may be about 1:1. On the other hand, the ratio of the width W2 of the second active contact 242 to the interval P3 may be determined within the range of 1:1.5 to 1:3. Since the widths W1 and W2 of each of the first and second active contacts 222 and 242 are substantially the same, the second active contact 242 may be formed in which the interval P3 is greater than the interval P1 . Meanwhile, the first and second active contacts 222 and 242 penetrate through the interlayer insulating layer 150 and the cover layer 260 and penetrate at least a portion of the first and second active regions 212 and 232 . can be extended as much as

Referring to FIGS. 22 and 23 , which are cross-sectional views taken in the III-III′ direction of FIGS. 22 , a plurality of cell contacts 181-186 ( 180 ) may be formed in the cell region C . The plurality of cell contacts 180 may pass through some of the interlayer insulating layer 150 and the plurality of insulating layers 140 to be connected to each of the plurality of gate electrode layers 130 . When the blocking layer 162 is disposed outside the plurality of gate electrode layers 130 , the cell contact 180 may also penetrate the blocking layer 162 .

In the embodiment of the present invention, it is assumed that the cell contact 180 and the peripheral contacts 220 and 240 are formed in a separate process, but otherwise, they may be formed in a single process. In addition, at least a portion of the cell contact 180 and the peripheral contacts 220 and 240 may have a tapered shape in which the width becomes narrower as it approaches the substrate 101 in the depth direction.

24 and 25 are block diagrams illustrating an electronic device including a memory device according to an embodiment of the present invention.

Referring to FIG. 24 , the storage device 1000 according to an embodiment may include a controller 1010 communicating with a host and memories 1020-1, 1020-2, and 1020-3 for storing data. can Each of the memories 1020-1, 1020-2, and 1020-3 may include the memory devices 100 and 300 according to various embodiments described above.

The host (HOST) communicating with the controller 1010 may be various electronic devices to which the storage device 1000 is mounted, and may be, for example, a smart phone, a digital camera, a desktop, a laptop, or a media player. The controller 1010 receives a data write or read request transmitted from the host and stores data in the memories 1020-1, 1020-2, and 1020-3, or the memory 1020-1, 1020-2, A command (CMD) for fetching data from 1020-3) may be generated.

24 , one or more memories 1020-1, 1020-2, and 1020-3 in the storage device 1000 may be connected to the controller 1010 in parallel. By connecting the plurality of memories 1020-1, 1020-2, and 1020-3 to the controller 1010 in parallel, the storage device 1000 having a large capacity, such as a solid state drive (SSD), may be implemented.

Next, referring to FIG. 25 , the electronic device 2000 according to an embodiment may include a communication unit 2010 , an input unit 2020 , an output unit 2030 , a memory 2040 , and a processor 2050 .

The communication unit 2010 may include a wired/wireless communication module, and may include a wireless Internet module, a short-range communication module, a GPS module, a mobile communication module, and the like. The wired/wireless communication module included in the communication unit 2010 may be connected to an external communication network according to various communication standards to transmit/receive data.

The input unit 2020 is a module provided for a user to control the operation of the electronic device 2000 , and may include a mechanical switch, a touch screen, a voice recognition module, and the like. In addition, the input unit 2020 may include a mouse or a finger mouse device that operates in a track ball or laser pointer method, and may further include various sensor modules through which a user can input data.

The output unit 2030 outputs information processed by the electronic device 2000 in the form of audio or video, and the memory 2040 may store a program or data for processing and controlling the processor 2050 or data. . The memory 2040 may include one or more memory devices 100 and 300 according to the various embodiments described above, and the processor 2050 stores or retrieves data by transmitting a command to the memory 2040 according to a necessary operation. can do.

The memory 2040 may be embedded in the electronic device 2000 or may communicate with the processor 2050 through a separate interface. When communicating with the processor 2050 through a separate interface, the processor 2050 may store or retrieve data from the memory 2040 through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB, etc. .

The processor 2050 may control the operation of each unit included in the electronic device 2000 . The processor 2050 may perform control and processing related to voice calls, video calls, data communication, and the like, or may perform control and processing for multimedia reproduction and management. In addition, the processor 2050 may process an input transmitted from the user through the input unit 2020 and output the result through the output unit 2030 . Also, as described above, the processor 2050 may store or retrieve data necessary for controlling the operation of the electronic device 2000 in the memory 2040 .

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitution, modification and change will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and it is also said that it falls within the scope of the present invention. something to do.

100, 300: memory device 110, 310: channel layer
130, 330: gate electrode layer 140, 340: insulating layer
150, 350: interlayer insulating layer 180, 380: cell contact
210, 410: first peripheral circuit element 220, 420: second peripheral circuit element
212, 412: first active region 232, 432: second active region
222, 422: first active contact 242, 442: second active contact

Claims (20)

a cell region having a channel region extending in a direction perpendicular to a top surface of the substrate, and a plurality of gate electrode layers stacked on the substrate to be adjacent to the channel region; and
A first active region disposed around the cell region, a second active region having a larger area than the first active region, a plurality of first contacts connected to the first active region, and connected to the second active region a peripheral circuit region having a plurality of second contacts that become including,
An interval between the plurality of first contacts is smaller than an interval between the plurality of second contacts.
According to claim 1,
and a width of the plurality of first contacts is the same as a width of the plurality of second contacts.
According to claim 1,
The memory device, wherein widths of the plurality of first contacts are greater than widths of the plurality of second contacts.
According to claim 1,
The memory device of claim 1, wherein a ratio of a width of each of the plurality of second contacts to an interval between the plurality of second contacts is 1:1.5 to 1:3.
5. The method of claim 4,
The memory device of claim 1, wherein a ratio of a width of each of the plurality of first contacts to an interval between the plurality of first contacts is in a range of 1:0.5 to 1:1.5.
According to claim 1,
The first active region is a plurality of first active regions,
The second active region is a plurality of second active regions.
7. The method of claim 6,
Intervals between the plurality of first contacts connected to any one of the plurality of first active regions are equal to each other, and intervals between the plurality of second contacts connected to any one of the plurality of second active regions are Memory devices characterized in that they are identical to each other.
7. The method of claim 6,
The number of the plurality of first contacts connected to each of the plurality of first active regions is the same, and the number of the plurality of second contacts connected to each of the plurality of second active regions is the same. memory device.
7. The method of claim 6,
The memory device of claim 1, wherein the number of the plurality of first contacts connected to each of the plurality of first active regions is greater than or equal to the number of the plurality of second contacts connected to each of the plurality of second active regions.
According to claim 1,
The memory device of claim 1, wherein the first active region serves as a source and drain region of a first peripheral circuit element, and the second active region serves as a source and drain region of a second peripheral circuit element.
11. The method of claim 10,
An area of the first peripheral circuit element is smaller than an area of the second peripheral circuit element.
a plurality of memory cell elements stacked on the upper surface of the substrate;
first and second active regions disposed around the plurality of memory cell devices;
a plurality of first contacts connected to the first active region and disposed along a first predetermined interval; and
a plurality of second contacts connected to the second active region and disposed along a second interval greater than the first interval; A memory device comprising a.
13. The method of claim 12,
An area of the first active area is smaller than an area of the second active area.
13. The method of claim 12,
The memory device of claim 1, wherein the number of the plurality of first contacts connected to one first active region is less than or equal to the number of the plurality of second contacts connected to one second active region.
13. The method of claim 12,
The memory device of claim 1 , wherein a ratio of a distance between the plurality of second contacts to a width of the plurality of second contacts is in a range of 1:1.5 to 1:3.
16. The method of claim 15,
The memory device of claim 1 , wherein a ratio of a distance between the plurality of first contacts to a width of the plurality of first contacts is in a range of 1:0.5 to 1:1.5.
13. The method of claim 12,
a first horizontal gate electrode layer intersecting the first active region, and a second horizontal gate electrode layer intersecting the second active region;
and the first active region and the first horizontal gate electrode layer provide a first peripheral circuit element, and the second active region and the second horizontal gate electrode layer provide a second peripheral circuit element.
Board;
a channel region extending in a direction perpendicular to the upper surface of the substrate;
a plurality of gate electrode layers adjacent to the channel region and stacked on the substrate;
a plurality of peripheral circuit elements disposed around the plurality of gate electrode layers; and
an interlayer insulating layer disposed on the plurality of gate electrode layers and the plurality of peripheral circuit elements; includes,
The plurality of peripheral circuit elements includes a first peripheral circuit element smaller than a predetermined reference size and a second peripheral circuit element larger than the reference size,
An interval between a plurality of first contacts connected to the first peripheral circuit element is smaller than an interval between a plurality of second contacts connected to the second peripheral circuit element.
19. The method of claim 18,
the first peripheral circuit element has a first active area, the second peripheral circuit element has a second active area that is larger than the first active area;
The plurality of first contacts are connected to the first active region, and the plurality of second contacts are connected to the second active region.
19. The method of claim 18,
The number of the plurality of first contacts is less than or equal to the number of the plurality of second contacts.

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