KR102427647B1 - Semiconductor devices and manufacturing methods of the same - Google Patents

Abstract

In a semiconductor device according to an embodiment of the present invention, gate electrodes stacked vertically on a substrate, channel holes extending perpendicular to the substrate through the gate electrodes, a channel region is disposed, and upper ends of each of the channel holes It is disposed to be connected to the channel region and includes channel pads having a convex top surface.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a method for manufacturing the same.

Semiconductor devices require high-capacity data processing while their volume is getting smaller. Accordingly, it is necessary to increase the degree of integration of semiconductor elements constituting such a semiconductor device. Accordingly, as one of methods for improving the degree of integration of a semiconductor device, a semiconductor device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device with improved reliability.

In a semiconductor device according to example embodiments, gate electrodes vertically stacked on a substrate, channel holes extending perpendicular to the substrate through the gate electrodes, and in which a channel region is disposed, and the channel holes The channel pads may be disposed to be connected to the channel region at their upper ends, and may include channel pads having a convex top surface.

For example, the channel pads may have upper surfaces convex toward the top.

For example, the channel pads may have lower surfaces convex in a direction opposite to the upper surfaces.

For example, first and second insulating layers disposed to have an interface around the upper surfaces of the channel pads may be further included.

For example, the channel pads may be disposed to protrude from the first insulating layer disposed thereunder.

For example, the channel pads may include p-type or n-type impurities.

For example, the display device may further include a gate dielectric layer disposed between the gate electrodes and the channel region, wherein the gate dielectric layer may extend to a side surface of the channel pad in the channel hole.

For example, the channel region may extend to a side surface of the channel pad in the channel hole.

For example, the width of the lower surface of the channel pads may be smaller than that of the upper surface.

In a semiconductor device according to example embodiments, gate electrodes vertically stacked on a substrate, channel holes extending perpendicular to the substrate through the gate electrodes, and in which a channel region is disposed, and the channel holes It is disposed on the upper end of each, and may include channel pads having upper and lower surfaces curved in different directions.

A method of manufacturing a semiconductor device according to example embodiments includes forming a stacked structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, and forming a first insulating layer and a mask layer on the stacked structure. forming channel holes penetrating the stacked structure and the first insulating layer using the mask layer; forming gate dielectric layers and channel regions on sidewalls of the channel holes; Forming channel insulating layers to fill the lower portion, forming a conductive layer to fill the upper portions of the channel holes on the channel insulating layers and extending over the mask layer, and to remain only in the channel holes The method may include removing the conductive layer from an upper portion of the mask layer to form channel pads having a convex top surface.

For example, in the forming of the channel pads, the conductive layer may be removed using a planarization process, and the first insulating layer may be used as a stop layer during the planarization process.

For example, during the planarization process, all of the mask layer may be removed and the first insulating layer may not be removed.

For example, at least a portion of upper surfaces of the channel pads may protrude from the first insulating layer.

For example, the mask layer includes a first mask layer formed below and a second mask layer formed on the first mask layer, and the forming of the channel pads may include forming the second mask layer as a stop layer. It may include removing a portion of the conductive layer by using a

For example, after forming the channel insulating layers, the method may further include removing the second mask layer by a planarization process using the first mask layer as a stop layer.

For example, the first mask layer and the second mask layer may be formed of different materials.

For example, forming the channel insulating layers may include depositing an insulating material to fill the channel holes, and performing an etch-back process to remove the insulating material from the top of the channel holes. can

For example, the channel insulating layers may have a convex top surface toward the substrate by the etch-back process.

For example, the channel pads may have a convex lower surface toward the substrate and a convex upper surface toward the opposite direction to the substrate.

For example, the thickness of the first insulating layer may be in the range of 1.5 times to 2.5 times the thickness of the channel pad.

For example, the thickness of the first insulating layer may be in the range of about 1000 Å to 2200 Å.

For example, the method may further include forming a second insulating layer covering the channel pads.

A method of manufacturing a semiconductor device according to example embodiments may include forming a stacked structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming an insulating layer on the stacked structure, and the stacking structure. forming channel holes penetrating the structure and the insulating layer, forming gate dielectric layers, channel regions and channel insulating layers in the channel holes, and having a convex top surface on top of the channel holes, the insulating layer and forming channel pads at least partially protruding from the layer.

For example, the thickness of the insulating layer may be in the range of 1.5 times to 2.5 times the thickness of the channel pad.

By controlling the thickness of the insulating layer around the channel pad to form the channel pad having a convex top, a semiconductor device with improved reliability can be provided.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic block diagram of a semiconductor device according to example embodiments.
2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to example embodiments.
3 is a schematic perspective view of a semiconductor device according to example embodiments.
4A to 4C are cross-sectional views illustrating a gate dielectric layer according to example embodiments.
5A to 5C are cross-sectional views illustrating a channel pad according to example embodiments.
6 is an electron micrograph for explaining a channel pad according to example embodiments.
7A to 7J are main step-by-step views schematically illustrating a method of manufacturing a semiconductor device according to example embodiments.
8 and 9 are schematic perspective views of a semiconductor device according to example embodiments.
10 is a schematic perspective view of a semiconductor device according to example embodiments.
11 is a block diagram illustrating a storage device including a semiconductor device according to example embodiments.
12 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments.
13 is a schematic diagram illustrating a system including a semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Embodiments of the present invention may be modified in various other forms or various embodiments may be combined, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer description, and elements indicated by the same reference numerals in the drawings are the same elements.

The terminology used herein is used to describe specific embodiments, and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. As used herein, terms such as “comprise,” “comprise,” or “have” are intended to specify that a feature, number, step, action, component, part, or combination thereof described in the specification is present. , the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof should not be construed as precluding the possibility of addition. The term “and/or” includes any one and all combinations of one or more of those listed items.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers and/or parts, these members, parts, regions, layers, and/or parts are limited by these terms, so that It is self-evident that These terms are used only to distinguish one member, component, region, layer or portion from another region, layer or portion. Accordingly, a first member, component, region, layer or portion discussed below may refer to a second member, component, region, layer or portion without departing from the teachings of the present invention.

In this specification, the term 'dummy' is used to refer to a configuration that has the same or similar structure and shape as other components, but does not have a substantial function within, and exists only as a pattern. Therefore, no electrical signal is applied to the 'dummy' component or it does not electrically perform a specific function.

1 is a schematic block diagram of a semiconductor device according to example embodiments.

Referring to FIG. 1 , a semiconductor device 10 according to an embodiment of the present invention includes a memory cell array 20 , a driving circuit 30 , a read/write circuit 40 , and a control circuit 50 . ) may be included.

The memory cell array 20 may include a plurality of memory cells, and the plurality of memory cells may be arranged along a plurality of rows and columns. A plurality of memory cells included in the memory cell array 20 include a word line (WL), a common source line (CSL), a string select line (SSL), and a ground select line ( It may be connected to the driving circuit 30 through a Ground Select Line (GSL), etc., and may be connected to the read/write circuit 40 through a bit line (Bit Line, BL). In some embodiments, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

A plurality of memory cells included in the memory cell array 20 may be divided into a plurality of memory blocks. Each memory block includes a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of bit lines BL, and at least one common source line CSL. ) may be included.

The driving circuit 30 and the read/write circuit 40 may be operated by the control circuit 50 . In one embodiment, the driving circuit 30 receives the address information ADDR from the outside, decodes the received address information ADDR, and the word line WL connected to the memory cell array, the common source line ( CSL), the string select line SSL, and at least some of the ground select line GSL may be selected. The driving circuit 30 may include a driving circuit for each of the word line WL, the string selection line SSL, and the common source line CSL.

The read/write circuit 40 may select at least a portion of the bit lines BL connected to the memory cell array 20 according to a command received from the control circuit 50 . The read/write circuit 40 may read data stored in memory cells connected to at least some of the selected bit lines BL or write data to memory cells connected to at least some of the selected bit lines BL. The read/write circuit 40 may include circuits such as a page buffer, an input/output buffer, and a data latch to perform the above operations.

The control circuit 50 may control the operation of the driving circuit 30 and the read/write circuit 40 in response to the control signal CTRL transmitted from the outside. When data stored in the memory cell array 20 is read, the control circuit 50 controls the operation of the driving circuit 30 to supply a voltage for a read operation to the word line WL in which data to be read is stored. can do. When the voltage for the read operation is supplied to the specific word line WL, the control circuit 50 controls the read/write circuit 40 to store data stored in the memory cell connected to the word line WL to which the voltage for the read operation is supplied. can be controlled to read.

Meanwhile, when data is written to the memory cell array 20 , the control circuit 50 may control the operation of the driving circuit 30 to supply a voltage for a write operation to the word line WL to which data is to be written. have. When the voltage for the write operation is supplied to the specific word line WL, the control circuit 50 writes data to the memory cell connected to the word line WL to which the voltage for the write operation is supplied, the read/write circuit 40 writes data. ) can be controlled.

2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to example embodiments.

2 is an equivalent circuit diagram illustrating a three-dimensional structure of a memory cell array included in the semiconductor device 100A having a vertical structure. Referring to FIG. 2 , in the memory cell array according to the present embodiment, n memory cell elements MC1 to MCn connected in series with each other, and ground selection transistors connected in series to both ends of the memory cell elements MC1 to MCn A plurality of memory cell strings S including a GST and a string select transistor SST may be included.

The n memory cell elements MC1 to MCn connected in series may be respectively connected to the word lines WL1 to WLn for selecting at least some of the memory cell elements MC1 to MCn.

The gate terminal of the ground select transistor GST may be connected to the ground select line GSL, and the source terminal may be connected to the common source line CSL. Meanwhile, a gate terminal of the string select transistor SST may be connected to the string select line SSL, and a source terminal may be connected to a drain terminal of the memory cell device MCn. 2 illustrates a structure in which the ground select transistor GST and the string select transistor SST are connected one by one to the n memory cell elements MC1 to MCn connected in series, but unlike the plurality of ground select transistors ( GST) or a plurality of string select transistors SST may be connected.

A drain terminal of the string select transistor SST may be connected to the bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, the signal applied through the bit lines BL1 to BLm is connected in series to the n memory cell devices MC1 to MCn. By being transferred to , a data read or write operation can be executed. In addition, by applying a signal through the gate selection line GSL to the gate terminal of the gate selection transistor GST whose source terminal is connected to the common source line CSL, the charges stored in the n memory cell elements MC1 to MCn are removed. An erase operation that removes all may be performed.

3 is a schematic perspective view illustrating a structure of memory cell strings of a semiconductor device according to example embodiments.

Referring to FIG. 3 , the semiconductor device 100 includes a substrate 101 , channel holes CH extending in a direction perpendicular to a top surface of the substrate 101 , and channel holes CH having a channel region 140 disposed therein. It may include a plurality of interlayer insulating layers 120 and a plurality of gate electrodes 130 stacked along the outer wall of (CH). In addition, the semiconductor device 100 includes a gate dielectric layer 150 disposed between the channel region 140 and the gate electrodes 130 , epitaxial layers 107 disposed below the channel regions 140 , It further includes channel pads 160 on top of the channel holes CH, an impurity region 105 in the substrate 101 between the gate electrodes 130 , and a conductive layer 170 on the impurity region 105 . can do. In FIG. 3 , some components such as the upper wiring structure, for example, the bit lines BL1 to BLm (refer to FIG. 2 ) are omitted and illustrated.

In the semiconductor device 100 , one memory cell string may be configured around each channel region 140 , and a plurality of memory cell strings may be arranged in columns and rows in the x-direction and the y-direction.

The substrate 101 may have an upper surface extending in the x-direction and the y-direction. The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer or as an epitaxial layer.

The channel holes CH may be disposed to be spaced apart from each other while forming rows and columns on the substrate 101 and may be disposed to be shifted from each other in the y-direction. That is, the channel holes CH may be disposed to form a grid pattern or may be disposed in a zigzag shape in one direction. The channel holes CH may have inclined sides that become narrower as they get closer to the substrate 101 according to the aspect ratio. However, the arrangement of the channel holes CH may vary according to embodiments, and is not limited to the illustrated form.

The columnar channel region 140 may be disposed in the channel hole CH extending in a direction perpendicular to the upper surface of the substrate 101 . In the channel hole CH, the channel region 140 may be formed in an annular shape surrounding the channel insulating layer 162 therein. However, according to an embodiment, the channel region 140 may be formed with a cylinder or a prism without the channel insulating layer 162 . It may have the same column shape. A part of the channel region 140 may be a dummy channel region. The channel region 140 may be connected to the substrate 101 through the epitaxial layer 107 at the bottom. The channel region 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material containing p-type or n-type impurities.

A plurality of gate electrodes 131-138: 130 may be disposed to be spaced apart from the substrate 101 in a vertical direction along side surfaces of each of the channel holes CH. Referring to FIG. 2 together, each of the gate electrodes 130 may form a gate of the ground select transistor GST, the plurality of memory cells MC1 to MCn, and the string select transistor SST. The gate electrode 130 may extend to form the word lines WL1 to WLn, and may be commonly connected to adjacent memory cell strings of predetermined units arranged in the x-direction and the y-direction. In example embodiments, five gate electrodes 132 to 136 of the memory cells MC1 to MCn may be arranged, but not limited thereto, and the memory cells MC1 to MCn may be arranged according to the capacity of the semiconductor device 100 . The number of gate electrodes 130 constituting the MCn) may be determined. For example, the number of gate electrodes 130 constituting the memory cells MC1 to MCn may be 2 ⁿ (n is a natural number).

The gate electrode 131 of the ground select transistor GST may extend in the y-direction to form the ground select line GSL. For the function of the ground select transistor GST, a predetermined impurity may also be doped into the substrate 101 under the gate electrode 131 .

The gate electrodes 137 and 138 of the string select transistor SST may extend in the y-direction to form the string select line SSL. The gate electrodes 137 and 138 of the string selection transistor SST disposed on a straight line in the x-direction have a separate wiring structure, so that adjacent memory cell strings have different bit lines BL1 to BLm (refer to FIG. 2 ). can be connected to each. In example embodiments, the gate electrodes 137 and 138 of the string select transistor SST may be formed to be separated from each other between adjacent memory cell strings in the x-direction to form different string select lines SSL. . According to an embodiment, each of the gate electrodes 137 and 138 of the string select transistor SST and the gate electrode 131 of the ground select transistor GST may be one or two or more, and the memory cells MC1 to MCn ) may have the same or different structures as the gate electrodes 132 to 136 .

In addition, some gate electrodes 130 , for example, gate electrodes 130 adjacent to the gate electrode 131 of the ground select transistor GST or the gate electrodes 137 and 138 of the string select transistor SST. may be a dummy gate electrode. For example, the gate electrode 132 adjacent to the gate electrode 131 of the ground select transistor GST may be a dummy gate electrode.

The gate electrodes 130 may include polycrystalline silicon or a metal silicide material. The metal silicide material may be, for example, a silicide material of a metal selected from Co, Ni, Hf, Pt, W, and Ti, or a combination thereof. In some embodiments, the gate electrodes 130 may include a metal material, for example, tungsten (W). Also, although not shown separately, the gate electrodes 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN). ) or a combination thereof.

A plurality of interlayer insulating layers 121-128 (120) may be arranged between the gate electrodes 130 . Like the gate electrodes 130 , the interlayer insulating layers 120 may be spaced apart from each other in the z-direction and may be arranged to extend in the y-direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

The first insulating layer 180 may be disposed on top of the gate electrodes 130 . The first insulating layer 180 may include an insulating material such as silicon oxide or silicon nitride, like the interlayer insulating layers 120 .

The channel pads 160 may be disposed on top of the memory cell strings to cover a top surface of the channel insulating layers 162 and to be electrically connected to the channel regions 140 . The channel pads 160 may serve as drain regions of the string select transistor SST (refer to FIG. 2 ). The channel pads 160 may be electrically connected to the bit lines BL1 to BLm (refer to FIG. 2 ) by a connection structure such as a contact plug.

The channel pads 160 may have an upper surface 160U and a lower surface 160L that are curved in different directions. The channel pads 160 may have a convex top surface 160U. In particular, the upper surface 160U of the channel pad 160 may have a convex shape toward an upper portion in a direction away from the substrate 101 . At least a portion of the upper surface 160U of the channel pad 160 may protrude from the first insulating layer 180 . With this shape, the channel pad 160 may be stably connected to the upper wiring structure.

Alternatively, the lower surfaces 160L of the channel pads 160 may be convex toward the substrate 101 . Accordingly, the channel pads 160 may have a first height H1 , which is the maximum height at the center, and may decrease in thickness toward the edge. The first height H1 may be in a range of about 600 Å to 1200 Å. The channel pads 160 may protrude from the first insulating layer 180 by a second height H2 from the center. The second height H2 may be several Å to several tens of Å. The channel pads 160 may be spaced apart from the uppermost gate electrode 138 by a third height H3 . The third height H3 may be in a range of about 600 Å to 1200 Å, and may be greater than the first height H1, but is not limited thereto.

Sides of the channel pads 160 may be in contact with the channel region 140 . In the present embodiment, it is illustrated that the side surfaces of the channel pads 160 are surrounded by the channel region 140 and the gate dielectric layer 150, but embodiments are not limited thereto. For example, in some embodiments, only the channel region 140 may be disposed on the side surfaces of the channel pads 160 , or neither the channel region 140 nor the gate dielectric layer 150 may be disposed. In this case, the channel pad 160 may extend to the sidewall of the channel hole CH and contact the first insulating layer 180 .

The channel pads 160 may include, for example, doped polycrystalline silicon. The channel pads 160 may include p-type or n-type impurities.

The gate dielectric layer 150 may be disposed between the gate electrodes 130 and the channel region 140 in the channel hole CH. The gate dielectric layer 150 may extend vertically on the substrate 101 along the channel region 140 . The gate dielectric layer 150 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel region 140 . This will be described in more detail with reference to FIGS. 4A to 4C below.

The epitaxial layer 107 is disposed on the substrate 101 at lower ends of the channel holes CH, and may be disposed on a side surface of the at least one gate electrode 130 . The epitaxial layer 107 may be disposed in the recessed region of the substrate 101 . The height of the upper surface of the epitaxial layer 107 may be higher than the upper surface of the lowermost gate electrode 131 , and may be lower than the lower surface of the upper gate electrode 132 . Even when the aspect ratio of the channel region 140 is increased due to the epitaxial layer 107 , the channel region 140 may be stably electrically connected to the substrate 101 , and a ground select transistor (GST) between the memory cell strings may be used. characteristics can be uniform. However, in exemplary embodiments, the epitaxial layer 107 may be omitted, and in this case, the channel region 140 may be directly connected to the substrate 101 .

The epitaxial layer 107 may be a layer formed using a selective epitaxial growth (SEG) process. The epitaxial layer 107 may be formed of a single layer or a plurality of layers. The epitaxial layer 107 may include polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal germanium doped or undoped with impurities. For example, when the substrate 101 is made of single crystal silicon (Si), the epitaxial layer 107 may also be made of single crystal silicon. In example embodiments, even when the substrate 101 is single crystal silicon (Si), at least a portion of the epitaxial layer 107 may have a polycrystalline silicon structure including a plurality of grains.

The conductive layer 170 may be connected to the substrate 101 through the gate electrodes 130 and the interlayer insulating layers 120 between the channel regions 140 , and a gated by the buried insulating layer 164 . It may be electrically insulated from the electrodes 130 . Accordingly, the gate electrodes 130 may be separated from each other in the x-direction with the conductive layer 170 interposed therebetween. The conductive layer 170 may be disposed in a line shape extending in the y-direction. The conductive layers 170 may be arranged at predetermined intervals in the x-direction, for example, one for every second to fourth column of the channel region 140 , but is not limited thereto. Due to the high aspect ratio, the conductive layer 170 may have a shape in which the width decreases toward the substrate 101 , but is not limited thereto.

The impurity region 105 may be disposed in the substrate 101 under the conductive layer 170 . The impurity region 105 may extend in the y-direction adjacent to the top surface of the substrate 101 . The impurity region 105 may include an impurity of the same conductivity type as that of the substrate 101 , and when it contains an impurity of the same conductivity type, it may contain a higher concentration than that of the substrate 101 . The conductive layer 170 may apply a voltage to the substrate 101 through the impurity region 105 .

4A to 4C are cross-sectional views illustrating a gate dielectric layer according to example embodiments, and a region corresponding to region 'A' of FIG. 3 is shown.

Referring to FIG. 4A , the gate electrode 132 , the gate dielectric layer 150 and the channel region 140 of the memory cell strings are shown. The gate dielectric layer 150 may include a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156 sequentially stacked from the channel region 140 .

The tunneling layer 152 may tunnel charges into the charge storage layer 154 in an FN tunneling method. The tunneling layer 152 may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof.

The charge storage layer 154 may be a charge trap layer or a floating gate conductive layer. For example, the charge storage layer 154 may include a dielectric material, quantum dots, or nanocrystals. Here, the quantum dots or nanocrystals may be composed of fine particles of a conductor, for example, a metal or a semiconductor. In example embodiments, when the charge storage layer 154 is a charge trap layer, the charge storage layer 154 may be formed of silicon nitride.

The blocking layer 156 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. The high-k dielectric material is, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ) may be any one.

Referring to FIG. 4B , the gate electrode 132 , the gate dielectric layer 150a and the channel region 140 of the memory cell strings are shown. The gate dielectric layer 150a may have a structure in which a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156a are sequentially stacked from the channel region 140 . The relative thicknesses of the layers constituting the gate dielectric layer 150a are not limited to those shown in the drawings and may be variously changed.

In particular, in the gate dielectric layer 150a of this embodiment, unlike the embodiment of FIG. 4A , the tunneling layer 152 and the charge storage layer 154 are arranged to extend vertically along the channel region 140, but the blocking layer ( 156a may be disposed to surround the gate electrode layer 132 .

Referring to FIG. 4C , the gate electrode 132 , the gate dielectric layer 150b and the channel region 140 of the memory cell strings are shown. The gate dielectric layer 150b may have a structure in which a tunneling layer 152b, a charge storage layer 154b, and a blocking layer 156b are sequentially stacked from the channel region 140 .

In particular, in the gate dielectric layer 150b of this embodiment, unlike the embodiments of FIGS. 4A and 4B , the tunneling layer 152b, the charge storage layer 154b and the blocking layer 156b all form the gate electrode layer 132 . It may be arranged to surround. In some embodiments, a portion of the blocking layer 156b may be disposed to extend vertically along the channel region 140 , and a portion may be disposed to surround the gate electrode layer 132 .

5A to 5C are cross-sectional views illustrating channel pads according to example embodiments, and a region corresponding to region 'B' of FIG. 3 is shown.

Referring to FIG. 5A , the channel region 140 in the channel hole CH, the gate dielectric layer 150 and the channel pad 160a are shown. The channel pad 160a may have a convex upper surface 160aU.

In particular, the channel pad 160a of this embodiment may have a flat lower surface 160aL, unlike the embodiment of FIG. 3 . The shape of the lower surface 160aL of the channel pad 160a may be changed according to a manufacturing method.

Referring to FIG. 5B , the channel region 140 in the channel hole CH, the gate dielectric layer 150 and the channel pad 160b are shown. The channel pad 160b may have an upper convex upper surface 160bU and a lower convex lower surface 160bL.

In particular, in the channel pad 160b of this embodiment, unlike the embodiment of FIG. 3 , the entire channel hole CH may protrude upward from the first insulating layer 180 . That is, the channel region 140 and the gate dielectric layer 150 surrounding the side surface of the channel pad 160b may protrude from the first insulating layer 180 together with the channel pad 160b. The gate dielectric layer 150 may protrude from the first insulating layer 180 to a fourth height H4 , and the fourth height H4 may range from, for example, several Å to several tens of Å.

5C shows the channel region 140, the gate dielectric layer 150, and the channel pad 160c in the channel hole CH. The channel pad 160c may have an upper convex upper surface 160cU and a lower convex lower surface 160cL.

In particular, in the channel pad 160c of the present embodiment, unlike the embodiment of FIG. 3 , the width W2 of the lower surface 160cL may be smaller than the width W1 of the upper surface 160cU. This may be because the channel hole CH has a shape in which the width decreases toward the bottom toward the substrate 101 . When the channel hole CH has a high aspect ratio, it may be formed in a shape that decreases in width toward the bottom according to the forming process, and accordingly, the channel pad 160c filling the upper end of the channel hole CH is also formed on the upper surface ( 160cU) and the lower surface 160cL may have different widths.

6 is an electron micrograph for explaining channel pads according to example embodiments.

Referring to FIG. 6 , the channel pad 160 analyzed by scanning electron microscopy (SEM) is shown. The gate dielectric layer 150 and the channel region 140 may be sequentially disposed in the channel hole CH from the sidewall. A channel insulating layer 162 may fill the channel hole CH at a lower portion of the channel hole CH, and a channel pad 160 may be disposed on the channel insulating layer 162 at an upper end thereof.

The channel pad 160 may have an upper surface 160U that is convex toward the top, and the degree of convexity may be variously changed in some embodiments. In addition, the channel pad 160 may have a lower surface 160L convex toward the bottom. The channel region 140 and the channel pad 160 may be made of the same material, and in this case, as shown in FIG. 6 , it may be difficult to distinguish the boundary in a photograph.

Also, in this embodiment, similar to the embodiment of FIG. 4B , a portion of the gate dielectric layer 150 may be disposed between the gate electrode 138 and the channel hole CH.

7A to 7J are main step-by-step views schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. 7A to 7J , a method of manufacturing the semiconductor device 100 of FIG. 3 is described.

Referring to FIG. 7A , after sacrificial layers 111-117: 110 and interlayer insulating layers 121-128: 120 are alternately stacked on the substrate 101, the first insulating layer 180 is formed on the uppermost part. can be formed in Through a subsequent process, the sacrificial layers 110 may be replaced with the gate electrode 130 .

First, the interlayer insulating layer 121 may be formed, and the sacrificial layers 110 and the interlayer insulating layers 120 may be alternately stacked on the substrate 101 as shown to form a stacked structure. The sacrificial layers 110 may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers 120 . That is, the sacrificial layers 110 may be formed of a material that can be etched while minimizing the etching of the interlayer insulating layers 120 during the process of etching the sacrificial layers 110 . The etch selectivity or etch selectivity may be quantitatively expressed through a ratio of the etch rate of the sacrificial layers 110 to the etch rate of the interlayer insulating layer 120 . For example, the interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the sacrificial layers 110 may include an interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. and other materials.

In some embodiments, the thicknesses of the interlayer insulating layers 120 may not all be the same. For example, the lowermost interlayer insulating layer 121 may be formed to be relatively thin. In addition, in some embodiments, the interlayer insulating layers 122 and 126 disposed between the ground select transistor GST and the string select transistor SST of FIG. 2 and the memory cells MC1 to MCn are the memory cells ( It may be formed to be relatively thicker than the interlayer insulating layers 123 to 125 disposed between MC1 to MCn. The thicknesses of the interlayer insulating layers 120 and the sacrificial layers 110 may be variously modified from those shown, and the number of layers constituting the interlayer insulating layers 120 and the sacrificial layers 110 may also vary. can be changed to

The first insulating layer 180 formed on the uppermost portion may include a region where the channel pad 160 (refer to FIG. 3 ) is subsequently formed, and has a relatively thicker thickness T1 than that of the interlayer insulating layers 120 . can be formed with The thickness T1 may range from 1.5 times to 2.5 times the thickness of the channel pad 160 . For example, the thickness T1 may be in the range of about 1000 Å to 2200 Å, for example, in the range of about 1500 Å to 2000 Å. When the first insulating layer 180 is thicker than the above range, an amount to be removed during a subsequent planarization process increases, and dishing may occur in the channel pad 160 . When the first insulating layer 180 is thinner than the above range, the distance to the uppermost gate electrode 138 to be formed later becomes close, and a defect may occur.

The first insulating layer 180 may be, for example, a Tetra-Ethly-Ortho-Silicate (TEOS) oxide film.

Referring to FIG. 7B , first to third mask layers 182 , 184 , and 186 are to be formed on the stacked interlayer insulating layers 120 , the sacrificial layers 110 , and the first insulating layer 180 . can

The first and second mask layers 182 and 184 may be made of different materials, and thus may have etch selectivity from each other. The second mask layer 184 may be made of the same material as the interlayer insulating layers 120 . For example, the first mask layer 182 may be silicon nitride, and the second mask layer 184 may be silicon nitride such as TEOS.

The third mask layer 186 may be, for example, a photoresist layer, and may be patterned to open regions corresponding to the channel holes CH (refer to FIG. 3 ).

Referring to FIG. 7C , channel holes CH may be formed using the third mask layer 186 .

The channel holes CH may be formed by anisotropically etching the first and second mask layers 182 and 184 , the first insulating layer 180 , the sacrificial layers 110 , and the interlayer insulating layers 120 . have. During the etching, the second mask layer 184 may function as a hard mask layer. A portion of the substrate 101 may be recessed by the channel holes CH, but is not limited thereto.

Since the stack structure including different types of layers is etched, sidewalls of the channel holes CH may not be perpendicular to the top surface of the substrate 101 in some embodiments. For example, in some embodiments, the width of the channel holes CH may decrease as it approaches the upper surface of the substrate 101 .

Referring to FIG. 7D , an epitaxial layer 107 , a gate dielectric layer 150 , a channel region 140 , and a preliminary channel insulating layer 162P may be formed in the channel holes CH.

First, an epitaxial layer 107 may be formed on the recessed region of the substrate 101 . The epitaxial layer 107 may be grown from the substrate 101 using SEG, and may be formed of a single layer or a plurality of layers. The epitaxial layer 107 may include polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal germanium doped or undoped with impurities. The epitaxial layer 107 may have a top surface higher than the top surface of the sacrificial layer 111 replaced with the gate electrode 131 of the ground selection transistor GST (refer to FIG. 2 ).

Next, the gate dielectric layer 150 may be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this step, all or part of the gate dielectric layer 150 may be formed, and a portion extending perpendicularly to the substrate 101 along the channel hole CH may be formed in this step. The channel region 140 may be formed on the gate dielectric layer 150 in the channel holes CH.

The preliminary channel insulating layer 162P is formed to fill the channel holes CH, and may be an insulating material. However, in some embodiments, the space between the channel regions 140 may be filled with a conductive material other than the preliminary channel insulating layer 162P. In this step, the preliminary channel insulating layer 162P may be formed on the second mask layer 184 to fill the channel holes CH.

Referring to FIG. 7E , the channel insulating layer 162 may be formed by removing a portion of the preliminary channel insulating layer 162P from the upper ends of the channel holes CH.

First, a planarization process such as a chemical mechanical polishing (CMP) process is performed using the first mask layer 182 as a stop layer to remove materials of the preliminary channel insulating layer 162P formed thereon; A flat upper surface of the laminate structure may be formed. Accordingly, the second mask layer 184 may be removed. However, this process is optional and may be omitted.

Next, a portion of the preliminary channel insulating layer 162P may be removed using an etch-back process. The upper surface of the channel insulating layer 162 formed by this process may be located in the first insulating layer 180 and may have a convex shape toward the substrate 101 . In some embodiments, when a portion of the preliminary channel insulating layer 162P is removed, at least a portion of the side channel region 140 and/or the gate dielectric layer 150 may also be removed. During the planarization process or the etch-back process, the first mask layer 182 may also be partially removed, and thus may have a thickness T3 reduced from the thickness T2 (refer to FIG. 7D ) in the previous step. .

Referring to FIG. 7F , a channel pad layer 160P may be formed on the channel insulating layer 162 .

A conductive material may be deposited to fill the channel holes CH on the channel insulating layer 162 and a channel pad layer 160P extending over the stacked structure may be formed. A channel pad layer 160P may be formed with a predetermined thickness T4 on the upper surface of the first mask layer 182 . The thickness T4 may be determined as a minimum thickness within a range in which all of the plurality of channel holes CH can be stably filled.

In this step, the channel pad layer 160P formed in the channel holes CH may be formed so as not to include defects such as voids therein by adjusting the depth thereof. The depth at which the channel pad layer 160P is formed may be determined according to the thicknesses of the first insulating layer 180 and the first mask layer 182 and the desired thickness of the channel pad 160. In the embodiment of the present invention, In particular, as described above with reference to FIG. 7A , the depth may be adjusted by adjusting the thickness of the first insulating layer 180 .

Referring to FIG. 7G , the channel pads 160 may be formed by removing a portion of the channel pad layer 160P to remain only in the channel holes CH.

First, a planarization process such as CMP may be performed using the first mask layer 182 as a stop layer to remove the channel pad layer 160P on the first mask layer 182 .

Next, a planarization process such as CMP may be performed using the first insulating layer 180 to remove the channel pad layer 160P and the first mask layer 182 on the first mask layer 182 . . At this time, since the planarization process is mainly performed under the condition of removing the first mask layer 182 , the channel pad layer 160P may not be removed relatively well, whereby the top surfaces of the channel pads 160 are convex. can be formed. In addition, since the first insulating layer 180 is hardly removed, a phenomenon such as dishing in the channel pad 160 can be prevented. The lower surfaces of the channel pads 160 may be convex downwards due to the shape of the channel insulating layer 162 .

After the channel pads 160 are formed, the thickness T5 of the first insulating layer 180 may be the same as the thickness T1 at the time of initial formation (refer to FIG. 7A ), or may be slightly smaller as a small amount is removed in this step. have. The thickness T5 may be in the range of about 1.5 to 2.5 times the thickness of the channel pad 160 , for example, about 1.5 to 2 times.

Referring to FIG. 7H , after forming the second insulating layer 188 on the channel pad 160 , an opening ( OP) may be formed, and the sacrificial layers 110 exposed through the opening OP may be removed.

The second insulating layer 188 may prevent damage to the channel pad 160 and the channel region 140 thereunder. The interface between the first and second insulating layers 180 and 188 may be formed at an edge of the channel region 140 and the gate dielectric layer 150 adjacent to the top surface 160U of the channel pad 160 .

The opening OP may be formed by forming a mask layer using a photolithography process and anisotropically etching the stack of the sacrificial layers 110 and the interlayer insulating layers 120 . The opening OP may be formed in the form of a trench extending in the y direction (refer to FIG. 3 ). The opening OP may expose the substrate 101 between the channel regions 140 . The sacrificial layers 110 may be removed by an etching process, and thus a plurality of side openings may be formed between the interlayer insulating layers 120 . Some sidewalls of the gate dielectric layer 150 may be exposed through the side openings.

Referring to FIG. 7I , the gate electrode 130 may be formed in the side openings from which the sacrificial layer 110 is removed.

The gate electrodes 130 may include a metal, polycrystalline silicon, or a metal silicide material. The metal silicide material may be, for example, a silicide material of a metal selected from Co, Ni, Hf, Pt, W, and Ti, or a combination thereof. When the gate electrodes 130 are made of a metal silicide material, the gate electrodes 130 may be formed by burying silicon (Si) in the tunnel portions TP and then performing a silicidation process by forming a separate metal layer. can

After the gate electrode 130 is formed, the material forming the gate electrode 130 formed in the opening OP may be removed through an additional process so that the gate electrode 130 is disposed only in the side openings. In this step, the interlayer insulating layer 120 may protrude more than the gate electrode 130 toward the opening OP as illustrated, but is not limited thereto.

Referring to FIG. 7J , an impurity region 105 may be formed in the substrate 101 in the opening OP, and a buried insulating layer 164 and a conductive layer 170 may be formed on the impurity region 105 .

First, the impurity region 105 may be formed by implanting impurities into the substrate 101 exposed by the opening OP. Next, a buried insulating layer 164 may be formed on a sidewall of the opening OP. The buried insulating layer 164 may be manufactured in the form of a spacer by forming an insulating material and removing the insulating material from the substrate 101 so that the top surface of the substrate 101 is exposed. In example embodiments, the impurity region 105 may be formed after at least a portion of the buried insulating layer 164 is first formed. In example embodiments, the buried insulating layer 164 may be formed of a multilayer film.

Next, the conductive layer 170 may be formed in a region defined by the buried insulating layer 164 . Before the formation of the conductive layer 170 , a diffusion barrier layer may be further formed on the buried insulating layer 164 . The diffusion barrier layer may include, for example, a nitride such as TiN or WN.

Thereafter, contact holes penetrating the second insulating layer 188 may be formed on the channel pads 160 , and contact plugs 190 filling the contact holes may be formed. In the present embodiment, since the channel pads 160 have a convex top surface toward the top, when the plurality of contact plugs 190 are formed in this step, there is a problem that some of them are not connected to the channel pads 160 . can be prevented from occurring. That is, the convex top surface of the channel pads 160 makes it possible to secure a process margin when the contact holes are formed, thereby preventing the channel pads 160 from being exposed by the contact holes. there will be

In some embodiments, the contact plugs 190 may be formed to partially recess the channel pads 160 . The contact plugs 190 may connect the channel pads 160 to wiring structures such as the bit lines BL1 to BLm (refer to FIG. 2 ).

The contact plugs 190 may be formed of a conductive material, for example, a metal such as tungsten (W), aluminum (Al), or copper (Cu).

8 and 9 are schematic perspective views of a semiconductor device according to example embodiments.

Referring to FIG. 8 , the semiconductor device 100a includes a substrate 101 , channel holes CH having a channel region 140 disposed therein, a plurality of interlayer insulating layers 120 , and a plurality of gate electrodes. 130 , a gate dielectric layer 150 , epitaxial layers 107 , channel pads 160 , an impurity region 105 , and a conductive layer 170 . Also, the semiconductor device 100a may further include contact plugs 190 and bit lines 195 on the channel pads 160 .

The channel pads 160 may be electrically connected to the bit lines 195 through contact plugs 190 . In the present embodiment, since the channel pads 160 have upper surfaces convex toward the top, they may be electrically and stably connected to the contact plugs 190 .

The contact plugs 190 may have a shape that decreases in width toward the bottom, but is not limited thereto. In some embodiments, the contact plugs 190 may be formed to recess upper portions of the channel pads 160 to a predetermined depth.

The bit lines 195 may extend above the contact plugs 190 in one direction, for example, the x-direction. The bit lines 195 may be arranged such that channel pads 160 arranged on a straight line in the x-direction are connected to different bit lines 195 . To this end, in some embodiments, the bit lines 195 may have a structure further including additional wiring lines and contact plugs positioned below or above.

The contact plugs 190 and the bit lines 195 may include a conductive material, for example, a metal such as tungsten (W), aluminum (Al), or copper (Cu).

Referring to FIG. 9 , the semiconductor device 100b includes a substrate 101 , channel holes CH having a channel region 140 disposed therein, a plurality of interlayer insulating layers 120 , and a plurality of gate electrodes. 130 , a horizontal portion SP disposed on the substrate 101 and including a region in which the channel region 140 horizontally extends, a horizontal filling layer 108 outside the horizontal portion SP, and a gate dielectric layer 150 . ) and channel pads 160 .

In particular, the semiconductor device 100b according to the present embodiment may further include a horizontal portion SP disposed under the gate electrode 130 . In some embodiments, the horizontal portion SP may be disposed in the substrate 101 .

The horizontal portion SP may be connected to the channel holes CH, may be disposed as a layer parallel to the upper surface of the substrate 101 , and may have a structure connected between at least some of the channel holes CH. The horizontal portion SP may have a plate-shaped structure connected to each other between at least some channel holes CH, and the number of channel holes CH connected by the horizontal portion SP may vary in the embodiments. It can be variously changed.

The horizontal portion SP may be formed of a part of the gate dielectric layer 150 and the channel region 140 . That is, the horizontal portion SP may be formed by extending the channel region 140 and the gate dielectric layer 150 from the channel holes CH in the horizontal direction. The gate dielectric layer 150 may be disposed on the lower surface and side surfaces of the horizontal portion SP, and the inside of the horizontal portion SP may be filled with the channel region 140 . However, the arrangement of the channel region 140 and the gate dielectric layer 150 in the horizontal portion SP is not limited thereto, and may be variously changed in embodiments.

The horizontal filling layer 108 may be disposed on the outside of the horizontal part SP and horizontally with the horizontal part SP. That is, the horizontal filling layer 108 may form one layer parallel to the upper surface of the substrate 101 together with the horizontal portion SP. The horizontal filling layer 108 may be formed of a conductive material, for example, a semiconductor material, but is not limited thereto. In some embodiments, the horizontal filling layer 108 may be omitted, and in this case, the horizontal portion SP may extend to an area in which the horizontal filling layer 108 is formed.

In the present embodiment, some of the channel pads 160 may be connected to the bit line 195 (refer to FIG. 8 ) at an upper portion, and some may be connected to a wiring line to which an electrical signal different from the bit line 195 is applied.

10 is a schematic perspective view of a semiconductor device according to example embodiments.

Referring to FIG. 10 , the semiconductor device 200 may include a cell region CELL and a peripheral circuit region PERI.

The cell region CELL may correspond to a region in which the memory cell array 20 of FIG. 1 is disposed, and the peripheral circuit region PERI is a region in which the driving circuit 30 of the memory cell array 20 of FIG. 1 is disposed. may be in the area. The cell region CELL may be disposed on top of the peripheral circuit region PERI. In example embodiments, the cell region CELL may be disposed below the peripheral circuit region PERI.

The cell region CELL includes the semiconductor device 100 , the substrate 101 , the channel holes CH extending in a direction perpendicular to the upper surface of the substrate 101 , and the channel region 140 disposed therein. It may include a plurality of interlayer insulating layers 120 and a plurality of gate electrodes 130 stacked along the outer wall of the devices CH. In addition, the semiconductor device 100 includes a gate dielectric layer 150 disposed between the channel region 140 and the gate electrodes 130 , epitaxial layers 107 disposed below the channel regions 140 , It further includes channel pads 160 on top of the channel holes CH, an impurity region 105 in the substrate 101 between the gate electrodes 130 , and a conductive layer 170 on the impurity region 105 . can do.

In the present embodiment, the cell region CELL is illustrated as having the same structure as the embodiment of FIG. 3 , but is not limited thereto. The cell region CELL may include, for example, a semiconductor device having a structure according to various embodiments of the present disclosure as described above with reference to FIGS. 4A to 5C , 8 and 9 .

The peripheral circuit region PERI may include a base substrate 201 , circuit elements 230 disposed on the base substrate 201 , contact plugs 250 , and wiring lines 260 .

The base substrate 201 may have a top surface extending in the x-direction and the y-direction. The base substrate 201 may have a device isolation layer 210 formed thereon to define an active region. A doped region 205 including impurities may be disposed in a portion of the active region. The base substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

The circuit element 230 may include a horizontal transistor. Each circuit element 230 may include a circuit gate insulating layer 232 , a spacer layer 234 , and a circuit gate electrode 235 . A doped region 205 may be disposed in the base substrate 201 on both sides of the circuit gate electrode 235 to serve as a source region or a drain region of the circuit device 230 .

A plurality of peripheral region insulating layers 244 , 246 , and 248 may be disposed on the circuit device 230 on the base substrate 201 .

The contact plugs 250 may be connected to the doped region 205 through the peripheral region insulating layer 244 . An electrical signal may be applied to the circuit element 230 by the contact plugs 250 . In an area not shown, the contact plugs 250 may also be connected to the circuit gate electrode 235 . The wiring lines 260 may be connected to the contact plugs 250 and may be arranged in a plurality of layers in example embodiments.

After the peripheral circuit region PERI is first manufactured, the substrate 101 of the cell region CELL may be formed thereon to manufacture the cell region CELL. The substrate 101 may have the same size as the base substrate 201 or may be formed smaller than the base substrate 201 . The substrate 101 may be formed of polycrystalline silicon or single-crystallized after being formed of amorphous silicon.

The cell region CELL and the peripheral circuit region PERI may be connected to each other in an area not shown. For example, one end of the gate electrode 130 in the y direction may be electrically connected to the circuit element 230 .

11 is a block diagram illustrating a storage device including a semiconductor device according to example embodiments.

Referring to FIG. 11 , the storage device 1000 according to the present embodiment may include a controller 1010 communicating with a host HOST and memories 1020-1, 1020-2, and 1020-3 for storing data. can Each of the memories 1020-1, 1020-2, and 1020-3 may include a semiconductor device according to various embodiments of the present disclosure as described above with reference to FIGS. 3 to 5C and FIGS. 8 to 10 . have.

The host (HOST) communicating with the controller 1010 may be various electronic devices to which the storage device 1000 is mounted, and may be, for example, a smart phone, a digital camera, a desktop, a laptop, or a media player. The controller 1010 receives a data write or read request transmitted from the host and stores data in the memories 1020-1, 1020-2, and 1020-3, or the memory 1020-1, 1020-2, A command (CMD) for fetching data from 1020-3) may be generated.

11 , one or more memories 1020-1, 1020-2, and 1020-3 in the storage device 1000 may be connected to the controller 1010 in parallel. By connecting the plurality of memories 1020-1, 1020-2, and 1020-3 to the controller 1010 in parallel, the storage device 1000 having a large capacity, such as a solid state drive (SSD), may be implemented.

12 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments.

Referring to FIG. 12 , the electronic device 2000 according to the present embodiment may include a communication unit 2010 , an input unit 2020 , an output unit 2030 , a memory 2040 , and a processor 2050 .

The communication unit 2010 may include a wired/wireless communication module, and may include a wireless Internet module, a short-range communication module, a GPS module, a mobile communication module, and the like. The wired/wireless communication module included in the communication unit 2010 may be connected to an external communication network according to various communication standards to transmit/receive data.

The input unit 2020 is a module provided for a user to control the operation of the electronic device 2000 , and may include a mechanical switch, a touch screen, a voice recognition module, and the like. In addition, the input unit 2020 may include a mouse or a finger mouse device that operates in a track ball or laser pointer method, and may further include various sensor modules through which a user can input data.

The output unit 2030 outputs information processed by the electronic device 2000 in the form of audio or video, and the memory 2040 may store a program or data for processing and controlling the processor 2050 or data. . The processor 2050 may store or retrieve data by transmitting a command to the memory 2040 according to a required operation.

The memory 2040 may be embedded in the electronic device 2000 or may communicate with the processor 2050 through a separate interface. When communicating with the processor 2050 through a separate interface, the processor 2050 may store or retrieve data from the memory 2040 through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB, etc. .

The processor 2050 controls the operation of each unit included in the electronic device 2000 . The processor 2050 may perform control and processing related to voice calls, video calls, data communication, and the like, or may perform control and processing for multimedia reproduction and management. In addition, the processor 2050 may process an input transmitted from the user through the input unit 2020 and output the result through the output unit 2030 . Also, as described above, the processor 2050 may store or retrieve data necessary for controlling the operation of the electronic device 2000 in the memory 2040 . At least one of the processor 2050 and the memory 2040 may include a semiconductor device according to various embodiments of the present disclosure as described above with reference to FIGS. 3 to 5C and FIGS. 8 to 10 .

13 is a schematic diagram illustrating a system including a semiconductor device according to example embodiments.

Referring to FIG. 13 , a system 3000 may include a controller 3100 , an input/output device 3200 , a memory 3300 , and an interface 3400 . The system 3000 may be a mobile system or a system for transmitting or receiving information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. can

The controller 3100 may serve to execute a program and control the system 3000 . The controller 3100 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device.

The input/output device 3200 may be used to input or output data of the system 3000 . The system 3000 may be connected to an external device, for example, a personal computer or a network, using the input/output device 3200 to exchange data with the external device. The input/output device 3200 may be, for example, a keypad, a keyboard, or a display.

The memory 3300 may store codes and/or data for operation of the controller 3100 , and/or store data processed by the controller 3100 . The memory 3300 may include the semiconductor device according to any one of the embodiments of the present invention.

The interface 3400 may be a data transmission path between the system 3000 and another external device. The controller 3100 , the input/output device 3200 , the memory 3300 , and the interface 3400 may communicate with each other through the bus 3500 .

At least one of the controller 3100 or the memory 3300 may include a semiconductor device according to various embodiments of the present disclosure as described above with reference to FIGS. 3 to 5C and FIGS. 8 to 10 .

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various types of substitutions, modifications and changes will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and this also falls within the scope of the present invention. something to do.

CH: channel hole 100: semiconductor device
101: substrate 105: impurity region
107: epitaxial layer 110: sacrificial layer
120: interlayer insulating layer 130: gate electrode
140: channel region 150: gate dielectric layer
152: tunneling layer 154: charge storage layer
156: blocking layer 160: channel pad
162: channel insulating layer 164: buried insulating layer
170: conductive layer 180: first insulating layer
182: first mask layer 184: second mask layer
186: third mask layer 188: second insulating layer
190: contact plug 195: bit line

Claims (20)

gate electrodes vertically stacked on the substrate;
channel holes extending perpendicular to the substrate through the gate electrodes and having channel regions respectively;
channel pads disposed on top of each of the channel holes to be connected to the channel region and having a convex top surface; and
first and second insulating layers disposed to have an interface around the upper surfaces of the channel pads;
The channel pads are disposed to protrude from the channel holes and the lower first insulating layer into the second insulating layer disposed thereon,
The channel region protrudes from the first insulating layer.
delete The method of claim 1,
The channel pads have a lower surface convex in a direction opposite to the upper surface.
The method of claim 1,
and a channel insulating layer disposed inside the channel region in each of the channel holes and having an upper surface convex toward the substrate.
delete The method of claim 1,
The channel pads include p-type or n-type impurities.
The method of claim 1,
Further comprising a gate dielectric layer disposed between the gate electrodes and the channel region,
and the gate dielectric layer extends from the channel hole to a side surface of the channel pad.
The method of claim 1,
The channel region extends to a side surface of the channel pad in the channel hole.
The method of claim 1,
The channel pads have a lower width than the upper surface of the semiconductor device.
gate electrodes vertically stacked on the substrate;
channel holes extending perpendicular to the substrate through the gate electrodes and having channel regions respectively;
channel pads disposed on top of each of the channel holes and having upper and lower surfaces curved in different directions; and
first and second insulating layers disposed to have an interface around the upper surfaces of the channel pads;
The channel pads are disposed to protrude from the channel holes and the lower first insulating layer into the second insulating layer disposed thereon,
The channel region protrudes from the first insulating layer.
forming a stacked structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate;
forming an insulating layer and a mask layer on the laminate structure;
forming channel holes penetrating the stacked structure and the insulating layer by using the mask layer;
forming gate dielectric layers and channel regions on sidewalls of the channel holes;
forming channel insulating layers filling the lower portions of the channel holes;
forming a conductive layer on the channel insulating layers to fill the upper portions of the channel holes and extend onto the mask layer; and
and forming channel pads having a convex top surface by removing the conductive layer from an upper portion of the mask layer so as to remain only in the channel holes.
12. The method of claim 11,
In the forming of the channel pads, the conductive layer is removed using a planarization process, and the insulating layer is used as a stop layer during the planarization process.
13. The method of claim 12,
During the planarization process, all of the mask layer is removed and the insulating layer is not removed.
12. The method of claim 11,
At least a portion of upper surfaces of the channel pads protrude from the insulating layer.
12. The method of claim 11,
The mask layer includes a first mask layer formed below and a second mask layer formed on the first mask layer,
The forming of the channel pads comprises:
removing a portion of the conductive layer using the second mask layer as a stop layer; and
and removing a portion of the first mask layer and the conductive layer by using the insulating layer as a stop layer.
16. The method of claim 15,
and removing the second mask layer by a planarization process using the first mask layer as a stop layer after forming the channel insulating layers.
12. The method of claim 11,
The forming of the channel insulating layers comprises:
depositing an insulating material to fill the channel holes; and
and performing an etch-back process to remove the insulating material from upper ends of the channel holes.
18. The method of claim 17,
The method of manufacturing a semiconductor device in which the channel insulating layers have a convex top surface toward the substrate by the etch-back process.
12. The method of claim 11,
The thickness of the insulating layer is in the range of 1.5 to 2.5 times the thickness of the channel pad.
forming a stacked structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate;
forming an insulating layer on the laminate structure;
forming channel holes penetrating the multilayer structure and the insulating layer;
forming gate dielectric layers, channel regions and channel insulating layers in the channel holes; and
and forming channel pads having convex top surfaces on top of the channel holes and protruding at least a portion of the insulating layer.

Images