KR102427646B1 - Semiconductor devices and manufacturing methods of the same - Google Patents

Abstract

In a semiconductor device according to an embodiment of the present invention, gate electrodes stacked vertically on a substrate, channel holes extending perpendicular to the substrate through the gate electrodes, and channel regions in which the channel region is disposed, and lengths different from the gate electrodes are different from each other. It includes gate pads extending to , and contact plugs connected to the gate pads, wherein at least some of the gate pads have a thinner region than the connected gate electrode.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a method for manufacturing the same.

Semiconductor devices require high-capacity data processing while their volume is getting smaller. Accordingly, it is necessary to increase the degree of integration of semiconductor elements constituting such a semiconductor device. Accordingly, as one of methods for improving the degree of integration of a semiconductor device, a semiconductor device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device having an improved degree of integration.

A semiconductor device according to example embodiments may include gate electrodes vertically stacked on a substrate, channel holes extending perpendicular to the substrate through the gate electrodes and having a channel region, and the gate electrodes. It includes gate pads extending to different lengths and contact plugs connected to the gate pads, and at least some of the gate pads may have a region thinner than the connected gate electrode.

For example, the gate pads may include a contact region in which the lower gate pad extends longer than the upper gate pad and is connected to the contact plugs, and a thickness in the contact region is equal to that of the gate electrode. may be thinner than the thickness of

For example, the gate pads may have a thickness smaller than a thickness of the gate electrode in the entire contact region.

For example, the gate pads may have a thickness that gradually decreases in the contact region.

For example, the gate pads may have a bent portion whose thickness is rapidly reduced near the contact region, and may extend horizontally in a region other than the bent portion.

For example, a difference in thickness between each of the gate pads and the connected gate electrode may be different from each other in the gate pads.

For example, in the gate pads, the difference in thickness may increase from the top surface of the substrate to the top.

For example, in the gate pads, the difference in thickness may increase in a group unit including two or more gate pads while moving upward from the top surface of the substrate.

For example, an etch stop layer disposed on the gate pads may be further included, and the contact plugs may pass through the etch stop layer.

For example, the etch stop layer may be in contact with the gate pads.

A semiconductor device according to example embodiments may include: gate electrodes vertically stacked on a substrate; gate pads extending at different lengths from the gate electrodes and having contact regions; and contact plugs connected to the gate pads in the contact region, wherein at least some of the gate pads may have a reduced thickness in the contact region.

For example, the contact region may include a region in which the lower gate pad extends longer than the upper gate pad.

For example, the gate pads may have a stepped portion or a bent portion to reduce a thickness in the contact region.

For example, a difference in thickness between the gate electrode and the gate pad connected to each other may be in a range of about 5 Å to 100 Å.

For example, the degree to which the thickness of the gate pads is reduced may be proportional to or inversely proportional to the distance from the substrate.

A method of manufacturing a semiconductor device according to example embodiments may include alternately stacking sacrificial layers and interlayer insulating layers on a substrate, and forming a mask layer on the stacked sacrificial layers and interlayer insulating layers. , forming pad regions extending in different lengths by removing a portion of the sacrificial layers and interlayer insulating layers using the mask layer, forming a pad insulating layer made of an oxide-based material on the pad region , removing the sacrificial layers, and filling the region from which the sacrificial layers are removed with a conductive material to form gate electrodes, wherein in the forming of the pad insulating layer, the sacrificial layer constituting the pad region At least a portion of the layers may be oxidized to form an oxide layer.

For example, a portion of the sacrificial layers may be oxidized from a top surface by a source material for forming the pad insulating layer.

For example, in the step of removing the sacrificial layers, the oxide layer may remain without being removed.

For example, the gate electrodes may have a reduced thickness under the oxide layer.

For example, the thickness of the oxide layer may increase as the distance from the upper surface of the substrate increases.

Since the gate pads include regions with reduced thickness, a semiconductor device with improved integration can be provided.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic block diagram of a semiconductor device according to example embodiments.
2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to example embodiments.
3 is a schematic plan view of a semiconductor device according to example embodiments.
4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
5A to 5C are cross-sectional views illustrating a gate dielectric layer according to example embodiments.
6A to 6C are cross-sectional views illustrating gate pads according to example embodiments.
7 to 9 are schematic cross-sectional views of semiconductor devices according to example embodiments.
10A to 10K are main step-by-step views schematically illustrating a method of manufacturing a semiconductor device according to example embodiments.
11A to 11D are main step-by-step views schematically illustrating a method of manufacturing a semiconductor device according to example embodiments.
12 is a schematic perspective view of a semiconductor device according to example embodiments.
13 is a block diagram illustrating a storage device including a semiconductor device according to example embodiments.
14 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments.
15 is a schematic diagram illustrating a system including a semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Embodiments of the present invention may be modified in various other forms or various embodiments may be combined, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer description, and elements indicated by the same reference numerals in the drawings are the same elements.

The terminology used herein is used to describe specific embodiments, and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. As used herein, terms such as “comprise,” “comprise,” or “have” are intended to specify that a feature, number, step, action, component, part, or combination thereof described in the specification is present. , the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof should not be construed as precluding the possibility of addition. The term “and/or” includes any one and all combinations of one or more of those listed items.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers and/or parts, these members, parts, regions, layers, and/or parts are limited by these terms, so that It is self-evident that These terms are used only to distinguish one member, component, region, layer or portion from another region, layer or portion. Accordingly, a first member, component, region, layer or portion discussed below may refer to a second member, component, region, layer or portion without departing from the teachings of the present invention.

In this specification, the term 'dummy' is used to refer to a configuration that has the same or similar structure and shape as other components, but does not have a substantial function within, and exists only as a pattern. Therefore, no electrical signal is applied to the 'dummy' component or it does not electrically perform a specific function.

1 is a schematic block diagram of a semiconductor device according to example embodiments.

Referring to FIG. 1 , a semiconductor device 10 according to an embodiment of the present invention includes a memory cell array 20 , a driving circuit 30 , a read/write circuit 40 , and a control circuit 50 . ) may be included.

The memory cell array 20 may include a plurality of memory cells, and the plurality of memory cells may be arranged along a plurality of rows and columns. A plurality of memory cells included in the memory cell array 20 include a word line (WL), a common source line (CSL), a string select line (SSL), and a ground select line ( It may be connected to the driving circuit 30 through a Ground Select Line (GSL), etc., and may be connected to the read/write circuit 40 through a bit line (Bit Line, BL). In some embodiments, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

A plurality of memory cells included in the memory cell array 20 may be divided into a plurality of memory blocks. Each memory block includes a plurality of word lines WL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of bit lines BL, and at least one common source line CSL. ) may be included.

The driving circuit 30 and the read/write circuit 40 may be operated by the control circuit 50 . In one embodiment, the driving circuit 30 receives the address information ADDR from the outside, decodes the received address information ADDR, and the word line WL connected to the memory cell array, the common source line ( CSL), the string select line SSL, and at least some of the ground select line GSL may be selected. The driving circuit 30 may include a driving circuit for each of the word line WL, the string selection line SSL, and the common source line CSL.

The read/write circuit 40 may select at least a portion of the bit lines BL connected to the memory cell array 20 according to a command received from the control circuit 50 . The read/write circuit 40 may read data stored in memory cells connected to at least some of the selected bit lines BL or write data to memory cells connected to at least some of the selected bit lines BL. The read/write circuit 40 may include circuits such as a page buffer, an input/output buffer, and a data latch to perform the above operations.

The control circuit 50 may control the operation of the driving circuit 30 and the read/write circuit 40 in response to the control signal CTRL transmitted from the outside. When data stored in the memory cell array 20 is read, the control circuit 50 controls the operation of the driving circuit 30 to supply a voltage for a read operation to the word line WL in which data to be read is stored. can do. When the voltage for the read operation is supplied to the specific word line WL, the control circuit 50 controls the read/write circuit 40 to store data stored in the memory cell connected to the word line WL to which the voltage for the read operation is supplied. can be controlled to read.

Meanwhile, when data is written to the memory cell array 20 , the control circuit 50 may control the operation of the driving circuit 30 to supply a voltage for a write operation to the word line WL to which data is to be written. have. When the voltage for the write operation is supplied to the specific word line WL, the control circuit 50 writes data to the memory cell connected to the word line WL to which the voltage for the write operation is supplied, the read/write circuit 40 writes data. ) can be controlled.

2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to example embodiments.

2 is an equivalent circuit diagram illustrating a three-dimensional structure of a memory cell array included in the semiconductor device 100A having a vertical structure. Referring to FIG. 2 , in the memory cell array according to the present embodiment, n memory cell elements MC1 to MCn connected in series with each other, and ground selection transistors connected in series to both ends of the memory cell elements MC1 to MCn A plurality of memory cell strings S including a GST and a string select transistor SST may be included.

The n memory cell elements MC1 to MCn connected in series may be respectively connected to the word lines WL1 to WLn for selecting at least some of the memory cell elements MC1 to MCn.

The gate terminal of the ground select transistor GST may be connected to the ground select line GSL, and the source terminal may be connected to the common source line CSL. Meanwhile, a gate terminal of the string select transistor SST may be connected to the string select line SSL, and a source terminal may be connected to a drain terminal of the memory cell device MCn. 2 illustrates a structure in which the ground select transistor GST and the string select transistor SST are connected one by one to the n memory cell elements MC1 to MCn connected in series, but unlike the plurality of ground select transistors ( GST) or a plurality of string select transistors SST may be connected.

A drain terminal of the string select transistor SST may be connected to the bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string select transistor SST through the string select line SSL, the signal applied through the bit lines BL1 to BLm is connected in series to the n memory cell devices MC1 to MCn. By being transferred to , a data read or write operation can be executed. In addition, by applying a signal through the gate selection line GSL to the gate terminal of the gate selection transistor GST whose source terminal is connected to the common source line CSL, the charges stored in the n memory cell elements MC1 to MCn are removed. An erase operation that removes all may be performed.

3 is a schematic plan view of a semiconductor device according to example embodiments. In FIG. 3 , some components such as the pad insulating layer 129 (refer to FIG. 4 ) are omitted and illustrated for convenience of understanding.

4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 4 is a cross-sectional view corresponding to the cutting line I-I' of FIG. 3, respectively.

3 and 4 , the semiconductor device 100 may include a cell region CELL and a pad region PAD. The pad area PAD may be disposed at at least one end of the cell area CELL in the x direction. The cell region CELL may correspond to the memory cell array 20 of FIG. 1 , and the pad region PAD corresponds to a region electrically connecting the memory cell array 20 and the driving circuit 30 of FIG. 1 . can do

In the cell region CELL, the semiconductor device 100 is alternately stacked with the gate electrodes 131 to 137 ( 130 ) and the gate electrodes 130 that are stacked apart from each other in a vertical direction on the substrate 101 . of the interlayer insulating layers 121-127: 120, and the channel holes CH and the channel holes CH extending in a direction perpendicular to the upper surface of the substrate 101 and having the channel region 140 disposed therein. It may include channel pads 160 disposed on top thereof, channel plugs 175 disposed on the channel pads 160 , and first wiring lines 170 . Also, the semiconductor device 100 may further include a channel region 140 and a gate dielectric layer 150 in the channel holes CH. In the semiconductor device 100 , one memory cell string may be configured around each of the channel holes CH, and a plurality of memory cell strings may be arranged in columns and rows in the x-direction and the y-direction.

In the pad region PAD, the semiconductor device 100 has gate pads 131P-137P: 130P extending horizontally from the gate electrodes 131 to 137: 130 and contacts connected to the gate pads 130P. It may include the plugs 180 , the second wiring lines 190 disposed on the contact plugs 180 , and dummy channel holes CHD having the same structure as the channel holes CH.

The substrate 101 may have an upper surface extending in the x-direction and the y-direction. The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer or as an epitaxial layer.

The gate electrodes 130 may be disposed to be spaced apart from the substrate 101 in a vertical direction along side surfaces of each of the channel holes CH. Referring to FIG. 2 together, each of the gate electrodes 130 may form a gate of the ground select transistor GST, the plurality of memory cells MC1 to MCn, and the string select transistor SST. The gate electrodes 130 may extend to form the word lines WL1 to WLn, and may be commonly connected to adjacent memory cell strings of predetermined units arranged in the x-direction and the y-direction. Accordingly, the stack of gate electrodes 130 may be disposed to be separated from each other by the trench TH in the y-direction, as shown in FIG. 3 .

In some embodiments, four gate electrodes 132 to 135 of the memory cells MC1 to MCn may be arranged, but not limited thereto, and the memory cells MC1 to MCn may be arranged according to the capacity of the semiconductor device 100 . ) the number of gate electrodes 130 forming may be determined. For example, the number of gate electrodes 130 constituting the memory cells MC1 to MCn may be 2 ⁿ (n is a natural number).

The gate electrode 131 of the ground select transistor GST may extend in the x direction to form the ground select line GSL. The gate electrodes 136 and 137 of the string select transistor SST may extend in the x direction to form the string select line SSL. The channel holes CH arranged on a straight line in the y-direction may be respectively connected to different first wiring lines 170 according to the arrangement of the upper wiring structure such as the channel plug 175 . In some embodiments, the gate electrodes 136 and 137 of the string select transistor SST are separated from each other between the channel holes CH arranged in one column in the y-direction to form different string select lines SSL. It may be formed to achieve According to an embodiment, each of the gate electrodes 136 and 137 of the string select transistor SST and the gate electrode 131 of the ground select transistor GST may be one or two or more, and the memory cells MC1 to MCn ) may have the same or different structures as the gate electrodes 132 to 135 .

Some of the gate electrodes 130 , for example, the gate electrodes 130 adjacent to the gate electrode 131 of the ground select transistor GST or the gate electrodes 136 and 137 of the string select transistor SST are dummy It may be a gate electrode. For example, the gate electrode 132 adjacent to the gate electrode 131 of the ground select transistor GST may be a dummy gate electrode.

The gate electrodes 130 may include polycrystalline silicon or a metal silicide material. The metal silicide material may be, for example, a silicide material of a metal selected from Co, Ni, Hf, Pt, W, and Ti, or a combination thereof. In some embodiments, the gate electrodes 130 may include a metal material, for example, tungsten (W). Also, although not shown separately, the gate electrodes 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN). ) or a combination thereof.

A common source line CSL may be disposed in a trench TH between a stack of adjacent gate electrodes 130 .

The gate pads 130P may correspond to regions in which the gate electrodes 130 horizontally extend from the cell region CELL to the pad region PAD. The gate pads 130P may extend to different lengths to form a step shape. The gate pads 130P may provide a contact region in which the lower gate pads 130P extend longer than the upper gate pads 130P. In the contact region, the gate pads 130P may be connected to the upper second wiring lines 190 by contact plugs 180 , whereby an electrical signal may be applied to the gate electrodes 130 . .

The gate pads 130P may include regions thinner than the gate electrodes 130 . The gate pads 130P may include regions extending from the gate electrodes 130 to a constant thickness and then decreasing in thickness. For example, the thickness of the gate pads 130P may be reduced in the contact region. Accordingly, in the entire contact region, the gate pads 130P may have a thickness from a first thickness T1 to a second thickness T2 smaller than the first thickness T1 . Accordingly, in the contact region, the gate pads 130P may have a step portion CP having a vertically decreasing thickness.

The difference between the first thickness T1 and the second thickness T2 may be in the range of about 5 Å to 100 Å, for example, in the range of about 10 Å to 50 Å, and is equal to 1 of the first thickness T1. % to 35%. In the present embodiment, the difference in thickness between the gate pads 130P and the gate electrodes 130 connected thereto, that is, the degree of thickness reduction in the gate pads 130P may be substantially the same as each other, but is limited thereto. it doesn't happen

The uppermost gate pad 137P may have a thickness smaller than that of the gate electrode 137 in the pad area PAD, and the length L1 extending to the thin thickness may be variously changed in some embodiments.

Interlayer insulating layers 120 may be arranged between the gate electrodes 130/gate pads 130P. Like the gate electrodes 130 , the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the top surface of the substrate 101 and may be arranged to extend in the x direction. In the pad area PAD, the interlayer insulating layers 120 may also extend to different lengths along the gate pads 130P. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

The channel holes CH may be disposed to be spaced apart from each other while forming rows and columns on the substrate 101 in the cell region CELL, and may be disposed to be shifted from each other in the x-direction. That is, the channel holes CH may be disposed to form a grid pattern or may be disposed in a zigzag shape in one direction. The channel holes CH may have inclined sides that become narrower as they get closer to the substrate 101 according to the aspect ratio. However, the arrangement of the channel holes CH may vary according to embodiments, and is not limited to the illustrated form.

The columnar channel region 140 may be disposed in the channel hole CH extending in a direction perpendicular to the upper surface of the substrate 101 . In the channel hole CH, the channel region 140 may be formed in an annular shape surrounding the first insulating layer 162 therein, but may be a cylinder without the first insulating layer 162 or a cylinder without the first insulating layer 162 according to an embodiment. It may have a column shape such as a prism. The channel region 140 may be connected to the substrate 101 at the bottom. The channel region 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material containing p-type or n-type impurities.

The dummy channel holes CHD may be disposed at ends of the gate pads 130P in the pad area PAD. However, the arrangement of the dummy channel holes CHD is not limited thereto, and may be variously arranged, for example, arranged on both sides of the contact plugs 180 in the x direction. The dummy channel holes CHD may have the same structure as the channel holes CH. However, a wiring structure such as the channel plug 175 may not be disposed on the dummy channel holes CHD.

The gate dielectric layer 150 may be disposed between the gate electrodes 130 and the channel region 140 in the channel hole CH. The gate dielectric layer 150 may extend vertically on the substrate 101 along the channel region 140 . The gate dielectric layer 150 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel region 140 . This will be described in more detail with reference to FIGS. 5A to 5C below.

Channel pads 160 may be disposed on the channel regions 140 . The channel pads 160 may be disposed to cover the upper surface of the first insulating layer 162 and be electrically connected to the channel region 140 . The channel pad 160 may include, for example, doped polycrystalline silicon.

Channel plugs 175 may pass through the second insulating layer 166 to be connected to the channel pads 160 . The channel pads 160 may be electrically connected to the upper first wiring lines 170 by the channel plugs 175 . The first wiring lines 170 may be bit lines BL1 to BLm (refer to FIG. 2 ).

The first wiring lines 170 may extend over the channel plugs 175 in a direction different from that of the gate electrodes 130 , for example, in a y-direction.

The channel plugs 175 and the first wiring lines 170 may include a conductive material, for example, a metal such as tungsten (W), aluminum (Al), or copper (Cu).

The contact plugs 180 may pass through the second insulating layer 166 and the pad insulating layer 129 to be connected to the gate pads 130P. As the heights of the gate pads 130P are different, the contact plugs 180 may have different lengths. The contact plugs 180 may be connected while partially recessing the gate pads 130P, but are not limited thereto. In some embodiments, the contact plugs 180 may have a shape in which the width decreases toward the bottom due to the high aspect ratio.

The second wiring lines 190 may extend above the contact plugs 180 in the same direction as the first wiring lines 170 , for example, in the y-direction. However, in some embodiments, the gate pads 136P and 137P connected to the gate electrodes 136 and 137 of the string select transistor SST are separate from the second wiring lines 190 extending in a different direction. It may be connected to a wiring line.

The contact plugs 180 and the second wiring lines 190 may include a conductive material, for example, a metal such as tungsten (W), aluminum (Al), or copper (Cu).

5A to 5C are cross-sectional views illustrating a gate dielectric layer according to example embodiments, and a region corresponding to region 'A' of FIG. 4 is shown.

Referring to FIG. 5A , the gate electrode 132 , the gate dielectric layer 150 and the channel region 140 of the memory cell strings are shown. The gate dielectric layer 150 may include a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156 sequentially stacked from the channel region 140 .

The tunneling layer 152 may tunnel charges into the charge storage layer 154 in an FN tunneling method. The tunneling layer 152 may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof.

The charge storage layer 154 may be a charge trap layer or a floating gate conductive layer. For example, the charge storage layer 154 may include a dielectric material, quantum dots, or nanocrystals. Here, the quantum dots or nanocrystals may be composed of fine particles of a conductor, for example, a metal or a semiconductor. In example embodiments, when the charge storage layer 154 is a charge trap layer, the charge storage layer 154 may be formed of silicon nitride.

The blocking layer 156 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. The high-k dielectric material is, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ) may be any one.

Referring to FIG. 5B , the gate electrode 132 , the gate dielectric layer 150a and the channel region 140 of the memory cell strings are shown. The gate dielectric layer 150a may have a structure in which a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156a are sequentially stacked from the channel region 140 . The relative thicknesses of the layers constituting the gate dielectric layer 150a are not limited to those shown in the drawings and may be variously changed.

In particular, in the gate dielectric layer 150a of this embodiment, unlike the embodiment of FIG. 5A , the tunneling layer 152 and the charge storage layer 154 are arranged to extend vertically along the channel region 140, but the blocking layer ( 156a may be disposed to surround the gate electrode layer 132 .

Referring to FIG. 5C , the gate electrode 132 , the gate dielectric layer 150b and the channel region 140 of the memory cell strings are shown. The gate dielectric layer 150b may have a structure in which a tunneling layer 152b, a charge storage layer 154b, and a blocking layer 156b are sequentially stacked from the channel region 140 .

In particular, in the gate dielectric layer 150b of this embodiment, unlike the embodiments of FIGS. 5A and 5B , the tunneling layer 152b, the charge storage layer 154b, and the blocking layer 156b all form the gate electrode layer 132 . It may be arranged to surround. In some embodiments, a portion of the blocking layer 156b may be disposed to extend vertically along the channel region 140 , and a portion may be disposed to surround the gate electrode layer 132 .

6A to 6C are cross-sectional views illustrating gate pads according to example embodiments, and a region corresponding to region 'B' of FIG. 4 is shown.

Referring to FIG. 6A , a gate pad 133Pa and a contact plug 180 are illustrated. The gate pad 133Pa includes a connection region PA that is connected to the gate electrode 133 and extends, and a contact region PB that is longer than the gate pad 134Pa and is connected to the contact plug 180 .

Unlike the embodiment of FIG. 4 , the thickness of the gate pad 133Pa of the present embodiment may gradually decrease in the contact region PB. Therefore, when the thickness in the connection area PA of the gate electrode 133 and the gate pad 133Pa is the first thickness T1 , in the contact area PB adjacent to the connection area PA, the first thickness ( The third thickness T3 may be smaller than T1 , and the fourth thickness T4 may be smaller than the third thickness T3 in a region close to the distal end of the contact area PB.

Referring to FIG. 6B , unlike the embodiment of FIG. 4 , the gate pad 133Pb has a curved portion CPa whose thickness is rapidly reduced in the contact area PB adjacent to the extension area PA. can have Due to the bent portion CPa, the gate pad 133Pb is reduced in thickness from the first thickness T1 to the second thickness T2 in the region where the bent portion CPa is formed, and the second thickness ( It may extend to T2) to have a flat top surface. However, the length L2 of the bent portion CPa may be variously changed in embodiments.

Referring to FIG. 6C , the gate pad 133Pc has a recessed bent portion CPb in the extension area PA adjacent to the contact area PB, unlike in the embodiments of FIGS. 4 and 6B . can The position, recessed shape, and depth of the bent portion CPb may be variously changed in the embodiments. Due to the bent portion CPb, the gate pad 133Pc decreases in thickness from the first thickness T1 to the second thickness T2 in the region where the bent portion CPb is formed, and the second thickness ( It may extend to T2) to have a flat top surface.

7 to 9 are schematic cross-sectional views of semiconductor devices according to example embodiments.

Referring to FIG. 7 , the semiconductor device 100a includes gate electrodes 130 , interlayer insulating layers 120 , channel holes CH, and gate pads horizontally extending from the gate electrodes 130 . 130Pd) and contact plugs 180 connected to the gate pads 130Pd.

The gate pads 130Pd may include regions extending from the gate electrodes 130 to a constant thickness and then decreasing in thickness. For example, the gate pads 130Pd may have a contact region extending longer than the gate pads 130Pd disposed thereon to be connected to the contact plugs 180 , and may have a reduced thickness in the contact region. have.

Unlike in the embodiment of FIG. 4 , the thickness reduction of the gate pads 130Pd may increase as the distance from the top surface of the substrate 101 increases. That is, the degree of reduction in thickness of the gate pads 130Pd disposed relatively above may be greater than the degree of reduction in thickness of the gate pads 130Pd disposed at the bottom. Accordingly, when the gate electrodes 130 have substantially the same thickness, the uppermost gate pad 137Pd has a fifth thickness T5 in the contact region, and the lowermost gate pad 131Pd has the same thickness. A sixth thickness T6 may be greater than the fifth thickness T5 in the contact region. The sixth thickness T6 may be equal to or smaller than the thickness of the gate electrode 131 connected to the gate pad 131Pd.

However, the present invention is not limited thereto, and in some embodiments, the degree of thickness reduction of the gate pads 130Pd decreases as the distance from the top surface of the substrate 101 increases, contrary to the thickness reduction tendency of the present embodiment. You may. That is, the degree of thickness reduction in the lower gate pads 130Pd may be greater than the thickness reduction in the upper gate pads 130Pd. The tendency of the thickness reduction between the gate pads 130Pd may be determined according to a formation order during a manufacturing process, and accordingly, may be proportional to or inversely proportional to the distance from the substrate 101 .

Referring to FIG. 8 , the semiconductor device 100b includes gate electrodes 130 , interlayer insulating layers 120 , channel holes CH, and gate pads horizontally extending from the gate electrodes 130 . 130Pe) and contact plugs 180 connected to the gate pads 130Pe.

The gate pads 130Pe may include regions extending from the gate electrodes 130 to a constant thickness and then decreasing in thickness. For example, the gate pads 130Pe may have a contact region extending longer than the gate pads 130Pe disposed thereon to be connected to the contact plugs 180 , and may have a reduced thickness in the contact region. have.

The gate pads 130Pe may be divided into first and second groups ST1 and ST2 arranged vertically. The first group ST1 may include lower gate pads 131Pe, 132Pe, and 133Pe, and the second group ST2 may include upper gate pads 134Pe, 135Pe, 136Pe, and 137Pe.

The gate pads 130Pe may have different degrees of thickness reduction in the first and second groups ST1 and ST2 . For example, the thickness reduction degree in the second group ST2 may be greater than the thickness reduction degree in the first group ST1 . Accordingly, when the gate electrodes 130 have substantially the same thickness, in the second group ST2 , they have a seventh thickness T7 in the contact region, and in the first group ST1 , they have a seventh thickness in the contact region. The eighth thickness T8 may be greater than the thickness T7 . In some embodiments, when the thicknesses of the gate electrodes 130 are different from each other, only the degree of thickness reduction in each of the first and second groups ST1 and ST2 may be the same.

However, in embodiments, the division of groups such as the first and second groups ST1 and ST2 may be variously changed. For example, the number of groups and the number of gate pads 130Pe included in one group may be variously changed. In addition, in some embodiments, contrary to the thickness reduction tendency of the present embodiment, the degree of thickness reduction may be small in the group disposed above. A difference in thickness reduction between the gate pads 130Pd according to these groups may be determined according to a formation order and method during a manufacturing process.

Referring to FIG. 9 , the semiconductor device 100c includes gate electrodes 130 , interlayer insulating layers 120 , channel holes CH, and gate pads horizontally extending from the gate electrodes 130 . 130P), contact plugs 180 connected to the gate pads 130P, and an etch stop layer 107 on the gate pads 130P.

The etch stop layer 107 may be disposed on step-shaped steps formed by the gate pads 130P. In particular, the etch stop layer 107 may be disposed on a region where the gate pads 130P are connected to the contact plugs 180 . Accordingly, the contact plugs 180 may pass through the etch stop layer 107 to be connected to the gate pads 130P.

The etch stop layer 107 may serve as an etch stop so that holes having different depths may be stably formed when the holes for forming the contact plugs 180 are formed. Accordingly, the etch stop layer 107 may be made of a material different from that of the pad insulating layer 129 and the gate pads 130P to have different etch selectivity. For example, when the pad insulating layer 129 is made of silicon oxide and the gate pads 130P are made of a metal material, the etch stop layer 107 may include silicon nitride or silicon carbide.

In some embodiments, the etch stop layer 107 may not be in direct contact with the gate pads 130P, but may be spaced apart from each other by a predetermined height and disposed in the pad insulating layer 129 . In this case, the etch stop layer 107 may be made of a conductive material such as polycrystalline silicon.

10A to 10K are main step-by-step views schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. 10A to 10K , a method of manufacturing the semiconductor device 100 of FIGS. 3 and 4 is described.

Referring to FIG. 10A , sacrificial layers 111-117: 110 and interlayer insulating layers 121-128: 120 may be alternately stacked on a substrate 101 . Through a subsequent process, the sacrificial layers 110 may be replaced with the gate electrode 130 .

First, the interlayer insulating layer 121 may be formed, and the sacrificial layers 110 and the interlayer insulating layers 120 may be alternately stacked on the substrate 101 as shown. The sacrificial layers 110 may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers 120 . That is, the sacrificial layers 110 may be formed of a material that can be etched while minimizing the etching of the interlayer insulating layers 120 during the process of etching the sacrificial layers 110 . The etch selectivity or etch selectivity may be quantitatively expressed through a ratio of the etch rate of the sacrificial layers 110 to the etch rate of the interlayer insulating layer 120 . For example, the interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the sacrificial layers 110 are interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide and silicon nitride. and other materials.

In some embodiments, the thicknesses of the interlayer insulating layers 120 may not all be the same. For example, the lowermost interlayer insulating layer 121 may be formed to be relatively thin, and the uppermost interlayer insulating layer 128 may be formed to be relatively thick. In addition, in some embodiments, the interlayer insulating layers 122 and 126 disposed between the ground select transistor GST and the string select transistor SST of FIG. 2 and the memory cells MC1 to MCn are the memory cells ( It may be formed to be relatively thicker than the interlayer insulating layers 123 to 125 disposed between MC1 to MCn. The thicknesses of the interlayer insulating layers 120 and the sacrificial layers 110 may be variously modified from those shown, and the number of layers constituting the interlayer insulating layers 120 and the sacrificial layers 110 may also vary. can be changed to

Referring to FIG. 10B , a hard mask layer HM and a first photo mask layer PM1 are formed on the stacked interlayer insulating layers 120 and sacrificial layers 110 , and the interlayer insulating layers are formed using the same. Part of 120 and the sacrificial layers 110 may be removed.

In order to form the step-shaped gate pads 130P in the pad area PAD as shown in FIG. 4 , a process of partially removing the sacrificial layers 110 may be started. First, the hard mask layer HM may be formed on the interlayer insulating layers 120 and the sacrificial layers 110 in the cell region CELL to protect the cell region CELL. The hard mask layer HM may include a material different from that of the interlayer insulating layer 120 , and may be formed of multiple layers.

Next, a first photomask layer PM1 for cutting the uppermost seventh sacrificial layer 117 may be formed. The first photomask layer PM1 may be formed to match the desired length of the seventh sacrificial layer 117 , that is, the desired length of the gate pad 137P (refer to FIG. 4 ). A portion of the interlayer insulating layers 120 and the sacrificial layers 110 exposed by the first photomask layer PM1 may be removed using dry etching or wet etching.

Referring to FIG. 10C , after removing the first photomask layer PM1 , a second photomask layer PM2 is formed, and parts of the interlayer insulating layers 120 and the sacrificial layers 110 are removed using the second photomask layer PM2 . can do.

First, the first photomask layer PM1 may be removed by an ashing process and a strip process. Some of the interlayer insulating layers 127 and 128 exposed during the stripping process may be removed together. For example, when the interlayer insulating layers 120 are made of silicon oxide and hydrofluoric acid (HF) is used during the stripping process, the thickness of the uppermost interlayer insulating layer 128 is the ninth thickness T9 ( FIG. 10B ). reference) may be reduced to a thinner tenth thickness T10.

Next, a second photomask layer PM2 for cutting the sixth sacrificial layer 116 may be formed. A portion of the interlayer insulating layers 120 and the sacrificial layers 110 exposed by the second photomask layer PM2 may be removed using dry etching or wet etching.

Referring to FIG. 10D , all of the sacrificial layers 110 may be cut to extend to different lengths.

As described above with reference to FIGS. 10B and 10C , the photomask layers PM1 and PM2 are formed, the interlayer insulating layers 120 and the sacrificial layers 110 are partially removed, and the photomask layers PM1 are formed. , PM2) by repeating the removal process, all of the sacrificial layers 110 may be cut to form a step shape.

During the repeated process, as described above with reference to FIG. 10C , the interlayer mask layers 120 may be partially removed when the photo mask layers PM1 and PM2 are removed. Accordingly, the thickness of the interlayer insulating layers 120 may be reduced in the exposed region PC, and the upper interlayer insulating layers 120 that are relatively exposed to the strip process may have a thinner thickness than the lower ones. . However, such a reduction in the thickness of the interlayer insulating layers 120 may appear in various embodiments in various embodiments. may be In this case, the lower sacrificial layers 110 may be exposed.

In the present embodiment, a method of cutting the sacrificial layers 110 in the order from top to bottom has been described, but the present invention is not limited thereto, and conversely, it is also possible to cut the sacrificial layers 110 in the order from bottom to top. In this case, in the exposed region PC, the lower interlayer insulating layers 120 may have a thinner thickness than the upper ones.

Referring to FIG. 10E , first and second pad insulating layers 129A and 129B may be formed.

The second pad insulating layer 129B may be formed of an oxide-based material, for example, a high density plasma (HDP) layer, but is not limited thereto. In the exposed region PC, the sacrificial layers 110 disposed under the relatively thin interlayer insulating layers 120 may be partially oxidized by an oxygen source applied when the second pad insulating layer 129B is formed. Accordingly, the first pad insulating layers 129A may be formed. That is, in the exposed region PC, the thickness of the interlayer insulating layers 120 disposed on the sacrificial layers 110 is reduced, and thus the sacrificial layers 110 are not protected, so the sacrificial layers 110 are not protected. ) may be at least partially oxidized to a predetermined depth from the upper surface.

In FIG. 10E , the first pad insulating layers 129A include an oxide layer formed by oxidizing the sacrificial layers 110 , and interlayer insulating layers remaining on the sacrificial layers 110 in the exposed region PC. (120) is shown as a combined layer. However, in some embodiments, the two layers may be distinguishable from each other.

When the thickness of the interlayer insulating layers 120 remaining in the exposed region PC is so thin that it is difficult to prevent oxidation, as in the present embodiment, the thickness of the oxidized sacrificial layers 110 is equal to the thickness of the upper interlayer insulating layer. Regardless of the remaining thickness of the elements 120 , they may be substantially the same as or similar to each other. However, in some embodiments as shown in FIG. 7 , the thickness of the oxide layer formed by oxidizing the sacrificial layers 110 may vary according to the thickness of the remaining interlayer insulating layers 120 . For example, when the thickness of the interlayer insulating layers 120 remaining in the lower portion is relatively thick, the oxide layer may be formed to be relatively thick in the upper portion. Embodiments such as those described above with reference to FIGS. 6A to 6C may also be determined according to the shape of the oxide layer in this step.

In some embodiments, a stack of the sacrificial layers 110 and the interlayer insulating layers 120 is not used, and the interlayer insulating layers 120 and the gate electrodes 130/gate pads 130P ( 4) may be stacked from the beginning to manufacture a semiconductor device. In this case, instead of cutting the sacrificial layers 110 , a cutting process of the gate pads 130P may be performed.

Even in this case, when the second pad insulating layer 129B is formed in this step, the gate pads 130P are partially oxidized to form an oxide layer in the exposed region PC, so that it has a structure as shown in FIG. 4 . can be formed.

Referring to FIG. 10F , by forming the third pad insulating layer 129C, the pad insulating layer 129 covering the pad area PAD may be formed.

First, after a portion of the third pad insulating layer 129C is formed, a planarization process may be performed to expose the hard mask layer HM. The third pad insulating layer 129C may be, for example, a Tetra-Ethyl-Ortho-Silicate (TEOS) layer.

Next, the third pad insulating layer 129C may be formed by selectively removing the hard mask layer HM and then depositing an insulating material thereon. However, the formation method and process sequence of the third pad insulating layer 129C may vary. As a result, the pad insulating layer 129 including the first to third pad insulating layers 129A, 129B, and 129C may be finally formed. The first to third pad insulating layers 129A, 129B, and 129C constituting the pad insulating layer 129 may be made of the same material, and thus, their boundaries may not be distinguished from each other. Therefore, it is shown as one layer below.

Referring to FIG. 10G , channel holes CH and dummy channel holes CHD (refer to FIG. 3 ) may be formed.

First, the channel holes CH may be formed by anisotropically etching the sacrificial layers 110 and the interlayer insulating layers 120 . Since the stacked structure including different types of layers is etched, sidewalls of the channel holes CH may not be perpendicular to the upper surface of the substrate 101 . For example, in some embodiments, the width of the channel holes CH may decrease as it approaches the upper surface of the substrate 101 . In some embodiments, a portion of the substrate 101 may be recessed by the channel holes CH.

Next, the gate dielectric layer 150 , the channel region 140 , the first insulating layer 162 , and the channel pads 160 may be formed in the channel holes CH. The dummy channel holes CHD of the pad area PAD may also have the same structure as the channel holes CH.

The gate dielectric layer 150 may be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this step, all or part of the gate dielectric layer 150 may be formed, and a portion extending perpendicularly to the substrate 101 along the channel hole CH may be formed in this step. The channel region 140 may be formed on the gate dielectric layer 150 in the channel holes CH.

The first insulating layer 162 is formed to fill the channel holes CH, and may be an insulating material. However, in some embodiments, the space between the channel regions 140 may be filled with a conductive material other than the first insulating layer 162 . The channel pad 160 may be made of a conductive material. The channel pad 160 may be made of, for example, polycrystalline silicon.

Referring to FIG. 10H , a trench TH (refer to FIG. 3 ) separating the stacked structure of the sacrificial layers 110 and the interlayer insulating layers 120 in a direction not shown is formed, and the trench TH is passed through the trench TH. The exposed sacrificial layers 110 may be removed.

The sacrificial layers 110 may be selectively removed with respect to the interlayer insulating layers 120 using, for example, wet etching to form the tunnel portion TP. Before removing the sacrificial layers 110 , a second insulating layer 166 may be further formed on the channel pads 160 to protect the channel holes CH.

In this step, a portion of the sacrificial layers 110 that are oxidized and form a part of the first pad insulating layer 129A (refer to FIG. 10F ) may not be removed. Accordingly, the tunnel part TP may have a shape in which a width decreases at the distal end.

Referring to FIG. 10I , the gate electrodes 130 and the gate pads 130P may be formed by filling a conductive material in the region from which the sacrificial layers 110 are removed.

The gate electrodes 130 and the gate pads 130P may include a metal, polycrystalline silicon, or a metal silicide material. The metal silicide material may be, for example, a silicide material of a metal selected from Co, Ni, Hf, Pt, W, and Ti, or a combination thereof. When the gate electrodes 130 and the gate pads 130P are made of a metal silicide material, silicon (Si) is buried in the tunnel portions TP, and then a separate metal layer is formed to perform a silicidation process. 130 and gate pads 130P may be formed.

Although not shown in the drawing, the material constituting the gate electrodes 130 formed in the trench TH (refer to FIG. 3 ) after forming the gate electrodes 130 and the gate pads 130P may be removed through an additional process. can Next, a common source line CSL (refer to FIG. 2 ) may be formed in the trench TH.

Referring to FIG. 10J , contact holes H may be formed by removing a portion of the pad insulating layer 129 .

The contact holes H may be formed by forming a separate mask pattern that opens a region in which the contact plugs 180 (refer to FIG. 4 ) are to be formed, and then using the formed mask pattern. The contact holes H may be formed to expose the gate pads 130P, or the gate pads 130P may be formed to be recessed to a predetermined depth.

Referring to FIG. 10K , contact plugs 180 may be formed.

First, the contact plugs 180 may be formed by filling the contact holes H with a conductive material.

Next, referring to FIG. 4 together, second wiring lines 190 may be formed on the contact plugs 180 . In the cell region CELL, after the channel plugs 175 are formed on the channel pads 160 , the first wiring lines 170 may be formed thereon. In embodiments, the arrangement of the first and second wiring lines 170 and 180 is not limited to the illustrated one, and for example, may be arranged at different heights.

11A to 11D are main step-by-step views schematically illustrating a method of manufacturing a semiconductor device according to example embodiments. 11A to 11D , a method of manufacturing the semiconductor device 100b of FIG. 8 is described. Hereinafter, descriptions overlapping with those described above with reference to FIGS. 10A to 10K will be omitted.

First, as described above with reference to FIG. 10A , a stacked structure of the sacrificial layers 110 and the interlayer insulating layer 120 may be formed.

Next, referring to FIG. 11A , a hard mask layer HM and a first photo mask layer PM1 ′ are formed on the stacked interlayer insulating layers 120 and sacrificial layers 110 , and using the A portion of the interlayer insulating layers 120 and the sacrificial layers 110 may be removed.

First, a process of cutting the sacrificial layers 110 may be performed at positions corresponding to the gate pads 130Pe of the second group ST2 of FIG. 8 . Accordingly, the first photomask layer PM1 ′ may be formed to match the length of the lowermost gate pad 134Pe (refer to FIG. 8 ) among the gate pads 130Pe of the second group ST2 . The region exposed by the first photomask layer PM1 ′ may be removed using dry etching or wet etching.

Referring to FIG. 11B , the trimming mask layer PM1a may be formed by trimming the first photomask layer PM1 ′.

The trimming process is a process of reducing the size of the first photomask layer PM1 ′ by using a dry etching method or a wet etching method. Accordingly, the first trimming mask layer PM1a may be formed to cover the reduced area such that one end corresponds to the length of the gate pad 135Pe (refer to FIG. 8 ). The height of the first photomask layer PM1 ′ may also be reduced by the trimming process.

Referring to FIG. 11C , all of the fourth to seventh sacrificial layers 114 to 117 replaced with the gate pads 130Pe of the second group ST2 of FIG. 8 may be cut.

After repeating the trimming process described above with reference to FIG. 11B to cut the fourth to seventh sacrificial layers 114 to 117 to have different lengths, the trimming mask layer PM1a may be removed.

When the trimming mask layer PM1a is removed, some of the exposed interlayer mask layers 120 may be removed together. Accordingly, the thickness of the interlayer insulating layers 120 exposed on the fourth to seventh sacrificial layers 114 to 117 may be reduced to the same extent.

Referring to FIG. 11D , in order to cut the sacrificial layers 110 at positions corresponding to the gate pads 130Pe of the first group ST1 of FIG. 8 , a second photomask layer PM2' is formed. can

The second photomask layer PM2 ′ may be formed to match the length of the lowermost gate pad 131Pe (refer to FIG. 8 ) among the gate pads 130Pe of the first group ST1 . The interlayer insulating layers 120 and the sacrificial layers 110 exposed by the twenty-first photo mask layer PM2 ′ may be removed using dry etching or wet etching.

Next, all of the sacrificial layers 110 may be cut by repeating the trimming process and the etching process as described above with reference to FIGS. 11B and 11C . As such, it is possible to reduce the number of processes for forming and removing the photomask layer by using the trimming process. However, since a portion of the exposed interlayer insulating layer 120 is removed when the photomask layer is removed, the interlayer insulating layers 120 on the sacrificial layers 110 cut into one photomask layer have the same thickness. The thickness may be reduced by as much. Accordingly, as shown in FIG. 8 , the gate pads 130Pe formed in the corresponding region may be formed to have different thicknesses in the contact region in units of the groups ST1 and ST2.

Next, the process described above with reference to FIGS. 10E to 10K may be performed to finally manufacture the semiconductor device 100b of FIG. 8 .

12 is a schematic perspective view of a semiconductor device according to example embodiments.

Referring to FIG. 12 , the semiconductor device 200 may include a cell region CELL, a pad region PAD, and a peripheral circuit region PERI.

The peripheral circuit region PERI may correspond to a region in which the driving circuit 30 of the memory cell array 20 of FIG. 1 is disposed. The peripheral circuit area PERI may be disposed below the cell area CELL and the pad area PAD. In some embodiments, the peripheral circuit area PERI may be disposed on top of or at least one side of the cell area CELL and the pad area PAD.

The cell region CELL and the pad region PAD include the gate electrodes 130 , the interlayer insulating layers 120 , the channel holes CH, and gate pads extending horizontally from the gate electrodes 130 . 130P, and contact plugs 180 connected to the gate pads 130P.

In the present embodiment, the cell region CELL and the pad region PAD have the same structure as in the embodiment of FIG. 4 , but are not limited thereto. The cell region CELL and the pad region PAD may include, for example, semiconductor devices according to various embodiments of the present disclosure as described above with reference to FIGS. 6A to 9 .

The peripheral circuit region PERI includes a base substrate 201 , circuit elements 230 disposed on the base substrate 201 , first and second contact plugs 250 and 275 , and first and second wirings. It may include lines 260 and 270 .

The base substrate 201 may have a top surface extending in the x-direction and the y-direction. The base substrate 201 may have a device isolation layer 210 formed thereon to define an active region. A doped region 205 including impurities may be disposed in a portion of the active region. The base substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

The circuit element 230 may include a horizontal transistor. Each circuit element 230 may include a circuit gate insulating layer 232 , a spacer layer 234 , and a circuit gate electrode 235 . A doped region 205 may be disposed in the base substrate 201 on both sides of the circuit gate electrode 235 to serve as a source region or a drain region of the circuit device 230 .

The peripheral region insulating layer 240 may be disposed on the circuit device 230 on the base substrate 201 .

The first contact plugs 250 may pass through the peripheral region insulating layer 240 to be connected to the doped region 205 or the circuit gate electrode 235 . The second contact plugs 275 may be disposed between the first and second wiring lines 260 and 270 . An electrical signal may be applied to the circuit device 230 through the first and second contact plugs 250 and 275 and the first and second wiring lines 260 and 270 .

The semiconductor device 200 may further include connection wiring structures 280 and 290 connecting the pad area PAD and the peripheral circuit area PERI to each other.

The connection wiring structures 280 and 290 are, for example, first and second wirings connected to the gate electrodes 130 and the channel region 140 of the cell region CELL and extending to the pad region PAD. The lines 170 and 190 may be disposed to connect to the circuit device 230 of the peripheral circuit region PERI.

After the peripheral circuit region PERI is first manufactured, the substrate 101 of the cell region CELL and the pad region PAD may be formed thereon to manufacture the cell region CELL and the pad region PAD. . The substrate 101 may be formed smaller than the base substrate 201 , but is not limited thereto. The substrate 101 may be formed of polycrystalline silicon or single-crystallized after being formed of amorphous silicon.

13 is a block diagram illustrating a storage device including a semiconductor device according to example embodiments.

Referring to FIG. 13 , the storage device 1000 according to the present embodiment may include a controller 1010 communicating with a host HOST and memories 1020-1, 1020-2, and 1020-3 for storing data. can Each of the memories 1020-1, 1020-2, and 1020-3 may include a semiconductor device according to various embodiments of the present disclosure as described above with reference to FIGS. 3 to 9 .

The host (HOST) communicating with the controller 1010 may be various electronic devices to which the storage device 1000 is mounted, and may be, for example, a smart phone, a digital camera, a desktop, a laptop, or a media player. The controller 1010 receives a data write or read request transmitted from the host and stores data in the memories 1020-1, 1020-2, and 1020-3, or the memory 1020-1, 1020-2, A command (CMD) for fetching data from 1020-3) may be generated.

As shown in FIG. 13 , one or more memories 1020-1, 1020-2, and 1020-3 in the storage device 1000 may be connected to the controller 1010 in parallel. By connecting the plurality of memories 1020-1, 1020-2, and 1020-3 to the controller 1010 in parallel, the storage device 1000 having a large capacity, such as a solid state drive (SSD), may be implemented.

14 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments.

Referring to FIG. 14 , the electronic device 2000 according to the present embodiment may include a communication unit 2010 , an input unit 2020 , an output unit 2030 , a memory 2040 , and a processor 2050 .

The communication unit 2010 may include a wired/wireless communication module, and may include a wireless Internet module, a short-range communication module, a GPS module, a mobile communication module, and the like. The wired/wireless communication module included in the communication unit 2010 may be connected to an external communication network according to various communication standards to transmit/receive data.

The input unit 2020 is a module provided for a user to control the operation of the electronic device 2000 , and may include a mechanical switch, a touch screen, a voice recognition module, and the like. In addition, the input unit 2020 may include a mouse or a finger mouse device that operates in a track ball or laser pointer method, and may further include various sensor modules through which a user can input data.

The output unit 2030 outputs information processed by the electronic device 2000 in the form of audio or video, and the memory 2040 may store a program or data for processing and controlling the processor 2050 or data. . The processor 2050 may store or retrieve data by transmitting a command to the memory 2040 according to a required operation.

The memory 2040 may be embedded in the electronic device 2000 or may communicate with the processor 2050 through a separate interface. When communicating with the processor 2050 through a separate interface, the processor 2050 may store or retrieve data from the memory 2040 through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB, etc. .

The processor 2050 controls the operation of each unit included in the electronic device 2000 . The processor 2050 may perform control and processing related to voice calls, video calls, data communication, and the like, or may perform control and processing for multimedia reproduction and management. In addition, the processor 2050 may process an input transmitted from the user through the input unit 2020 and output the result through the output unit 2030 . Also, as described above, the processor 2050 may store or retrieve data necessary for controlling the operation of the electronic device 2000 in the memory 2040 . At least one of the processor 2050 and the memory 2040 may include a semiconductor device according to various embodiments of the present disclosure as described above with reference to FIGS. 3 to 9 .

15 is a schematic diagram illustrating a system including a semiconductor device according to example embodiments.

Referring to FIG. 15 , a system 3000 may include a controller 3100 , an input/output device 3200 , a memory 3300 , and an interface 3400 . The system 3000 may be a mobile system or a system for transmitting or receiving information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. can

The controller 3100 may serve to execute a program and control the system 3000 . The controller 3100 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device.

The input/output device 3200 may be used to input or output data of the system 3000 . The system 3000 may be connected to an external device, for example, a personal computer or a network, using the input/output device 3200 to exchange data with the external device. The input/output device 3200 may be, for example, a keypad, a keyboard, or a display.

The memory 3300 may store codes and/or data for the operation of the controller 3100 , and/or store data processed by the controller 3100 . The memory 3300 may include the semiconductor device according to any one of the embodiments of the present invention.

The interface 3400 may be a data transmission path between the system 3000 and another external device. The controller 3100 , the input/output device 3200 , the memory 3300 , and the interface 3400 may communicate with each other through the bus 3500 .

At least one of the controller 3100 and the memory 3300 may include a semiconductor device according to various embodiments of the present disclosure as described above with reference to FIGS. 3 to 9 .

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various types of substitutions, modifications and changes will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and this also falls within the scope of the present invention. something to do.

CH: channel hole 100: semiconductor device
101: substrate 107: etch stop layer
110: sacrificial layer 120: interlayer insulating layer
129: pad insulating layer 130: gate electrode
130P: gate pad 140: channel region
150: gate dielectric layer 160: channel pad
162: first insulating layer 166: second insulating layer
170: first wiring line 175: channel plug
180: contact plug 190: second wiring line

Claims (20)

gate electrodes vertically stacked on the substrate;
channel holes extending perpendicular to the substrate through the gate electrodes and having a channel region;
gate pads extending from the gate electrodes to different lengths; and
and contact plugs connected to the gate pads;
the gate pads include a contact region in which the lower gate pad extends longer than the upper gate pad and is connected to the contact plugs;
At least some of the gate pads have a thickness smaller than a thickness of the connected gate electrode in the entire contact region.
delete delete The method of claim 1,
The gate pads have a thickness that gradually decreases in the contact region.
The method of claim 1,
The gate pads have a bent portion whose thickness is rapidly reduced in the vicinity of the contact region, and extend horizontally in a region other than the bent portion.
The method of claim 1,
A difference in thickness between each of the gate pads and the connected gate electrode is different in the gate pads.
7. The method of claim 6,
In the gate pads, the difference in thickness increases from the top surface of the substrate to the top.
7. The method of claim 6,
In the gate pads, the difference in thickness increases in a group unit including two or more gate pads while moving upward from the top surface of the substrate.
The method of claim 1,
and an etch stop layer disposed on the gate pads, wherein the contact plugs pass through the etch stop layer.
10. The method of claim 9,
The etch stop layer is disposed to contact the gate pads.
gate electrodes vertically stacked on the substrate;
gate pads extending from the gate electrodes to different lengths and having contact regions; and
and contact plugs connected to the gate pads in the contact region;
The contact region includes first regions in direct contact with the contact plugs and second regions not in direct contact with the contact plugs;
A thickness of at least some of the gate pads is reduced in the second regions of the contact region.
12. The method of claim 11,
The contact region may include a region in which the lower gate pad extends longer than the upper gate pad.
12. The method of claim 11,
The gate pads have a stepped portion or a bent portion to reduce a thickness in the contact region.
12. The method of claim 11,
A difference in thickness between the gate electrode and the gate pad connected to each other is in the range of 5 Å to 100 Å.
12. The method of claim 11,
A degree to which the thickness of the gate pads is reduced is proportional to or inversely proportional to a distance from the substrate.
alternately stacking sacrificial layers and interlayer insulating layers on a substrate;
forming a mask layer on the stacked sacrificial layers and interlayer insulating layers;
removing a portion of the sacrificial layers and the interlayer insulating layers using the mask layer to form pad regions extending to different lengths;
forming a pad insulating layer made of an oxide-based material on the pad region;
removing the sacrificial layers; and
forming gate electrodes by burying a conductive material in the region from which the sacrificial layers are removed;
In the forming of the pad insulating layer, at least a portion of the sacrificial layers constituting the pad region is oxidized to form an oxide layer.
17. The method of claim 16,
A method of manufacturing a semiconductor device in which the sacrificial layers are partially oxidized from an upper surface by a source material for forming the pad insulating layer.
17. The method of claim 16,
In the removing of the sacrificial layers, the oxide layer is not removed and remains therein.
19. The method of claim 18,
wherein the gate electrodes have a reduced thickness under the oxide layer.
17. The method of claim 16,
The thickness of the oxide layer increases as the distance from the upper surface of the substrate increases.

Images