JP2012074731A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a macro-cell structure that achieves reduction in cell area without degradation in performance characteristics.SOLUTION: An N-well region 2 is formed in the center of a P-well region 1. N-active regions 4a and 4b are formed above and below the N-well region 2 in a plan view. In the P-well region 1, P-well contact regions 5a and 5b are formed above and below the N-active region 4a in a plan view so as to extend in a transverse direction. A P-active region 3 is formed in the center of the N-well region 2, and an N-well contact region 6 is formed at the left side of the P-active region 3 so as to extend vertically. A well contact portion 14c, which is a part of a metal wiring layer 14 for VDD crossing across the center of the P-active region 3, is formed also above the N-well contact region 6. The well contact portion 14c and the N-well contact region 6 are electrically connected to each other via a plurality of contact holes 21.

Description

  The present invention relates to a semiconductor integrated circuit having a macro cell structure.

  In a semiconductor integrated circuit (hereinafter sometimes referred to as “LSI”) having logic elements called macrocells whose height (cell formation length in a predetermined direction) is uniform, macrocells are arranged in a specific region, Are connected by wiring to form a desired circuit.

  FIG. 17 is a plan view showing a 16-times power (× 16) NAND gate as an example of a conventional single-height cell structure. In this specification, the positional relationship in the plan view is such that the vertical direction in the figure is the vertical direction (first direction), the horizontal direction in the figure is the horizontal direction (second direction), and is mainly upward (plan view). , Down, left and right.

  As shown in FIG. 17, a rectangular N-well region 52 and an N-active region 54 are selectively formed in the P-well region 51 so as to extend in the lateral direction. An active region 53 extends selectively in the lateral direction. In the N well region 52, an N well contact region 56 is formed extending in the lateral direction above the P active region 53 in plan view (on the opposite side to the N active region 54 in the vertical direction with respect to the P active region 53). In the N well region 52, a P well contact region 55 is formed extending laterally below the N active region 54 in plan view (on the opposite side to the P active region 53 in the vertical direction with respect to the N active region 54). The

  Thirty-two gate polysilicon layers 59 are formed side by side at predetermined intervals in the horizontal direction by cutting the P active region 53 and the N active region 54 vertically. Each gate polysilicon layer 59 on the P active region 53 and the N active region 54 functions as a gate electrode of the MOS transistor.

  A VDD metal wiring layer 64 is formed on the N well contact region 56, and the VDD metal wiring layer 64 and the N well contact region 56 are electrically connected through a plurality of contact holes 71. Further, the metal wiring layer 64 for VDD is the (2i) th and (2i + 1) th from the left on the P active region 53 on the left side of the leftmost gate polysilicon layer 59 among the 32 gate polysilicon layers 59. (I = 1 to 15) formed on the P active region 53 between the gate polysilicon layers 59 and 59 and on the right P active region 53 of the rightmost gate polysilicon layer 59, respectively. 71 is electrically connected to the P active region 53 (corresponding to the source region of the PMOS transistor) via 71.

  A ring-shaped output metal wiring layer 63 is formed across the 32 gate polysilicon layers 59 in the P active region 53 and across the 32 gate polysilicon layers 59 in the N active region 54.

  Further, the output metal wiring layer 63 includes the (2i-1) th and (2i) th (i = 1 to 16) gate polysilicon layers 59, 59 from the left of the 32 gate polysilicon layers 59. The P active region 53 is formed on the P active region 53 and is electrically connected to the P active region 53 (corresponding to the drain region of the PMOS transistor) through the contact hole 71.

  A second input metal wiring layer 62 is formed across the 32 gate polysilicon layers 59. Further, the second input metal wiring layer 62 includes (4i) th and (4i + 1) th (i = 1 to 7) from the left on the leftmost gate polysilicon layer 59 among the 32 gate polysilicon layers 59. ) On the gate polysilicon layers 59, 59 and the rightmost gate polysilicon layer 59, respectively, and the corresponding gate polysilicon layers 59 (second input receiving the second input) via the contact holes 71 are formed. Electrically connected to the gate electrodes of the PMOS transistor and the second NMOS transistor).

  A first input metal wiring layer 61 is formed across 28 gate polysilicon layers 59 except for the left and right two (total of four). Further, the first input metal wiring layer 61 is formed on the (4i + 2) th and (4i + 3) th (i = 0 to 7) gate polysilicon layers 59 and 59 from the left, respectively. Are electrically connected to the corresponding gate polysilicon layer 59 (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input).

  The output metal wiring layer 63 further includes an N between the (4i + 2) th and (4i + 3) th (i = 0 to 7) gate polysilicon layers 59, 59 of the 32 gate polysilicon layers 59 from the left. It is formed extending over the active region 54 and is electrically connected to the N active region 54 (corresponding to the drain region of the NMOS transistor) through the contact hole 71.

  A GND metal wiring layer 65 is formed on the P well contact region 55, and the GND metal wiring layer 65 and the P well contact region 55 are electrically connected through a plurality of contact holes 71. Further, the GND metal wiring layer 65 includes the (4i) th and (4i + 1) th from the left on the N active region 54 on the left side of the leftmost gate polysilicon layer 59 among the 32 gate polysilicon layers 59. (I = 1-7) formed on the N active region 54 between the gate polysilicon layers 59 and 59 and on the N active region 54 on the right side of the rightmost gate polysilicon layer 59. 71 is electrically connected to the N active region 54 (corresponding to the source region of the NMOS transistor) via 71.

  The macro cell M11 having such a configuration includes a first PMOS transistor and a first NMOS transistor each receiving a first input at the gate electrode, a second PMOS transistor and a second PMOS transistor each receiving a second input at the gate electrode. A two-input NAND gate serving as an NMOS transistor is constituted by 32 units of basic transistors (a MOS transistor constituted by one gate polysilicon layer 59 is defined as one unit of basic transistor). The macro cell M11 has a power supply wiring (VDD metal wiring layer 64) above the cell in plan view and a GND wiring (GND metal wiring layer 65) below, and an active region for forming transistors (P active region 53,. N active region 54) is arranged, and a vertical height is defined by the distance between the N well contact region 56 and the P well contact region 55 (second distance). The single-height cell structure described above is disclosed in Patent Document 1, for example.

JP-A-6-53318

  However, in the macro cell having the single-height cell structure described above, a 16-fold power NAND gate (comprising 32 basic transistors) or a flip-flop which is a relatively complicated logic circuit, like the macro cell M11 shown in FIG. If these cells are used for automatic placement and routing at the time of LSI construction, these cells have a large cell size in the horizontal direction, so that the degree of freedom in design is reduced, and the pro-plan for the entire LSI becomes difficult. As a result, the layout quality is degraded, which causes the operating characteristics such as the operating frequency of the created LSI to deteriorate.

  The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor integrated circuit having a macro cell structure in which the cell area is reduced without deteriorating the operation characteristics.

  According to a first aspect of the present invention, there is provided the semiconductor integrated circuit according to the first aspect of the present invention, wherein the first active region is formed in the upper layer portion of the semiconductor substrate and is rectangular in plan view and defined by the first and second directions. In the first active region, a first conductivity type basic transistor having a predetermined operating characteristic defined by a first length in the first direction is provided along the second direction. A plurality of second conductivity types are formed on the semiconductor substrate and disposed on one side and the other side in the first direction with respect to the first active region, respectively. The active region and a second layer formed in the upper layer portion of the semiconductor substrate in the vicinity of the first active region on a predetermined side in the second direction and extending in the first direction. A conductive type substrate potential setting region, and the substrate The substrate potential of the plurality of elementary transistor is set by a potential applied to position setting area.

  According to a first aspect of the present invention, the second and third active regions are arranged in the first direction with respect to the first active region, thereby increasing the cell area in the second direction. Can be suppressed and design freedom can be increased.

  Further, in the semiconductor integrated circuit according to the first aspect, since the substrate potential setting region is disposed in the vicinity of the predetermined side in the second direction with respect to the first active region, the semiconductor integrated circuit is defined by the first length in the first direction. The substrate potential setting region has no influence on the predetermined operating characteristics of the basic transistor.

  As a result, since the substrate potential setting region does not affect the predetermined operation characteristics, the predetermined operation characteristics of the first reference transistor in one unit can be improved, so that the cell characteristics are not degraded. There is an effect that the use efficiency of the first active region can be increased as compared with the conventional one while reducing the area.

It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 1 of this invention. It is explanatory drawing which shows typically the irregular AA cross-section of FIG. It is explanatory drawing which shows typically the irregular BB cross-section of FIG. 3 is a circuit diagram showing a NAND gate realized by the macro cell of Embodiment 1. FIG. FIG. 5 is a circuit diagram showing a transistor configuration for realizing the NAND gate of FIG. 4. It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 2 of this invention. It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 3 of this invention. It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 4 of this invention. It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 5 of this invention. It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 6 of this invention. FIG. 10 is a circuit diagram showing an AND gate realized by a macro cell according to a sixth embodiment. It is a circuit diagram which shows the transistor structure which implement | achieves the inverter of FIG. It is a top view which shows the cell structure of the macro cell of the double height cell structure which is Embodiment 7 of this invention. It is a top view which shows the internal structure of the semiconductor integrated circuit which is Embodiment 8 of this invention. It is a top view which shows the cell structure of the macro cell (the 1) of the double height cell structure used as a premise technique. It is a top view which shows the cell structure of the macro cell (the 2) of the double height cell structure used as a premise technique. It is a top view which shows the structure of the macro cell of the conventional single height cell structure.

<Prerequisite technology>
(Double height cell structure (1))
In order to solve the problems of the single height cell and to suppress the deterioration of the operation characteristics of the LSI accompanying the increase in the cell area in the lateral direction, the following macro cell structure of the double height cell configuration is conceivable. The double height cell configuration is a macro cell configured with a height twice as high as the distance (second distance) between the power supply VDD wiring and the GND wiring of the single height cell configuration as shown in FIG. Means structure.

  FIG. 15 is a plan view showing a cell structure of a macro cell M12 having a double-height cell structure, which is a prerequisite technology of the present invention. The macro cell M12 has a two-input NAND gate electrically equivalent to the macro cell M11, and a 16-unit basic transistor (a MOS composed of one gate polysilicon layer 59a, 59b in each of the upper and lower sides of the GND metal wiring layer 65 in plan view). The transistor is a basic transistor of one unit.

  As shown in FIG. 15, a rectangular N-well region 52 is formed extending in the lateral direction at the center of the P-well region 51, and a rectangular N-active region 54 a is formed above the N-well region 52 in plan view. A rectangular N active region 54b is selectively formed by extending in the lateral direction below. In the P well region 51, a P well contact region 55a extends selectively in the lateral direction above the N active region 54a in plan view, and the P well contact region 55b extends in the lateral direction below the N active region 54b in plan view. It extends and is selectively formed.

  In the N well region 52, rectangular P active regions 53a and 53b are selectively formed extending in the lateral direction above and below the plan view, respectively, and an N well contact region 56 is formed between the P active regions 53a and 53b. Is formed extending in the lateral direction.

  Sixteen gate polysilicon layers 59a are formed side by side at predetermined intervals in the vertical direction on the P active region 53a and the N active region 54a, and the gates are formed in the vertical direction on the P active region 53b and the N active region 54b. Polysilicon layers 59b are formed side by side at predetermined intervals.

  A GND metal wiring layer 65 a is formed on the P well contact region 55 a, and the GND metal wiring layer 65 a and the P well contact region 55 a are electrically connected through a plurality of contact holes 71. Further, the GND metal wiring layer 65a is the (4i) th and (4i + 1) th from the left on the left N active region 54a of the leftmost gate polysilicon layer 59a among the 16 gate polysilicon layers 59a. (I = 1 to 3) formed on the N active region 54a between the gate polysilicon layers 59a and 59a and on the N active region 54a on the right side of the rightmost gate polysilicon layer 59a. 71 is electrically connected to the N active region 54a (corresponding to the source region of the NMOS transistor) via 71.

  Similarly, a GND metal wiring layer 65 b is formed on the P well contact region 55 b, and the GND metal wiring layer 65 b and the P well contact region 55 b are electrically connected through a plurality of contact holes 71. Further, the GND metal wiring layer 65b includes the (4i) th and (4i + 1) th from the left on the left N active region 54b of the leftmost gate polysilicon layer 59b among the 16 gate polysilicon layers 59b. (I = 1 to 3) formed on the N active region 54b between the gate polysilicon layers 59b and 59b and on the right N active region 54b of the rightmost gate polysilicon layer 59b. 71 is electrically connected to the N active region 54 b (corresponding to the source region of the NMOS transistor) through 71.

  An output metal wiring layer 63a is formed across most of the 16 gate polysilicon layers 59a on the N active region 54a, and the output metal wiring layer 63a further includes 16 gate polysilicon layers 59a. Of these, the N active region 54a is formed extending from the left to the N active region 54a between the (4i + 2) th and (4i + 3) th (i = 0-3) gate polysilicon layers 59a, 59a. 54a (corresponding to the drain region of the NMOS transistor) is electrically connected.

  Similarly, an output metal wiring layer 63b is formed across most of the 16 gate polysilicon layers 59b on the N active region 54b, and the output metal wiring layer 63b further includes 16 gate poly layers. Of the silicon layer 59b, it is formed to extend on the N active region 54b between the (4i + 2) th and (4i + 3) th (i = 0-3) gate polysilicon layers 59b, 59b from the left, via the contact hole 71. Are electrically connected to the N active region 54b (corresponding to the drain region of the NMOS transistor).

  A first input metal wiring layer 61a is formed across most of the 16 gate polysilicon layers 59a, and the first input metal wiring layer 61a is formed from the left of the 16 gate polysilicon layers 59a. Formed on the (4i + 2) th and (4i + 3) th (i = 0 to 3) gate polysilicon layers 59a, 59a, the corresponding gate polysilicon layer 59a (receives the first input) via the contact hole 71. Electrically connected to the gate electrodes of the first PMOS transistor and the first NMOS transistor).

  Similarly, a first input metal wiring layer 61b is formed across most of the 16 gate polysilicon layers 59b, and the first input metal wiring layer 61b is formed of the 16 gate polysilicon layers 59b. Of these, the gate polysilicon layers 59b and 59b are formed extending from the left to the (4i + 2) th and (4i + 3) th (i = 0 to 3) th gate polysilicon layers 59b and 59b. Electrically connected to the gate electrodes of the first PMOS transistor and the first NMOS transistor).

  A first input metal wiring layer 81 is formed in a layer different from the first input metal wiring layers 61a and 61b by vertically cutting between the first input metal wiring layers 61a and 61b. The layer 81 and the first input metal wiring layers 61a and 61b are electrically connected through the via holes 72, respectively.

  A VDD metal wiring layer 64 is formed on the N well contact region 56, and the VDD metal wiring layer 64 and the N well contact region 56 are electrically connected through a plurality of contact holes 71.

  Further, the VDD metal wiring layer 64 is formed on the P active region 53a from the left (2i) on the P active region 53a on the left side of the leftmost gate polysilicon layer 59a among the 16 gate polysilicon layers 59a. ) And (2i + 1) th (i = 1 to 7) gate polysilicon layers 59a, 59a between P active regions 53a and rightmost P active region 53a of gate polysilicon layer 59a, respectively. It extends and is electrically connected to the P active region 53a (corresponding to the source region of the PMOS transistor) through the contact hole 71.

  Similarly, the VDD metal wiring layer 64 is formed on the left side P active region 53b of the leftmost gate polysilicon layer 59b out of the 16 gate polysilicon layers 59b on the P active region 53b. On the P active region 53b between the (2i) th and (2i + 1) th (i = 1 to 7) gate polysilicon layers 59b, 59b, and on the right P active region 53b of the rightmost gate polysilicon layer 59b And is electrically connected to the P active region 53b (corresponding to the source region of the PMOS transistor) through the contact hole 71.

  An inter-Tr connection metal wiring layer 66a is formed across most of the 16 gate polysilicon layers 59a on the P active region 53a, and the inter-Tr connection metal wiring layer 66a further includes 16 gates. The polysilicon layer 59a is formed to extend on the P active region 53a between the (2i-1) th and (2i) th (i = 1 to 8) gate polysilicon layers 59a, 59a from the left, respectively, and is a contact hole. 71 is electrically connected to the P active region 53a (corresponding to the drain region of the PMOS transistor) via 71.

  Similarly, an inter-Tr connection metal wiring layer 66b is formed across most of the gate polysilicon layer 59b on the P active region 53b, and the inter-Tr connection metal wiring layer 66b includes 16 wires. The gate polysilicon layer 59b is formed to extend on the P active region 53b between the (2i-1) th and (2i) th (i = 1 to 8) th gate polysilicon layers 59b and 59b from the left, respectively. It is electrically connected to the P active region 53b (corresponding to the drain region of the PMOS transistor) through the hole 71.

  Then, the output metal wiring layer 63a, the Tr connecting metal wiring layer 66a, the Tr connecting metal wiring layer 66b, and the output metal wiring layer 63b are cut vertically to form the output metal wiring layers 63a and 63b and the Tr. An output metal wiring layer 83 is formed in a layer different from the connection metal wiring layers 66a and 66b, and the output metal wiring layer 83, the output metal wiring layers 63a and 63b, and the inter-Tr connection metal wiring layers 66a and 66b. Each is electrically connected via a via hole 72.

  A second input metal wiring layer 62a is formed across the 16 gate polysilicon layers 59a on the P active region 53a, and the second input metal wiring layer 62a includes 16 gate polysilicon layers. 59a, the leftmost gate polysilicon layer 59a, the (4i) th and (4i + 1) th (i = 1 to 3) gate polysilicon layers 59a and 59a from the left, and the rightmost gate polysilicon layer The gate polysilicon layers 59a (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) are electrically connected to the corresponding gate polysilicon layers 59a through the contact holes 71. Is done.

  Similarly, the second input metal wiring layer 62b is formed across the 16 gate polysilicon layers 59b on the P active region 53b, and the second input metal wiring layer 62b includes 16 Of the gate polysilicon layer 59b, on the leftmost gate polysilicon layer 59b, on the (4i) th and (4i + 1) th (i = 1 to 3) th gate polysilicon layers 59b and 59b from the left, and on the rightmost A gate polysilicon layer 59b (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor that receives the second input) is formed on the gate polysilicon layer 59b and extends through the contact hole 71, respectively. Electrically connected.

  A second input metal wiring layer 82 is formed in a layer different from the second input metal wiring layers 62a and 62b by vertically cutting between the second input metal wiring layers 62a and 62b. The layer 82 and the second input metal wiring layers 62a and 62b are electrically connected through the via holes 72, respectively.

  Like the macro cell M11, the macro cell M12 having such a configuration includes a first PMOS transistor and a first NMOS transistor each receiving the first input at the gate electrode, and a second input receiving the second input at the gate electrode. A two-input NAND gate serving as a PMOS transistor and a second NMOS transistor is composed of 16 units of transistors. The macro cell M12 is provided with a power supply wiring (VDD metal wiring layer 64) at the center of the cell in plan view, and two GND wirings (GND metal wiring layers 65a and 65b) divided in the upper and lower parts of the plan view. The first transistor formation region (P active region 53a, N active region 54a) is disposed between the wiring layer 65a and the VDD metal wiring layer 64, and the second transistor forming region is interposed between the GND metal wiring layer 65b and the VDD metal wiring layer 64. Transistor formation regions (P active region 53b, N active region 54b) are arranged.

  That is, the distance (first distance) between the well contact regions formed between the upper and lower ends of the macro cell M12 (between the P well contact regions 55a and 55b) is between the well contact regions formed at the upper and lower ends of the macro cell M11. A double height cell configuration that is twice the distance (second distance) between the N well contact region 56 and the P well contact region 55 is employed to suppress an increase in the cell area in the lateral direction.

(Double height cell structure (2))
FIG. 16 is a plan view showing a cell structure of a macro cell M13 having a double height cell configuration (No. 2) which is a prerequisite technology of the present invention. The macro cell M13 includes a 16-unit transistor that is a 2-input NAND gate equivalent to the macro cells M11 and M12.

  As shown in FIG. 16, a P-well contact region 55 is formed in the central portion of the P-well region 51 so as to extend in the lateral direction. The rectangular N active regions 54b are selectively formed extending in the lateral direction. Further, a rectangular N well region 52a extends selectively in the lateral direction above the N active region 54a in plan view, and a rectangular N well region 52b extends in the lateral direction below the N active region 54b in plan view. It extends and is selectively formed.

  In each of the N well regions 52a and 52b, rectangular P active regions 53a and 53b are selectively formed extending in the lateral direction. An N well contact region 56a is formed extending laterally above the P active region 53a in plan view in the N well region 52a, and an N well contact region 56b is formed in the N well region 52b below the P active region 53b in plan view. It is formed extending in the lateral direction.

  Sixteen gate polysilicon layers 59a are formed side by side at predetermined intervals in the vertical direction on the P active region 53a and the N active region 54a, and the gates are formed in the vertical direction on the P active region 53b and the N active region 54b. Polysilicon layers 59b are formed side by side at predetermined intervals.

  A VDD metal wiring layer 64 a is formed on the N well contact region 56 a, and the VDD metal wiring layer 64 a and the N well contact region 56 a are electrically connected through a plurality of contact holes 71. Further, the metal wiring layer 64a for VDD is the (2i) th and (2i + 1) th from the left on the left P active region 53a of the leftmost gate polysilicon layer 59a among the 16 gate polysilicon layers 59a. (I = 1 to 7) formed on the P active region 53a between the gate polysilicon layers 59a and 59a and on the right P active region 53a of the rightmost gate polysilicon layer 59a. 71 is electrically connected to the P active region 53a (corresponding to the source region of the PMOS transistor) via 71.

  Similarly, a VDD metal wiring layer 64 b is formed on the N well contact region 56 b, and the VDD metal wiring layer 64 b and the N well contact region 56 b are electrically connected through a plurality of contact holes 71. Further, the metal wiring layer 64b for VDD is the (2i) th and (2i + 1) th from the left on the P active region 53b on the left side of the leftmost gate polysilicon layer 59b among the 16 gate polysilicon layers 59b. (I = 1-7) formed on the P active region 53b between the gate polysilicon layers 59b and 59b and on the right P active region 53b of the rightmost gate polysilicon layer 59b. The P active region 53 b (corresponding to the source region of the PMOS transistor) is electrically connected via the 71.

  A Tr interconnection metal wiring layer 66a is formed across most of the 16 gate polysilicon layers 59a on the P active region 53a. Further, the Tr interconnection metal wiring layer 66a includes 16 gate polysilicon layers. Of the silicon layer 59a, the contact hole 71 is formed extending on the P active region 53a between the (2i-1) th and (2i) th (i = 1 to 8) gate polysilicon layers 59a, 59a from the left. Is electrically connected to the P active region 53a (corresponding to the drain region of the PMOS transistor).

  Similarly, an inter-Tr connection metal wiring layer 66b is formed across most of the 16 gate polysilicon layers 59b on the P active region 53b. Among the gate polysilicon layers 59b, the gate polysilicon layers 59b are formed extending from the left to the P active region 53b between the (2i-1) th and (2i) th (i = 1 to 8) gate polysilicon layers 59b and 59b. The P active region 53b (corresponding to the drain region of the PMOS transistor) is electrically connected through the contact hole 71.

  A second input metal wiring layer 62a is formed across the 16 gate polysilicon layers 59a, and the second input metal wiring layer 62a is the leftmost gate polysilicon layer among the 16 gate polysilicon layers 59a. Formed on the silicon layer 59a, on the (4i) th and (4i + 1) th (i = 1 to 3) gate polysilicon layers 59b and 59b from the left, and on the rightmost gate polysilicon layer 59a. The contact gate 71 is electrically connected to the corresponding gate polysilicon layer 59a (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input).

  Similarly, a second input metal wiring layer 62b is formed across the 16 gate polysilicon layers 59b, and the second input metal wiring layer 62b is the outermost of the 16 gate polysilicon layers 59b. It extends on the leftmost gate polysilicon layer 59b, on the (4i) th and (4i + 1) th (i = 1 to 3) th gate polysilicon layers 59b and 59b from the left, and on the rightmost gate polysilicon layer 59b. And is electrically connected to the corresponding gate polysilicon layer 59b (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) through the contact hole 71.

  A second input metal wiring layer 82 is formed in a layer different from the second input metal wiring layers 62a and 62b by vertically cutting between the second input metal wiring layers 62a and 62b. The layer 82 and the second input metal wiring layers 62a and 62b are electrically connected through the via holes 72, respectively.

  A GND metal wiring layer 65 is formed on the P well contact region 55, and the GND metal wiring layer 65 and the P well contact region 55 are electrically connected through a plurality of contact holes 71.

  Further, the GND metal wiring layer 65 is formed on the N active region 54a from the left (4i) on the N active region 54a on the left side of the leftmost gate polysilicon layer 59a among the 16 gate polysilicon layers 59a. ) And (4i + 1) -th (i = 1 to 3) gate polysilicon layers 59a, 59a and N-active region 54a on the right side of rightmost gate polysilicon layer 59a, respectively. It extends and is electrically connected to the N active region 54a (corresponding to the source region of the NMOS transistor) through the contact hole 71.

  Similarly, the GND metal wiring layer 65 is formed on the N active region 54b on the left side of the leftmost gate polysilicon layer 59b among the 16 gate polysilicon layers 59b on the N active region 54b. On the N active region 54b between the (4i) th and (4i + 1) th (i = 1 to 3) gate polysilicon layers 59b, 59b, and on the N active region 54b on the right side of the rightmost gate polysilicon layer 59b And are electrically connected to the N active region 54b (corresponding to the source region of the NMOS transistor) through the contact hole 71.

  An output metal wiring layer 63a is formed across most of the gate polysilicon layer 59a on the N active region 54a, and the output metal wiring layer 63a is composed of 16 gate polysilicon layers 59a. From the left, the (4i + 2) th and (4i + 3) th (i = 0 to 3) gate polysilicon layers 59a are formed on the N active region 54a between the gate polysilicon layers 59a and 59a. Electrically connected to the drain region of the NMOS transistor).

  Similarly, an output metal wiring layer 63b is formed across most of the gate polysilicon layer 59b on the N active region 54b, and the output metal wiring layer 63b includes 16 gate polysilicon layers. 59b, the (4i + 2) th and (4i + 3) th (i = 0 to 3) gate polysilicon layers 59b and 59b from the left are formed to extend over the N active region 54b, and N It is electrically connected to the active region 54b (corresponding to the drain region of the NMOS transistor).

  Then, the Tr interconnection metal wiring layers 66a and 66b and the output metal interconnection layers 63a and 63b are vertically cut to a layer different from the Tr interconnection metal wiring layers 66a and 66b and the output metal interconnection layers 63a and 66b. An output metal wiring layer 83 is formed, and the output metal wiring layer 83 is electrically connected to the inter-Tr connection metal wiring layers 66a and 66b and the output metal wiring layers 63b and 66b through the via holes 72, respectively. .

  A first input metal wiring layer 61a is formed across most of the 16 gate polysilicon layers 59a, and the first input metal wiring layer 61a is formed of the 16 gate polysilicon layers 59a. The gate polysilicon layers 59a are formed on the (4i + 2) th and (4i + 3) th (i = 0-3) gate polysilicon layers 59a, 59a from the left, respectively. Electrically connected to the gate electrodes of the first PMOS transistor and the first NMOS transistor).

  Similarly, a first input metal wiring layer 61b is formed across most of the 16 gate polysilicon layers 59b, and the first input metal wiring layer 61b is formed of 16 gate polysilicon layers. Among the layers 59b, the gate polysilicon layers 59b and 59b extending from the left to the (4i + 2) th and (4i + 3) th (i = 0 to 3) th (i = 0 to 3) gate polysilicon layers 59b and 59b are formed. It is electrically connected to the layer 59b (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input).

  A first input metal wiring layer 81 is formed in a layer different from the first input metal wiring layers 61a and 61b by vertically cutting between the first input metal wiring layers 61a and 61b. The layer 81 and the first input metal wiring layers 61a and 61b are electrically connected through the via holes 72, respectively.

  In the macro cell M13 having such a configuration, the two-input NAND gate is configured by 16 units of transistors, like the macro cells M11 and M12. The macro cell M13 is provided with a GND wiring (GND metal wiring layer 65) in the center of the cell in plan view, and two power supply wirings (VDD metal wiring layers 64a and 64b) divided into upper and lower parts of the plan view. A first transistor formation region (P active region 53a, N active region 54a) is disposed between the wiring layer 64a and the GND metal wiring layer 65, and the second transistor forming region is interposed between the VDD metal wiring layer 64b and the GND metal wiring layer 65. The double-height cell configuration in which the transistor formation regions (P active region 53b and N active region 54b) are arranged is used to suppress an increase in the cell area in the lateral direction.

  However, in the above-described macro cells M12 and M13 having the double-height cell structure, the N-well contact region 56 and the VDD metal wiring layer 64 for supplying power or the P-well contact region 55 and supplying power for the N-well contact region 56 in the center of the cell region. As described above, since the GND metal wiring layer 65 is disposed transversely, the first and second transistor formation regions are divided into upper and lower parts in plan view, thereby degrading the use efficiency of the active region. The problem remains.

  Accordingly, the following first to first embodiments are aimed at obtaining a macro cell structure in which the cell area is reduced without deteriorating the use efficiency of an active region for forming an element such as a transistor. 7 macrocells and the semiconductor integrated circuit of the eighth embodiment.

<Embodiment 1>
FIG. 1 is a plan view showing a cell structure of a macro cell M1 having a double-height cell configuration according to Embodiment 1 of the present invention. FIG. 2 is an explanatory view schematically showing an irregular AA cross-sectional structure of FIG. FIG. 3 is an explanatory view schematically showing an irregular BB cross-sectional structure of FIG.

  The macro cell M1 shown in these figures implements a 2-input NAND gate, which will be described in detail later, with a 12-unit basic transistor configuration (a MOS transistor formed by one gate polysilicon layer 9 is used as a single unit basic transistor). is doing. 2 and 3, first input metal wiring layers 11a and 11b, second input metal wiring layers 12a and 12b (not shown in FIGS. 2 and 3), output metal wiring layer 13a and 13b, VDD metal wiring layer 14 (well contact portion 14c), GND metal wiring layers 15a and 15b, and Tr inter-connection metal wiring layers 16a and 16b are formed in the same layer. The first and second input metal wiring layers (not shown) and the output signal connection metal wiring layer 33 are second layer metal wirings formed in a layer different from the first layer metal wiring. Therefore, the first layer metal wiring and the second layer metal wiring do not come into electrical contact.

  As shown in FIGS. 2 and 3, the P well region 1 and the N well region 2 are formed in the upper layer portion of the semiconductor substrate 10, and the P active region 3 and the N well contact region 6 having a rectangular shape in plan view are formed in the N well. N active regions 4a and 4b and P well contact regions 5a and 5b, which are formed on the surface of region 2 and have a rectangular shape in plan view, are formed on the surface of P well region 1. N well contact region 6 functions as a substrate potential setting region for setting the substrate potential of a PMOS transistor formed in P active region 3, and P well contact regions 5a and 5b are formed in N active regions 4a and 4b. It functions as a substrate potential setting region (second and third substrate potential setting regions) for setting the substrate potential of the NMOS transistor.

  Hereinafter, the structure of the macro cell M1 will be described with reference to FIGS. As shown in FIG. 1, a rectangular N-well region 2 is formed extending in the lateral direction at the center between the P-well regions 1 and 1. An N active region 4a is selectively formed by extending in the lateral direction above (on one side) the N well region 2 in a plan view and N active region 4b below (on the other side) in a plan view. In the P well region 1, a P well contact region 5 a extends selectively in the lateral direction above the N active region 4 a in plan view (on the side opposite to the P active region 3 in the vertical direction with respect to the N active region 4 a). A P well contact region 5b is selectively formed to extend in the lateral direction below the N active region 4b in plan view (on the side opposite to the P active region 3 in the vertical direction with respect to the N active region 4b).

  In the N well region 2, a rectangular P active region 3 is selectively formed in the center in plan view, and a vertical direction is formed in a region near the left side (predetermined side) in the lateral direction (second direction) of the P active region 3. An N well contact region 6 is formed extending in the (first direction).

  Twelve gate polysilicon layers 9 formed by vertically running on the P active region 3 and the N active regions 4a and 4b are arranged in the horizontal direction at predetermined intervals.

  A GND metal wiring layer 15a is formed on P well contact region 5a, and GND metal wiring layer 15a and P well contact region 5a are electrically connected through a plurality of contact holes 21 (see FIG. 2). . Further, the GND metal wiring layer 15a includes N gates between the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 and 9 out of the twelve gate polysilicon layers 9. Each is formed extending on active region 4a, and is electrically connected to N active region 4a (corresponding to the source region of the NMOS transistor) through contact hole 21.

  Similarly, a GND metal wiring layer 15b is formed on the P well contact region 5b, and the GND metal wiring layer 15b and the P well contact region 5b are electrically connected via a plurality of contact holes 21 ( (See FIG. 2). Further, the GND metal wiring layer 15b includes an N between the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 and 9 out of the twelve gate polysilicon layers 9. Each is formed extending on active region 4b, and is electrically connected to N active region 4b (corresponding to the source region of the NMOS transistor) through contact hole 21.

  An output metal wiring layer 13 a is formed across the gate polysilicon layer 9 on the N active region 4 a, and the output metal wiring layer 13 a is the leftmost gate of the 12 gate polysilicon layers 9. On the N active region 4a on the left side of the polysilicon layer 9, on the N active region 4a between the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9, 9 from the left, and on the top Each is formed to extend on the right N active region 4a of the rightmost gate polysilicon layer 9, and is electrically connected to the N active region 4a (corresponding to the drain region of the NMOS transistor) through the contact hole 21 ( (See FIG. 2).

  Similarly, an output metal wiring layer 13b is formed across the gate polysilicon layer 9 on the N active region 4b, and the output metal wiring layer 13b includes the 12 gate polysilicon layers 9, On the left N active region 4b of the leftmost gate polysilicon layer 9, the N active region 4b between the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9, 9 from the left The upper and rightmost gate polysilicon layers 9 are formed to extend on the N active region 4b on the right side, and are electrically connected to the N active region 4b (corresponding to the drain region of the NMOS transistor) through the contact hole 21. Connected (see FIG. 2).

  A first input metal wiring layer 11 a is formed across the 12 gate polysilicon layers 9, and the first input metal wiring layer 11 a is the leftmost gate polysilicon layer among the 12 gate polysilicon layers 9. The silicon layer 9 is formed to extend on the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9 and 9 from the left, and on the rightmost gate polysilicon layer 9, respectively. It is electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input) via the contact hole 21 (see FIG. 2).

  Similarly, a first input metal wiring layer 11 b is formed across the 12 gate polysilicon layers 9, and the first input metal wiring layer 11 b is the outermost of the 12 gate polysilicon layers 9. It extends on the leftmost gate polysilicon layer 9, on the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9 and 9, and on the rightmost gate polysilicon layer 9 from the left. And is electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input) via the contact hole 21 (FIG. 2). reference).

  Then, a second layer metal wiring corresponding to the first input metal wiring layer 81 of FIG. 15 is formed in a layer different from the first input metal wiring layers 11a and 11b by vertically cutting between the first input metal wiring layers 11a and 11b. The first input connection metal wiring layer (not shown) is formed, and the first input connection metal wiring layer and the first input metal wiring layers 11a and 11b are respectively connected via via holes (not shown) corresponding to the via holes 22. Are electrically connected.

  A VDD metal wiring layer 14 is formed across the central portion of the P active region 3, and a well contact portion 14 c which is a part of the VDD metal wiring layer 14 is also formed on the N well contact region 6. Well contact portion 14c and N well contact region 6 are electrically connected through a plurality of contact holes 21 (see FIGS. 2 and 3).

  Further, the VDD metal wiring layer 14 is formed on the P active region 3 from among the 12 gate polysilicon layers 9 on the leftmost P active region 3 of the leftmost gate polysilicon layer 9 (2i). ) And (2i + 1) th (i = 1 to 5) gate polysilicon layers 9, 9 on the P active region 3, and on the rightmost gate polysilicon layer 9 on the right P active region 3. It is formed to extend upward and downward in plan view, and is electrically connected to the P active region 3 (corresponding to the source region of the PMOS transistor) through the contact hole 21 (see FIG. 3).

  A Tr interconnect metal wiring layer 16a is formed across most of the twelve gate polysilicon layers 9 on the P active region 3 above the VDD metal interconnect layer 14 in plan view. The connecting metal wiring layer 16a includes a P between the (2i-1) th and (2i) th (i = 1 to 6) gate polysilicon layers 9, 9 out of the twelve gate polysilicon layers 9. Each is formed extending on the active region 3 and is electrically connected to the P active region 3 (corresponding to the drain region of the PMOS transistor) through the contact hole 21.

  Similarly, a Tr interconnection metal wiring layer 16b is formed across most of the 12 gate polysilicon layers 9 on the P active region 3 below the VDD metal wiring layer 14 in plan view. Further, the Tr interconnection metal wiring layer 16b includes the (2i-1) th and (2i) th (i = 1 to 6) gate polysilicon layers 9 out of the twelve gate polysilicon layers 9, The P active regions 3 are formed so as to extend between the nine active regions 3 and are electrically connected to the P active regions 3 (corresponding to the drain regions of the PMOS transistors) via the contact holes 21 (see FIG. 3).

  Then, the output metal wiring layer 13a, the Tr connecting metal wiring layer 16a, the Tr connecting metal wiring layer 16b and the output metal wiring layer 13b are cut vertically to form the output metal wiring layers 13a and 13b and the Tr. An output signal connection metal wiring layer 33 which is a second layer aluminum wiring is formed in a layer different from the connection metal wiring layers 16a and 16b, and the output signal connection metal wiring layer 33, the output metal wiring layers 13a and 13b, and Tr The inter-connection metal wiring layers 16a and 16b are electrically connected through the via holes 22, respectively.

  A second input metal wiring layer 12a is formed across most of the twelve gate polysilicon layers 9 on the P active region 3 above the Tr connecting metal wiring layer 16a in plan view. The second input metal wiring layer 12a is on the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 and 9 from the left of the 12 gate polysilicon layers 9, respectively. The gate polysilicon layer 9 is formed extending to be electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) through the contact hole 21.

  Similarly, a second input metal wiring layer 12b is formed across most of the twelve gate polysilicon layers 9 on the P active region 3 below the Tr interconnection metal wiring layer 16b in plan view. Further, the second input metal wiring layer 12b includes the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 from the left among the twelve gate polysilicon layers 9. 9 is formed extending over the gate 9 and electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) via the contact holes 21. Is done.

  Then, a second layer metal corresponding to the second input metal wiring layer 82 in FIG. 15 is formed in a layer different from the second input metal wiring layers 12a and 12b by vertically cutting between the second input metal wiring layers 12a and 12b. A second input connection metal wiring layer (not shown) as a wiring is formed, and the second input connection metal wiring layer and the second input metal wiring layers 12a and 12b are electrically connected via via holes corresponding to the via holes 22, respectively. Connected.

  FIG. 4 is a circuit diagram showing a NAND gate G1 realized by the macro cell M1. As shown in the figure, the NAND gate G1 receives an input signal A (first input) and an input signal B (second input), and outputs the NAND operation result as an output signal YB.

  FIG. 5 is a circuit diagram showing a transistor configuration for realizing the NAND gate G1. As shown in the figure, the NAND gate G1 is realized by the PMOS transistors Q1, Q2 (first and second PMOS transistors) and the NMOS transistors Q3, Q4 (first and second NMOS transistors). The

  The sources of the PMOS transistors Q1 and Q2 are commonly connected to the power supply VDD (via the VDD metal wiring layer 14), and the drains of the PMOS transistors Q1 and Q2 are commonly connected to the drain of the NMOS transistor Q3. The source is connected to the drain of the NMOS transistor Q4, and the source of the NMOS transistor Q4 is connected to the GND level (via the GND metal wiring layers 15a and 15b). The gates of the PMOS transistor Q1 and the NMOS transistor Q3 receive the input signal A (via the first input metal wiring layers 11a and 11b), and the gates of the PMOS transistor Q2 and the NMOS transistor Q4 (second input metal wiring). An input signal B is received (via layers 12a, 12b). A signal obtained from the drain of the PMOS transistor Q2 (NMOS transistor Q3) (via the output metal wiring layers 13a and 13b) is the output signal YB.

  When the PMOS transistor and the NMOS transistor constituted by one gate polysilicon layer 9 are basic transistors of one unit (Finger number 1), the macro cell M1 has 12 units (Finger number) of the NAND gate G1 having the configuration shown in FIG. 12) The basic transistor configuration is realized.

  The macro cell M1 of the first embodiment having such a configuration is divided into a power supply wiring (VDD metal wiring layer 14) in the center of the cell in plan view, and two GND wirings (GND metal wiring layer) divided upward and downward in plan view. 15a, 15b), the PMOS transistor forming active region is composed only of the P active region 3, and the NMOS transistor forming first active region (N active region 4a) is formed above the P active region 3 in plan view. And adopting a double-height cell configuration in which a second active region (N active region 4b) for forming an NMOS transistor is disposed below the P active region 3 in plan view, thereby suppressing an increase in the cell area in the lateral direction. is doing.

  In the macro cell M1, an N well contact region 6 is provided in a region on the left side of the P active region 3 in the lateral direction, and the electricity by the contact hole 21 with the well contact portion 14c of the metal wiring layer 14 for VDD on the N well contact region 6 is provided. Connections are made.

  For this reason, by forming the N well contact region 6, the P active region 3 for forming the PMOS transistor is not divided into upper and lower parts in plan view like the P active regions 53a and 53b of the macro cell M12 shown in FIG. It can be formed as one region.

  The vertical formation length (first length) of the P active region 3 defines the gate width of a single unit PMOS transistor structure realized by one gate polysilicon layer 9 that vertically cuts the P active region 3. The gate width defines operating characteristics such as driving capability (predetermined operating characteristics).

  As a result, the N well contact region 56 and the region sandwiched between the N well contact region 56 and the P active regions 53a and 53b in the macro cell M12 having the double height cell structure shown in FIG. The gate width of the one-unit PMOS transistor configuration can be made larger than the gate width of the one-unit PMOS transistor configuration of the macro cell M12 (defined by the sum of the vertical formation lengths of the P active regions 53a and 53b).

  Therefore, in the macro cell M1 of the first embodiment, the total gate width by the 12-unit PMOS transistor is made substantially equal to the total gate width by the 16-unit PMOS transistor in the macro cell M12 shown in FIG. Therefore, the operation characteristics equivalent to those of the macro cell M12 can be exhibited.

  As a result, when the operating characteristics of the macro cell M1 are realized at the same level as the macro cell M12, the width of the P active region 3 can be made narrower than the width of the P active regions 53a and 53b of the macro cell M12 shown in FIG. There is an effect that the usage rate of the P active region 3 for forming the PMOS transistor can be improved.

<Embodiment 2>
FIG. 6 is a plan view showing a cell structure of a macro cell M2 having a double height cell configuration according to the second embodiment of the present invention.

  The basic configuration of the macro cell M2 is the same as that of the macro cell M1, except that a two-input NAND gate is realized by a basic transistor configuration of 16 units. Hereinafter, the macro cell M2 will be described focusing on differences from the macro cell M1. As in the first embodiment, the first input metal wiring layer and the via hole are not shown.

  In the N well region 2, the P active region 3L of the first embodiment is selectively formed in the center in plan view extending in the lateral direction longer than the lateral width of the P active region 3 of the first embodiment. An N well contact region 6 is formed extending in the vertical direction in the region on the left side in the horizontal direction.

  Sixteen gate polysilicon layers 9 formed by vertically running on the P active region 3L and the N active regions 4a and 4b are arranged side by side at predetermined intervals.

  The GND metal wiring layer 15a includes the (4i) th and (4i + 1) th (i) from the left on the left active N region 4a of the leftmost gate polysilicon layer 9 among the 16 gate polysilicon layers 9. = 1 to 3) formed on the N active region 4a between the gate polysilicon layers 9 and 9 and on the N active region 4a on the right side of the rightmost gate polysilicon layer 9, respectively. And electrically connected to the N active region 4a (corresponding to the source region of the NMOS transistor). Similarly to the GND metal wiring layer 15a, the GND metal wiring layer 15b is also formed on the N active region 4b.

  The output metal wiring layer 13a is an N active region between the (4i + 2) th and (4i + 3) th (i = 0-3) gate polysilicon layers 9, 9 from the left among the 16 gate polysilicon layers 9. 4a are formed to extend on 4a and are electrically connected to N active region 4a (corresponding to the drain region of the NMOS transistor) through contact hole 21 (see FIG. 2). Similarly to the output metal wiring layer 13a, the output metal wiring layer 13b is also formed on the N active region 4b.

  The first input metal wiring layer 11a is formed on the (4i + 2) th and (4i + 3) th (i = 0-3) gate polysilicon layers 9, 9 from the left of the 16 gate polysilicon layers 9, respectively. It extends and is electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input) through the contact hole 21. The first input metal wiring layer 11b is also electrically connected to the gate polysilicon layer 9 in the same manner as the first input metal wiring layer 11a.

  A VDD metal wiring layer 14 is formed across the center of the P active region 3L, and a well contact portion 14c, which is a part of the VDD metal wiring layer 14, is also formed on the N well contact region 6. The well contact portion 14 c and the N well contact region 6 are electrically connected through a plurality of contact holes 21.

  Further, the VDD metal wiring layer 14 is formed on the P active region 3L from the left on the P active region 3L on the left side of the leftmost gate polysilicon layer 9 among the 16 gate polysilicon layers 9 (2i). ) And (2i + 1) th (i = 1 to 7) gate polysilicon layers 9, 9 on the P active region 3L, and on the rightmost gate polysilicon layer 9 on the right P active region 3L. It is formed to extend upward and downward in plan view, and is electrically connected to the P active region 3L (corresponding to the source region of the PMOS transistor) through the contact hole 21.

  The inter-Tr connection metal wiring layer 16a is formed between the (2i-1) th and (2i) th (i = 1 to 8) gate polysilicon layers 9, 9 of the 16 gate polysilicon layers 9. The P active region 3L is formed to extend on the P active region 3L, and is electrically connected to the P active region 3L (corresponding to the drain region of the PMOS transistor) through the contact hole 21. Similarly to the Tr interconnection metal wiring layer 16a, the Tr interconnection metal wiring layer 16b is also electrically connected to the P active region 3L below the VDD metal interconnection layer 14 in plan view.

  The second input metal wiring layer 12a is the (4i) th and (4i + 1) th (i = 1-3) from the left on the leftmost gate polysilicon layer 9 among the 16 gate polysilicon layers 9. The gate polysilicon layers 9 and 9 and the rightmost gate polysilicon layer 9 are formed to extend to the corresponding gate polysilicon layer 9 (second PMOS transistor receiving the second input and the second input via the contact hole 21). Electrically connected to the gate electrode of the second NMOS transistor). Similarly, second input metal wiring layer 12b is electrically connected to gate polysilicon layer 9.

  The macro cell M2 includes the NAND gate G1 having the configuration shown in FIG. 5 and includes 16 units (Finger number 16), and adopts a double height cell configuration, like the macro cell M1 of the first embodiment, and has a cell area in the horizontal direction. The increase is suppressed.

  In the macro cell M2, an N well contact region 6 is provided in the region on the left side in the lateral direction of the P active region 3L, and the electrical contact by the contact hole 21 with the well contact portion 14c of the metal wiring layer 14 for VDD on the N well contact region 6 is provided. Connection is made.

  For this reason, as in the first embodiment, the N well contact region 56 in the macro cell M12 and the region sandwiched between the N well contact region 56 and the P active regions 53a and 53b can also be used as the P active region 3L. The gate width of the PMOS transistor (basic transistor) can be made larger than that of the macro cell M12.

  Therefore, in the macro cell M2 of the second embodiment, the total gate width of the 16 units of PMOS transistors can be set larger than the total gate width of the 16 units of PMOS transistors in the macro cell M12 shown in FIG. The above operating characteristics can be exhibited.

  As a result, it is possible to increase the number of basic transistor units (number of fingers) while improving the usage rate of the P active region 3L for forming the PMOS transistor, and also to exhibit the effect of improving the operating characteristics such as driving ability. Can do.

<Embodiment 3>
FIG. 7 is a plan view showing a cell structure of a macro cell M3 having a double height cell configuration according to the third embodiment of the present invention.

  The basic configuration of the macro cell M3 is realized by a 12-unit basic transistor configuration in the same manner as the macro cell M1. Hereinafter, the macro cell M3 will be described focusing on differences from the macro cell M1.

  In the vicinity of the N active region 4 b, a first input metal wiring layer 11 is formed across the 12 gate polysilicon layers 9, and the first input metal wiring layer 11 includes the 12 gate polysilicon layers 9. Among these, on the leftmost gate polysilicon layer 9, on the (4i + 2) th and (4i + 3) th (i = 0 to 2) th gate polysilicon layers 9, 9 from the left, and on the rightmost gate polysilicon layer 9 And electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input) through the contact hole 21. .

  A VDD metal wiring layer 14L (first metal wiring layer) is formed across the vicinity of the upper end portion of the P active region 3, and the well contact portion 14c, which is a part of the VDD metal wiring layer 14L, It is also formed on well contact region 6, and well contact portion 14 c and N well contact region 6 are electrically connected via a plurality of contact holes 21.

  Further, the metal wiring layer 14L for VDD is formed on the P active region 3 from among the 12 gate polysilicon layers 9 on the leftmost P active region 3 of the leftmost gate polysilicon layer 9 (2i ) And (2i + 1) th (i = 1 to 5) gate polysilicon layers 9, 9 on the P active region 3, and on the rightmost gate polysilicon layer 9 on the right P active region 3. , Extending downward from the upper end in the vertical direction in the P active region 3 and electrically connected to the P active region 3 (corresponding to the source region (one electrode region) of the PMOS transistor) through the contact hole 21. .

  In a region below the P active region 3 in plan view, a Tr interconnection metal wiring layer 16 (second metal wiring layer) crosses over most of the 12 gate polysilicon layers 9 on the P active region 3. In addition, the Tr interconnection metal wiring layer 16 includes (2i-1) th and (2i) th (i = 1 to 6) gate polysilicons from the left among the twelve gate polysilicon layers 9. On the P active region 3 between the layers 9, 9, the P active region 3 (the drain region of the PMOS transistor (the other electrode) is formed through the contact hole 21, extending upward from the lower end in the vertical direction in the P active region 3. Is electrically connected to the area).

  Then, the output metal wiring layer 13a, the Tr connection metal wiring layer 16 and the output metal wiring layer 13b are vertically cut to be different from the output metal wiring layers 13a and 13b and the Tr connection metal wiring layer 16. The output signal connecting metal wiring layer 33, which is the second layer metal wiring, is formed, and the output signal connecting metal wiring layer 33, the output metal wiring layers 13a and 13b, and the inter-Tr connecting metal wiring layer 16 are formed in the via holes 22. It is electrically connected via.

  A second input metal wiring layer 12 is formed across most of the 12 gate polysilicon layers 9 on the P active region 3 below the Tr interconnection metal wiring layer 16 in plan view, The second input metal wiring layer 12 is on the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 and 9 from the left of the 12 gate polysilicon layers 9, respectively. It is formed extending downward in plan view and is electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) through the contact hole 21. Is done.

  The macro cell M3 of the third embodiment is configured such that the NAND gate G1 having the configuration shown in FIG. 5 includes 12 units (12 Fingers) of basic transistors. Like the macro cell M1 of the first embodiment, the macro cell M3 has a double height cell configuration. Adopted to suppress an increase in the cell area in the lateral direction.

  In the macro cell M3 of the third embodiment, an N well contact region 6 is provided in the lateral direction of the P active region 3, and the contact hole 21 with the well contact portion 14c of the VDD metal wiring layer 14L is formed on the N well contact region 6. The electrical connection is intended.

  Therefore, as in the first and second embodiments, the N well contact region 56 in the macro cell M12 and the region sandwiched between the N well contact region 56 and the P active regions 53a and 53b are also used as the P active region 3. Therefore, the gate width realized by one gate polysilicon layer 9 can be increased.

  Therefore, the macro cell M3 according to the third embodiment has a transistor characteristic with a gate width equivalent to that of the macro cell M1 according to the first embodiment by the 12-unit PMOS transistor (basic transistor) realized by the twelve gate polysilicon layers 9. It can be demonstrated.

  Further, in the macro cell M3, a VDD metal wiring layer 14L is disposed above the P active region 3, and the wiring length of the contact portion (first contact portion) with the P active region 3 is set to be higher than that in the plan view of the P active region 3. Therefore, the number of contact holes 21 with the source region of the PMOS transistor can be increased more than in the first and second embodiments.

  In addition, an inter-Tr connection metal wiring layer 16 is disposed below the P active region 3, and the wiring length of the contact portion (second contact portion) with the P active region 3 is determined from below the plan view of the P active region 3. It is long for the upper part. Therefore, the number of contact holes 21 with the drain region of the PMOS transistor can be increased more than in the first and second embodiments.

  As described above, in the macro cell M3 of the third embodiment, by increasing the wiring lengths of the contact portion of the VDD metal wiring layer 14L and the contact portion of the inter-Tr connection metal wiring layer 16, the source region of the PMOS transistor and Since the number of contact holes 21 formed in each drain region can be increased, there is an effect that the reliability of the macro cell M3 can be improved.

  As a result, the macro cell M3 of the third embodiment can exhibit the effect of improving the cell reliability while improving the usage rate of the P active region 3 for forming the PMOS transistor.

  In addition, although the example of arrangement | positioning of the metal wiring layer 14L for VDD and the metal wiring layer 16 for connecting between Trs which showed the 1st layer metal wiring in the case of comprising the NAND gate of the macrocell M3 of Embodiment 3, these 1st metal wiring layers 16 were shown. Of course, the optimum position of the layer metal wiring is appropriately changed depending on the type of the cell.

<Embodiment 4>
FIG. 8 is a plan view showing a cell structure of a macro cell M4 having a double height cell configuration according to the fourth embodiment of the present invention.

  The macro cell M4 is the same as the macro cell M3 of the third embodiment except for the electrically connected contents of the N well contact region. Hereinafter, the macro cell M4 will be described focusing on differences from the macro cell M3.

  A VDD metal wiring layer 14 </ b> L is formed across the vicinity of the upper end of the P active region 3. Further, the metal wiring layer 14L for VDD is formed on the P active region 3 from among the 12 gate polysilicon layers 9 on the leftmost P active region 3 of the leftmost gate polysilicon layer 9 (2i ) And (2i + 1) th (i = 1 to 5) gate polysilicon layers 9, 9 on the P active region 3, and on the rightmost gate polysilicon layer 9 on the right P active region 3. It extends downward in plan view and is electrically connected to the P active region 3 (corresponding to the source region (one electrode region) of the PMOS transistor) through the contact hole 21.

  Adjacent N well contact region 7 is provided in contact with the left lateral direction of P active region 3. Since the left end region of the P active region 3 corresponds to the source region of the PMOS transistor to which the power VDD is supplied by the VDD metal wiring layer 14L, the adjacent N well contact region 7 supplies the power VDD from the source region (by batting connection). Power supply).

  The macro cell M4 includes the NAND gate G1 having the configuration shown in FIG. 5 including basic transistors for 12 units (Finger number 12), and adopts a double-height cell configuration as in the macro cell M1 of the first embodiment. An increase in cell area is suppressed.

  The macro cell M4 is provided with an adjacent N well contact region 7 adjacent to the lateral direction of the P active region 3, and is sandwiched between the N well contact region 56 and the N well contact region 56 and the P active regions 53a and 53b in the macro cell M12. Since this region can also be used as the P active region 3, the gate width realized by the single gate polysilicon layer 9 can be increased as in the first to third embodiments.

  Further, the adjacent N well contact region 7 is supplied with the power supply VDD by the batting connection by contacting the left end region of the P active region 3 without forming the well contact portion 14c of the metal wiring layer 14L for VDD on the upper side. Therefore, since it is not necessary to form the well contact portion 14c, this portion can be used as a wiring area of the first layer metal wiring in the automatic placement and routing at the time of LSI construction. It is possible to improve the ease.

  Further, in the macro cell M4 of the fourth embodiment, the number of contact holes 21 formed in each of the source region and the drain region of the PMOS transistor can be increased similarly to the macro cell M3 of the third embodiment, so that the reliability of the macro cell M4 is improved. The effect which can aim at is also show | played.

  As a result, the macro cell M4 according to the fourth embodiment exhibits the effect of improving the reliability of the cell and the ease of wiring of the metal wiring while improving the usage rate of the P active region 3 for forming the PMOS transistor. it can.

<Embodiment 5>
FIG. 9 is a plan view showing a cell structure of a macro cell M5 having a double height cell configuration according to the fifth embodiment of the present invention. The macro cell M5 implements a 2-input NAND gate equivalent to the macro cell M1 with a 12-unit basic transistor configuration.

  As shown in FIG. 9, a rectangular N active region 4 is formed extending in the lateral direction in the center of the P well region 1. An N well region 2a is formed above the N active region 4 in plan view, and an N well region 2b is formed selectively in the lateral direction below the plan view. A rectangular P active region 3a is selectively formed in the N well region 2a, and a rectangular P active region 3b is selectively formed in the N well region 2b.

  An N well contact region 6a is selectively formed by extending in the lateral direction above the N well region 2a in plan view (on the side opposite to the N active region 4 in the vertical direction with respect to the P active region 3a). An N well contact region 6b is selectively formed to extend in the horizontal direction below 2b in plan view (on the side opposite to the N active region 4 in the vertical direction with respect to the P active region 3b). Then, a P-well contact region 5 is formed extending in the vertical direction in a region on the left side in the horizontal direction of the N active region 4.

  Twelve gate polysilicon layers 9 formed by vertically running on the N active region 4 and the P active regions 3a and 3b are arranged in the horizontal direction at predetermined intervals. The P well contact region 5 functions as a substrate potential setting region for the NMOS transistor formed in the N active region 4, and the N well contact regions 6a, 6b are the substrate of the PMOS transistor formed in the P active region 3a, 3b. It functions as a potential setting region.

  A VDD metal wiring layer 14 a is formed on the N well contact region 6 a, and the VDD metal wiring layer 14 a and the N well contact region 6 a are electrically connected through a plurality of contact holes 21. Further, the metal wiring layer 14a for VDD is the (2i) th and (2i + 1) th from the left on the P active region 3a on the left side of the leftmost gate polysilicon layer 9 among the twelve gate polysilicon layers 9. (I = 1 to 5) formed on the P active region 3a between the gate polysilicon layers 9 and 9 and on the right P active region 3a of the rightmost gate polysilicon layer 9, respectively. Is electrically connected to the P active region 3a (corresponding to the source region of the PMOS transistor).

  Similarly, a VDD metal wiring layer 14 b is formed on the N well contact region 6 b, and the VDD metal wiring layer 14 b and the N well contact region 6 b are electrically connected through a plurality of contact holes 21. Further, the metal wiring layer 14b for VDD is the (2i) th and (2i + 1) th from the left on the P active region 3b on the left side of the leftmost gate polysilicon layer 9 among the 12 gate polysilicon layers 9. (I = 1-5) formed on the P active region 3b between the gate polysilicon layers 9 and 9 and on the right P active region 3b of the rightmost gate polysilicon layer 9, respectively. And electrically connected to the P active region 3b (corresponding to the source region of the PMOS transistor).

  A Tr interconnection metal wiring layer 16a is formed across most of the twelve gate polysilicon layers 9 on the P active region 3a. Further, the Tr interconnection metal wiring layer 16a includes 12 gates. Of the polysilicon layer 9, it is formed to extend on the P active region 3 between the (2i-1) th and (2i) th (i = 1 to 6) gate polysilicon layers 9, 9 from the left, and is formed as a contact hole. 21 is electrically connected to the P active region 3 (corresponding to the drain region of the PMOS transistor) through 21.

  Similarly, a Tr interconnection metal wiring layer 16b is formed across most of the twelve gate polysilicon layers 9 on the P active region 3b. Further, the Tr interconnection metal wiring layer 16b includes: Of the twelve gate polysilicon layers 9, each is formed to extend on the P active region 3 between the (2i-1) th and (2i) th (i = 1 to 6) gate polysilicon layers 9, 9 from the left. Then, it is electrically connected to the P active region 3 (corresponding to the drain region of the PMOS transistor) through the contact hole 21.

  A second input metal wiring layer 12a is formed across most of the 12 gate polysilicon layers 9 on the P active region 3 below the Tr interconnection metal wiring layer 16a in plan view. The second input metal wiring layer 12a is on the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 and 9 from the left of the 12 gate polysilicon layers 9, respectively. The gate polysilicon layer 9 is formed extending to be electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) through the contact hole 21.

  Similarly, a second input metal wiring layer 12b is formed across most of the twelve gate polysilicon layers 9 on the P active region 3 above the Tr interconnection metal wiring layer 16b in plan view. Further, the second input metal wiring layer 12b includes the (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon layers 9 from the left among the twelve gate polysilicon layers 9. 9 is formed extending over the gate 9 and electrically connected to the corresponding gate polysilicon layer 9 (corresponding to the gate electrodes of the second PMOS transistor and the second NMOS transistor receiving the second input) via the contact holes 21. Is done.

  Then, a second layer metal corresponding to the second input metal wiring layer 82 in FIG. 16 is formed in a layer different from the second input metal wiring layers 12a and 12b by vertically cutting between the second input metal wiring layers 12a and 12b. A second input connection metal wiring layer (not shown) which is a wiring layer is formed, and the second input connection metal wiring layer and the second input metal wiring layers 12a and 12b are respectively connected via via holes corresponding to the via holes 22. Electrically connected.

  A GND metal wiring layer 15 is formed across the central portion of the N active region 4, and a well contact portion 15 c which is a part of the GND metal wiring layer 15 is also formed on the P well contact region 5. Well contact portion 15c and P well contact region 5 are electrically connected through a plurality of contact holes 21.

  Further, the GND metal wiring layer 15 includes (4i + 2) th and (4i + 3) th (i = 0 to 2) gate polysilicon from the left of the 12 gate polysilicon layers 9 on the N active region 4. Formed on the N active region 4 between the layers 9 and 9 so as to extend upward and downward in plan view, and is electrically connected to the N active region 4 (corresponding to the source region of the NMOS transistor) via the contact hole 21. .

  Above the GND metal wiring layer 15 in plan view, an output metal wiring layer 13a is formed across the gate polysilicon layer 9 on the N active region 4, and the output metal wiring layer 13a includes twelve wiring metal layers 13a. Among the gate polysilicon layers 9, the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9 on the left N active region 4 of the leftmost gate polysilicon layer 9. , 9 and on the N active region 4 on the right side of the rightmost gate polysilicon layer 9, extending downward in a plan view, and formed through the contact hole 21, the N active region 4 ( Electrically connected to the drain region of the NMOS transistor).

  Similarly, an output metal wiring layer 13b is formed across the gate polysilicon layer 9 on the N active region 4 below the GND metal wiring layer 15 in plan view, and the output metal wiring layer 13b is The (4i) th and (4i + 1) th (i = 1 to 2) gates from the left on the leftmost N active region 4 of the leftmost gate polysilicon layer 9 among the 12 gate polysilicon layers 9 It is formed on the N active region 4 between the polysilicon layers 9 and 9 and on the N active region 4 on the right side of the rightmost gate polysilicon layer 9 so as to extend upward in a plan view. It is electrically connected to the active region 4 (corresponding to the drain region of the NMOS transistor).

  Then, the Tr interconnection metal wiring layer 16a, the output metal interconnection layers 13a and 13b, and the Tr interconnection metal wiring layer 16b are cut vertically to form the output metal interconnection layers 13a and 13b and the Tr interconnection metal wiring layer. An output signal connection metal wiring layer 33 which is a second layer metal wiring layer is formed in a layer different from 16a and 16b, and the output signal connection metal wiring layer 33, the output metal wiring layers 13a and 13b, and the inter-Tr connection metal. The wiring layers 16 a and 16 b are electrically connected through the via hole 22.

  Above the output metal wiring layer 13a in plan view, a first input metal wiring layer 11a is formed across the 12 gate polysilicon layers 9, and the first input metal wiring layer 11a has 12 gates. Among the polysilicon layers 9, on the leftmost gate polysilicon layer 9, on the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9, 9 from the left, and the rightmost gate A gate polysilicon layer 9 (corresponding to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input) and the corresponding gate polysilicon layer 9 is formed extending over the polysilicon layer 9 through the contact hole 21, respectively. Connected.

  Similarly, a first input metal wiring layer 11b is formed across the 12 gate polysilicon layers 9 below the output metal wiring layer 13b in plan view. Among the twelve gate polysilicon layers 9, on the leftmost gate polysilicon layer 9, on the (4i) th and (4i + 1) th (i = 1 to 2) th gate polysilicon layers 9, 9 from the left, and Each of the gate polysilicon layers 9 is formed to extend on the rightmost gate polysilicon layer 9 via the contact hole 21 (to the gate electrodes of the first PMOS transistor and the first NMOS transistor receiving the first input). Equivalent).

  Then, a second layer metal corresponding to the first input metal wiring layer 81 of FIG. 16 is formed in a layer different from the first input metal wiring layers 11a and 11b by longitudinally cutting between the first input metal wiring layers 11a and 11b. A first input connection metal wiring layer (not shown) that is a wiring is formed, and the first input connection metal wiring layer and the first input metal wiring layers 11a and 11b are electrically connected via via holes corresponding to the via holes 22, respectively. Connected to.

  The macro cell M5 of the first embodiment having such a configuration is divided into a GND wiring (GND metal wiring layer 15) at the center of the cell in plan view and two power supply wirings (VDD metal wiring layer) divided upward and downward in plan view. 14a, 14b), the NMOS transistor forming active region is constituted only by the N active region 4, and the PMOS transistor forming first active region (P active region 3a) is formed above the N active region 4 in plan view. A double-height cell configuration in which a second active region (P active region 3b) for forming a PMOS transistor is disposed below the N active region 4 in a plan view and suppresses an increase in the cell area in the lateral direction. is doing.

  In the macro cell M5, a P well contact region 5 is provided in the lateral direction of the N active region 4, and an electrical connection is made on the P well contact region 5 to the well contact portion 15c of the GND metal wiring layer 15 by the contact hole 21. I am trying.

  For this reason, it is not necessary to form the N active region 4 for forming the NMOS transistor by dividing it vertically in the plan view like the N active regions 54a and 54b in the macro cell M13 shown in FIG. 16 by the P well contact region 5. , Can be formed as one region.

  As a result, the P well contact region 55 and the region sandwiched between the P well contact region 55 and the N active regions 54a and 54b in the macro cell M13 shown in FIG. The gate width of one unit of NMOS transistor realized by the silicon layer 9 can be made larger than the gate width of one unit of NMOS transistor of the macro cell M13 of FIG.

  Therefore, in the macro cell M5 of the fifth embodiment, the total gate width by the 12-unit NMOS transistor (basic transistor) is substantially equal to the total gate width by the 16-unit PMOS transistor in the macro cell M13 shown in FIG. As a result, the operational characteristics equivalent to those of the macro cell M13 can be exhibited.

  As a result, when the operating characteristics of the macro cell M5 are realized at the same level as the macro cell M13, the lateral width of the N active region 4 can be made narrower than the lateral widths of the N active regions 54a and 54b of the macro cell M13 shown in FIG. There is an effect that the usage rate of the N active region 4 for forming the NMOS transistor can be improved.

  The macro cell M5 of the fifth embodiment is realized by a cell structure in which the conductivity type is reversed on the basis of the macro cell M1 of the first embodiment. Similarly, the macro cell M2 of the second to fourth embodiments. It is also possible to realize a cell structure in which the conductivity type is reversed on the basis of M4.

<Embodiment 6>
FIG. 10 is a plan view showing a cell structure of a macro cell M6 having a double height cell configuration according to the sixth embodiment of the present invention. The macro cell M6 realizes a two-input AND gate obtained by outputting the output of the two-input NAND gate of the macro cell M5 through an inverter with a basic transistor configuration of 13 units including the basic transistor constituting the inverter. Hereinafter, the configuration of the macro cell M6 will be described focusing on differences from the macro cell M5.

  In the upper layer portion of the semiconductor substrate 10 (see FIGS. 2 and 3), a P active region 23a is selectively formed in the left region in the N well region 2a, and the P active region is formed in the left region in the N well region 2b. 23b is selectively formed.

  In the upper layer portion of the semiconductor substrate 10, an N active region 24 is selectively formed in the left lateral direction of the P well contact region 5 in the P well region 1. That is, the P well contact region 5 is disposed between the N active region 4 and the N active region 24.

  In addition to the twelve gate polysilicon layers 9, a thirteenth gate polysilicon layer 29 is further disposed vertically across the P active region 23a, the N active region 24, and the P active region 23b.

  The VDD metal wiring layer 14a is further formed on the P active region 23a on the right side of the gate polysilicon layer 29, and is formed through the contact hole 21 in the P active region 23a (in the source region of the third PMOS transistor). Equivalent).

  Similarly, the VDD metal wiring layer 14 b is formed to extend further on the P active region 23 b on the right side of the gate polysilicon layer 29, and the P active region 23 b (third PMOS transistor) is connected via the contact hole 21. Electrically connected to the source region).

  The inter-Tr connection metal wiring layer 16a is further formed on the gate polysilicon layer 29, and is electrically connected to the gate polysilicon layer 29 (corresponding to the gate electrode of the third PMOS transistor) via the contact hole 21. Connected to.

  Similarly, the Tr interconnection metal wiring layer 16b is formed to extend further on the gate polysilicon layer 29, and corresponds to the gate polysilicon layer 29 (corresponding to the gate electrode of the third PMOS transistor) via the contact hole 21. ) And electrically connected.

  The output metal wiring layer 17a is formed on the left P active region 23a of the gate polysilicon layer 29, and is electrically connected to the P active region 23a (corresponding to the drain region of the third PMOS transistor) through the contact hole 21. Connected to.

  Similarly, the output metal wiring layer 17b is formed on the left P active region 23b of the gate polysilicon layer 29, and corresponds to the P active region 23b (corresponding to the drain region of the third PMOS transistor) via the contact hole 21. ) Is electrically connected.

  An NMOS output metal wiring layer (not shown) is formed on the left N active region 24 of the gate polysilicon layer 29 above and below the GND metal wiring layer 15 in plan view, and is a contact hole (not shown). ) To the N active region 24 (corresponding to the drain region of the third NMOS transistor).

  Then, the output metal wiring layers 17a and 17b and the NMOS output metal wiring layer are vertically cut, and the output signal connecting metal wiring layer 34 which is the second layer metal wiring is formed in a layer different from the output metal wiring layers 17a and 11b. The output signal connecting metal wiring layer 34, the output metal wiring layers 17a and 17b, and the NMOS output metal wiring layer are electrically connected through the via holes 22, respectively.

  The GND metal wiring layer 15 is further formed on the N active region 24 on the right side of the gate polysilicon layer 29 so as to extend upward and downward in plan view, and the N active region 24 (third Electrically connected to the source region of the NMOS transistor).

  FIG. 11 is a circuit diagram showing an AND gate realized by the macro cell M6. As shown in the figure, the AND gate of the macro cell M6 receives an input signal A and an input signal B, receives a NAND gate G1 that outputs the NAND operation result as an output signal YB, and an output signal YB of the NAND gate G1, And an inverter G2 that outputs an output signal Y.

  FIG. 12 is a circuit diagram showing a transistor configuration for realizing the inverter G2. As shown in the figure, the inverter G2 is realized by a PMOS transistor Q5 (third PMOS transistor) and an NMOS transistor Q6 (third NMOS transistor).

  The source of the PMOS transistor Q5 is commonly connected to the power supply VDD (via the VDD metal wiring layers 14a and 14b), connected to the drain of the PMOS transistor Q5 and the drain of the NMOS transistor Q6, and the source of the NMOS transistor Q6 is at the GND level. Connected (via the GND metal wiring layer 15). The gates of the PMOS transistor Q5 and the NMOS transistor Q6 receive the output signal YB (via the inter-Tr connection metal wiring layers 16a and 16b), and the output signal connection metal wiring from the drain of the PMOS transistor Q5 (NMOS transistor Q6). The signal obtained (via layer 34) becomes the output signal Y.

  Like the macro cell M5 of the fifth embodiment, the macro cell M6 of the sixth embodiment having such a configuration adopts a double height cell configuration and suppresses an increase in the cell area in the lateral direction.

  In the macro cell M6, a P well contact region 5 is provided in the lateral direction of the N active region 4, and an electrical connection is made on the P well contact region 5 to the well contact portion 15c of the GND metal wiring layer 15 through the contact hole 21. I am trying. Accordingly, the macro cell M6 of the sixth embodiment can reduce the lateral width of the N active region 4 in the same manner as the macro cell M5 of the fifth embodiment, so that the usage rate of the N active region 4 for forming the NMOS transistor can be improved. There is an effect that can be achieved.

  Further, in the macro cell M6 of the sixth embodiment, a P well contact region 5 is provided between the N active region 4 in the NMOS transistor forming region for the NAND gate G1 and the N active region 24 in the NMOS transistor forming region for the inverter G2. Thus, an AND gate having a larger number of necessary transistors than the NAND gate can be realized with high usage efficiency while effectively suppressing an increase in cell area.

  The macro cell M6 of the sixth embodiment has a configuration in which an inverter formation region is added to the macro cell M5 of the fifth embodiment, but the inverter formation region is added to the macro cells M1 to M4 of the first to fourth embodiments. Of course, the added configuration can be realized.

<Embodiment 7>
FIG. 13 is a plan view showing a cell structure of a macro cell M7 having a double height cell configuration according to the seventh embodiment of the present invention.

  The macro cell M7 is the same as the macro cell M1 of the first embodiment except for the shape of the gate polysilicon layer 9. Hereinafter, the macro cell M7 will be described focusing on differences from the macro cell M1. In FIG. 13, in order to clearly show the shape of the gate polysilicon layer 9 which is a feature of the seventh embodiment, the gate polysilicon layer 9 is hatched to form the first input metal wiring layer 11a and the second input metal layer 11a. The illustration of the metal wiring layer 12a is omitted, and the Tr interconnection metal wiring layers 16a and 16b, the first input metal wiring layer 11b, and the second input metal wiring layer 12b are not hatched.

  As shown in the figure, among the 12 gate polysilicon layers 9, two connections are made between the (2i) th and (2i + 1) th (i = 1 to 5) gate polysilicon layers 9, 9 from the left. By providing the portions 9c and 9d, a total of five ring-shaped polysilicon ring portions 9R are formed. That is, the macro cell M7 of the seventh embodiment includes a gate electrode of a PMOS transistor that is a pair of basic transistors having the (2i) th and (2i + 1) th (i = 1 to 5) gate polysilicon layers 9 and 9 from the left. (Gate polysilicon layer 9) is formed in one ring shape. Other configurations are the same as those of the macro cell M1 of the first embodiment.

  In the macro cell M7 of the seventh embodiment having such a configuration, in addition to the effect of the macro cell M1 of the first embodiment, signal propagation at the ring-shaped gate electrode is achieved by forming the gate electrodes of the pair of PMOS transistors into a ring shape. There is an effect that the time can be advanced and the operation speed of the cell can be improved.

  The macro cell M7 of the seventh embodiment has a structure having the polysilicon ring portion 9R based on the structure of the first embodiment, but the polysilicon ring portion 9R based on the structures of the other embodiments 2 to 6. Of course, a structure having the above can be realized.

<Eighth embodiment>
FIG. 14 is a plan view showing the internal structure of a semiconductor integrated circuit 8 according to the eighth embodiment of the present invention. As shown in the figure, in the P well region 1 formed in the upper layer portion of the semiconductor substrate 10 (see FIGS. 2 and 3), the macro cell M3 of the third embodiment (see FIG. 7 for the detailed structure), the embodiment 5 macro cell M5 (refer to FIG. 9 for the detailed structure) and macro cell M11 (refer to FIG. 17 for the detailed structure).

  Then, the GND metal wiring layer 15a of the macro cell M3 and the GND metal wiring layer 15 of the macro cell M5 are commonly connected, and the VDD metal wiring layer 14L of the macro cell M3 and the VDD metal wiring layer 64 of the macro cell M11 are commonly connected. The GND metal wiring layer 15b of the macro cell M3 and the GND metal wiring layer 65 of the macro cell M11 are connected in common.

  Since the macro cells M3 and M5 have a double-height cell structure, the macro cells M3 and M5 have a first well contact region (N well contact region 6, P well contact region 5) on the central left side, The first distance between the third well contact regions (between the P well contact regions 5a and 5b and between the N well contact regions 6a and 6b) is the first distance arranged at the upper and lower ends in the vertical direction of the macro cell M11 having a single height cell structure. 4, the second distance between the fifth well contact regions (between the VDD metal wiring layer 64 and the GND metal wiring layer 65) is also long.

  As described above, in the semiconductor integrated circuit 8 according to the eighth embodiment, the P-type double-height cell structure macro cell M3 (first partial circuit portion) arranged around the PMOS transistor formation region and the NMOS transistor formation region are mainly used. By using a mixed macro cell M5 (first partial circuit portion) having an N-type double height cell structure and a macro cell M11 (second partial circuit portion) having a single height cell structure, the degree of freedom in design can be increased. It is possible to perform more advanced logical operations while increasing the level.

  The semiconductor integrated circuit 8 according to the eighth embodiment can be designed without any difference from the conventional design method even if a plurality of types of macro cells M3, M5, and M11 are combined by automatic placement and wiring (P & R). .

<Others>
In each of the macrocells M1 to M7 shown in the first to seventh embodiments, the N well contact region 6 is disposed in the vicinity of the left side in the lateral direction of the P active region 3, or the P well contact region 5 is disposed in the N active region. 4, the N-well contact region 6 or the P-well contact region 5 is arranged in the right-side vicinity region or the right-and-left both-side region of the P active region 3 or the N active region 4. Configuration is also conceivable.

  In addition, as the macrocells M1 to M7 shown in the first to seventh embodiments, a 16-times power NAND gate and an AND gate have been described as examples. However, the present invention has a macrocell structure such as a flip-flop, a selector, and the like. Obviously, it can be applied to all logic circuits.

  1 P well region, 2, 2a, 2b N well region, 3, 3LP active region, 4, 4a, 4b N active region, 5a, 5b P well contact region, 6 N well contact region, 7 adjacent N well contact region , 8 Semiconductor integrated circuit, 9, 29 Gate polysilicon layer, 10 Semiconductor substrate, 11, 11a, 11b First input metal wiring layer, 12, 12a, 12b Second input metal wiring layer, 13a, 13b Output metal Wiring layer, 14, 14a, 14b, 14L VDD metal wiring layer, 15, 15a, 15b GND metal wiring layer, 16, 16a, 16b Tr inter-connection metal wiring layer, 21 contact holes, 22 via holes, 23a, 23b P active region, 24 N active region, 33, 34 Metal wiring layer for output signal connection, M1-M7 Mac Cell.

Claims (1)

A first active region of a first conductivity type having a rectangular shape in plan view, which is formed in the upper layer portion of the semiconductor substrate and defined by the first and second directions, is provided in the first active region. A plurality of first conductivity type basic transistors whose predetermined operating characteristics are defined by a first length in one direction are formed along the second direction;
Second and third active regions of a second conductivity type formed in the upper layer portion of the semiconductor substrate and disposed respectively on one side and the other side in the first direction with respect to the first active region;
A substrate potential of a second conductivity type formed in the upper layer portion of the semiconductor substrate in the vicinity of the first active region on the predetermined side in the second direction and extending in the first direction. A setting region, and substrate potentials of the plurality of basic transistors are set by a potential applied to the substrate potential setting region.
Semiconductor integrated circuit.

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