JPH07161944A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid the decrease in the degree of integration of a semiconductor integrated circuit device and to increase the connection rate of a logic gate constituted of basic cells by preventing the increase in an area occupied by the basic cells. CONSTITUTION:A basic cell 1 is provided with a PMOS transistor T1, T2 and an NMOS transistor T3, T4. The transistor T1, T2 is constituted of three P-type semiconductor regions 2-4 and gate electrodes 8, 9 which are placed between the P-type semiconductor regions. The transistor T3, T4 is constituted of three N-type semiconductor regions 5-7 and gate electrode 8, 9 which are placed between the N-type semiconductor regions. The transistors T1, T2 and T3, T4 face each other with contact formation regions 8A, 9A being placed between. The contact formation regions 8A, 9A are so formed that they may be adjacent to other contact formation regions in the arrangement direction of the two transistors and a plurality of contacts may be located.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which a large number of basic cells composed of CMOS transistors are formed.

In recent years, CMOS semiconductor integrated circuits are strongly required to have high integration in terms of high-speed operation and reduction in manufacturing cost. For that purpose, it is necessary to reduce the size of the gate formed by using one or more basic cells and to arrange the gate electrode capable of improving the wiring efficiency.

[0003]

2. Description of the Related Art FIG. 6 shows a layout of a basic cell in a conventional CMOS semiconductor integrated circuit.
The basic cell 21 includes three P-type semiconductor regions 22, 23, 24 formed at predetermined intervals and three N-type semiconductor regions 25, 26, 27 formed at predetermined intervals. Each P-type semiconductor region and each N-type semiconductor region are arranged to face each other. Integrated gate electrodes 28 and 29 are formed above each pair of P-type and N-type semiconductor regions. P-type regions 22 and 23 and gate electrode 28
Form a PMOS transistor T5, and the P-type regions 23 and 24 and the gate electrode 29 form a PMOS transistor T6. Therefore, the P-type regions 22, 2
4 is the source (or drain) of the transistors T5 and T6
Therefore, the P-type region 23 becomes the drain (or source) of the transistors T5 and T6. In addition, the N-type regions 25 and 26
And the gate electrode 28 form an NMOS transistor T7, and the N-type regions 26 and 27 and the gate electrode 29 form an NMOS transistor T8. Therefore, the N-type regions 25 and 27 become sources (or drains) of the transistors T7 and T8, and the N-type region 26 becomes drains (or sources) of the transistors T7 and T8.

Contact formation regions 28A and 29A are formed in the gate electrodes 28 and 29 between the transistors T5 and T7 and between the transistors T6 and T8. The contact forming regions 28A and 29A are opposed to each other with an interval corresponding to the width of the region 23 (length in the vertical direction in FIG. 6). Two contacts 28a and 28b and two contacts 29a and 29b can be formed in the contact formation regions 28A and 29A, respectively. FIG. 7 shows an equivalent circuit diagram of the basic cell 21.

In the basic cell 21, for example, the contacts 28a and 29a are connected by the wiring 30 of the first layer of aluminum, and any one of the P-type regions 22 to 24 is connected to one of the N-type regions 25 to 27. Connect to one. In this case, the wiring of the first layer of aluminum causes P
In order to connect the contact 24a of the type region 24 to the contact 27a of the N-type region 27, the wiring 31 extends from the region of the basic cell 21 to the region of another basic cell adjacent thereto. Even when the P-type regions 22 and 23 are connected to the N-type regions 25 and 26 opposed to the P-type regions 22 and 23 by the wiring of the first layer of aluminum, the wirings protrude from the area of the basic cell 21. Further, in order to prevent the wiring from protruding from the area of the basic cell 21, the wirings of the first and second layers of aluminum are required. For example, the wirings 32 and 33 of the aluminum first layer are formed on the P-type region 23 and the N-type region 26,
One ends thereof are connected to the contacts 23a and 26a, respectively. A wiring 34 is formed on the second aluminum layer, and both ends thereof are connected to the wirings 32 and 33 by contacts 23b and 26b, respectively.

[0006]

As described above, when the conventional basic cell 21 is used to form a gate having various logics, since the contact forming regions 28A and 29A are provided separately from each other, the gate is formed. When the electrodes 28 and 29 are connected, the wiring in the gate may protrude from the area of the basic cell. Moreover, if the wiring in the gate is prevented from protruding, the wiring channel on the basic cell 21 will be used more than necessary.
Therefore, the internal wiring of the gate or the wiring for connecting the gate to another gate cannot be connected. Therefore, in order to prevent the internal wiring of the gate from overhanging the area of other basic cells adjacent to it, or to prevent unconnection, widen the interval between the basic cells and increase the area occupied by the basic cells. , New wiring channels must be secured. As a result, there is a problem that the degree of integration of the integrated circuit device decreases.

The present invention has been made to solve the above problems, and an object of the present invention is to prevent an increase in the area occupied by a basic cell and prevent a decrease in the degree of integration.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of improving the connection rate of logic gates composed of basic cells.

[0008]

To achieve the above object, according to the present invention, three P-type semiconductor regions are formed at predetermined intervals, and a gate electrode is formed above each P-type semiconductor region. A pair of PMOS transistors and a pair of NMOSs in which three N-type semiconductor regions are formed at a predetermined interval and a gate electrode is formed above each N-type semiconductor region.
A semiconductor integrated circuit device provided with a large number of basic cells in which a pair of PMOS transistors and a pair of NMOS transistors are opposed to each other with a contact formation region where a contact of each gate electrode is formed interposed therebetween. In each of the two arrangement directions of the transistors, each contact formation region was formed adjacent to another contact formation region, and each contact formation region was formed so that a plurality of contacts could be arranged.

[0009]

Therefore, according to the present invention, the contact formation region is formed adjacent to the other contact formation regions in the two arrangement directions of the MOS transistors in the basic cell. Therefore, the region occupying the metal wiring layer is minimized when connecting the gate electrodes of the adjacent MOS transistors, and the connection rate at the time of routing the wirings of the gates having various logics can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention is shown in FIG.
It will be described with reference to FIG. FIG. 1 shows a basic cell in a CMOS semiconductor integrated circuit of this embodiment.
The basic cell 1 is provided with three P-type semiconductor regions 2, 3, 4 formed at predetermined intervals and three N-type semiconductor regions 5, 6, 7 formed at predetermined intervals.
Each P-type semiconductor region and each N-type semiconductor region are arranged to face each other. Integrated gate electrodes 8 and 9 are formed above each pair of P-type and N-type semiconductor regions. The P-type regions 2, 3 and the gate electrode 8 form a PMOS transistor T1, and the P-type regions 3, 4 and the gate electrode 9 form a PMOS transistor T2. Therefore, the P-type regions 2 and 4 become sources (or drains) of the transistors T1 and T2, and the P-type region 3 becomes the transistor T.
It becomes the drain (or source) of 1, T2. Further, the N-type regions 5, 6 and the gate electrode 8 form an NMOS transistor T3, and the N-type regions 6, 7 and the gate electrode 9 form an NMOS transistor T4. Therefore, the N-type regions 5 and 7 become the sources (or drains) of the transistors T3 and T4, and the N-type region 6 becomes the transistor T.
It becomes the drain (or source) of T3.

Contact formation regions 8A and 9A are formed in the gate electrodes 8 and 9 between the transistors T1 and T3 and between the transistors T2 and T4. In the contact forming regions 8A and 9A, a protruding portion that extends inward, that is, a protruding portion that extends inward and a protruding portion that extends outward are formed, respectively. 4 in each contact formation region 8A, 9A
One contact 8a, 8b, 8c, 8d and four contacts 9a, 9b, 9c, 9d can be formed respectively. The contact formation region 8 is formed by the protrusion extending inward.
A and 9A are adjacent to other contact formation regions in the two arrangement directions of the MOS transistors. FIG. 2 shows an equivalent circuit diagram of the basic cell 1.

Therefore, in the basic cell 1, for example, the contact 2a of the P-type region 2 and the contact 5a of the N-type region 5 are connected. At this time, the gate electrode cannot be drawn from the contacts 8b and 8c in the contact formation region 8A, but the gate electrode can be drawn from the contacts 8a and 8d. In addition, the gate electrode 8,
When connecting 9 to each other, if it is desired to leave many wiring channels in the arrangement direction of PMOS (or NMOS) transistors (vertical direction in FIG. 1), the contacts 8c,
9a or the contacts 8a and 9c may be connected. Furthermore, if it is desired to leave a large number of wiring channels in the arrangement direction of the PMOS and NMOS transistors (the horizontal direction in FIG. 1), the contacts 8a and 9a may be connected.

Therefore, the contact forming regions 8A and 9A are connected to each other, and any one of the P type regions 2 to 4 is connected to the N type region 5.
It shall be connected to any one of ~ 7. in this case,
The contacts 8a and 9a are connected by a wiring of a first layer of aluminum. In order to connect any one of the contacts 2a to 4a and any one of the contacts 5a to 7a with the wiring of the first layer of aluminum, wiring may be performed so as to bypass the contacts 8a and 9a in the region of the basic cell 1. Good.

As described above, in this embodiment, the gate electrodes 8 and
The degree of freedom of connection with the contact 9 is increased. Also,
When connecting the gate electrodes of adjacent transistors, the area occupied by the wiring is minimized. Therefore, it is possible to suppress an increase in the area occupied by the basic cell 1 and prevent a decrease in the degree of integration, and it is possible to improve the connection rate of the logic gate configured by the basic cell 1.

FIGS. 3 and 4 show a basic cell 10 according to another embodiment. The gate electrodes 11 and 1 are provided above the P-type regions 2 and 3 and between 3 and 4 of the basic cell 10.
3 is formed, and the gate electrodes 12 and 14 are formed above the N-type regions 5 and 6 and between the N-type regions 6 and 7. The P-type regions 2, 3 and the gate electrode 11 form a PMOS transistor T1, and the P-type regions 3, 4 and the gate electrode 13 form a PMOS transistor T2. Therefore, the P-type regions 2 and 4 become sources (or drains) of the transistors T1 and T2, and the P-type region 3 becomes the transistor T.
It becomes the drain (or source) of 1, T2. Further, the N-type regions 5 and 6 and the gate electrode 12 form an NMOS transistor T3, and the N-type regions 6 and 7 and the gate electrode 1 are formed.
4 forms an NMOS transistor T4.
Therefore, the N-type regions 5 and 7 become sources (or drains) of the transistors T3 and T4, and the N-type region 6 becomes drains (or source) of the transistors T3 and T4.

Between the transistors T1 and T3 and between the transistors T2 and T4, the gate electrodes 11, 12, 1 are provided.
Contact formation regions 11A, 12A, 13
A and 14A are formed respectively. Each of the contact formation regions 11A, 12A, 13A, 14A has a rectangular shape extending in the arrangement direction of the PMOS (or NMOS) transistors, and the contact formation regions 11A, 12A, 13A,
14A has two contacts 11a, 11b,
12a, 12b, 13a, 13b, 14a, 14b can be formed. Contact forming regions 11A, 12A, 13
A and 14A are adjacent to other contact formation regions in the two arrangement directions of the MOS transistors. FIG. 4 shows an equivalent circuit diagram of the basic cell 10.

The basic cell 10 also has the same operation and effect as the basic cell 1. FIG. 5 shows a basic cell 15 of still another embodiment.
Contact formation regions 8B of the integrated gate electrodes 8 and 9,
9B is different from the basic cell 1 in that the protrusions extending outward from the contact formation regions 8A and 9A are omitted.
The configuration is different. Other configurations are the same as those of the basic cell 1.

[0018]

As described in detail above, according to the present invention,
There is an excellent effect that it is possible to improve the connection rate of the logic gate configured by the basic cells while suppressing the increase of the area occupied by the basic cells and preventing the deterioration of the degree of integration.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a basic cell according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the basic cell of FIG.

FIG. 3 is a layout diagram showing a basic cell of another embodiment.

FIG. 4 is an equivalent circuit diagram of the basic cell of FIG.

FIG. 5 is a layout diagram showing a basic cell of still another embodiment.

FIG. 6 is a layout diagram showing a basic cell of a conventional example.

7 is an equivalent circuit diagram of the basic cell of FIG.

[Explanation of symbols]

 1 basic cell 2,3,4 P-type semiconductor region 5,6,7 N-type semiconductor region 8,9 gate electrode 8A, 9A contact formation region T1, T2 PMOS transistor T3, T4 NMOS transistor

Claims (1)

[Claims] 1. Three P-type semiconductor regions (2, 3, 4) are formed at predetermined intervals, and each P-type semiconductor region (2, 3, 4) is formed.
A pair of PMOS transistors (T1, T2) having gate electrodes (8, 9) formed above them between three and four) and three N-type semiconductor regions (5, 6, 7) are formed at a predetermined interval. And a pair of NMOS transistors (T3, T4) each having a gate electrode (8, 9) formed above each N-type semiconductor region (5, 6, 7), and each gate electrode (8, 9).
Contact formation region (8A,
9A) with the pair of PMOS transistors (T
1, T2) and a pair of NMOS transistors (T3, T
In a semiconductor integrated circuit device provided with a large number of basic cells (1) facing each other, the contact formation regions (8) are arranged in the two arrangement directions of the MOS transistors in the basic cell (1).
A, 9A) is formed adjacent to other contact formation regions, and each contact formation region (8A, 9A) is formed so that a plurality of contacts can be arranged.