JP4447297B2 - Gate array semiconductor device - Google Patents

Description

  The present invention relates to a gate array semiconductor device, and more particularly to a gate array semiconductor device having a basic cell composed of a plurality of cells.

  Semi-custom semiconductor devices are widely used in semiconductor devices represented by large-scale integrated circuits (LSIs). This semi-custom semiconductor device is a semiconductor device that is completed by combining a design part provided by a semiconductor manufacturer and a design part provided by a customer (customer), and is a gate array type semiconductor device (hereinafter referred to as a gate array semiconductor). And a standard cell semiconductor device (hereinafter referred to as a standard cell semiconductor device).

  In the gate array semiconductor device, a semi-finished product in which a plurality of basic cells including transistor gates are arranged on a semiconductor chip in advance on the semiconductor manufacturer side, and a wiring pattern based on a necessary logic is formed on the basic cell on the customer side. A semiconductor device is completed. On the other hand, in the standard cell semiconductor device, a semi-finished product in which standard basic cells in which desired logic gates are combined in advance is arranged on the semiconductor manufacturer side is combined with the basic cells on the customer side based on the required logic. Is to complete. Gate array semiconductor devices are preferred because they have the advantage of a shorter development period compared to standard cell semiconductor devices. However, gate array semiconductor devices are inferior in terms of integration due to the generation of basic cells that are not used. Even in an array semiconductor device, it is required to improve the degree of integration by reducing the size of the basic cell as much as possible. In order to reduce the size of the basic cell, it is necessary to refine the process.

  Here, in general, various signal integrity problems due to process miniaturization have become apparent in semiconductor devices. One of them is electromigration that causes deterioration of metal wiring and contact holes. Deterioration of metal wiring and contact holes due to electromigration depends on the amount of current flowing in the wiring, and therefore it is necessary to enhance resistance to electromigration for output terminals having a large current driving capability. For this purpose, it is necessary to increase the cross-sectional area of the wiring through which current flows. Specifically, for metal wiring, it is necessary to increase the wiring width, while for contact holes, it is necessary to form a plurality of contact holes when forming the wiring.

  In addition, the resistance to electromigration is greatly influenced by the layout of primitive blocks. For this reason, the layout of the primitive block is required to be resistant to electromigration and have high reliability.

  As described above, a gate array semiconductor device configured to reduce the size of the basic cell in order to improve the defect of the gate array semiconductor device that is less integrated than the standard cell semiconductor device is disclosed in, for example, Patent Document 1. Is disclosed. In the gate array semiconductor device, as shown in FIG. 5, basic cells 50 are formed in an N well 51 disposed in an upper portion along a vertical direction (up and down direction) along a horizontal direction (left and right direction). Three substantially rectangular P-type semiconductor regions 52A to 52C and three substantially rectangular N-type semiconductor regions formed along the horizontal direction in the P well 53 disposed in the lower portion along the vertical direction 54A to 54C, a common first gate 55 extending along the vertical direction between the P-type semiconductor regions 52A and 52B and between the N-type semiconductor regions 54C and 54B, and the P-type semiconductor region 52B , 52C and the N-type semiconductor regions 54B and 54A, the second gate 56 extending along the vertical direction and the N well 51 and the P well 53 are formed at diagonal positions. N-well contact 57 and And a well contact 58.. Here, as will be described later, the P-type semiconductor regions 52A and 52C constitute the drain regions of the pair of PMOS transistors Q1 and Q2, and the P-type semiconductor region 52B constitutes the common source region of Q1 and Q2. The N-type semiconductor regions 54A and 54C constitute drain regions of the pair of NMOS transistors Q3 and Q4, and the N-type semiconductor region 54B constitutes a common source region of Q3 and Q4.

  The P-type semiconductor region 52A has contact holes 52a and 52b from the top along the vertical direction. Similarly, the P-type semiconductor region 52B has contact holes 52c to 52f. Similarly, the P-type semiconductor region 52C has contact holes. 52g to 52i are respectively provided. On the other hand, the N-type semiconductor region 54A has contact holes 54a and 54b from the bottom along the vertical direction, the N-type semiconductor region 54B has contact holes 54c to 54f, and the N-type semiconductor region 54C has the same structure. Contact holes 54g to 54i are respectively provided. The first gate 55 is provided with contact holes 55a and 55b from above along the vertical direction, and the second gate 56 is provided with contact holes 56a and 56b from below along the vertical direction. The first and second gates 55 and 56 are arranged symmetrically with respect to the central portion of the basic cell 50. The N well contact 57 is provided with a contact hole 57a, and the P well contact 58 is provided with a contact hole 58a.

Further, a VDD (power supply) wiring 59 connected to the N well contact 57 via the contact hole 57a is disposed along the horizontal direction, while a GND (grounding) connected to the P well contact 58 via the contact hole 58a. ) The wiring 60 is arranged in the horizontal direction. In addition, seven wiring tracks 61 to 67 are connected to the P-type semiconductor regions 52A to 52C, the N-type semiconductor regions 54A to 54C, and the first and second gates 55 and 56 through the corresponding contact holes, respectively. Arranged along the horizontal direction.
With the above configuration, in the basic cell 50, a pair of PMOS transistors Q1 and Q2 are formed in the N well 51, and a pair of NMOS transistors Q3 and Q4 are formed in the P well 53. Q1 and Q3 constitute a common first gate 55, and Q3 and Q4 constitute a common second gate 56 to form a complementary metal oxide semiconductor (CMOS) circuit, respectively.

  According to the gate array semiconductor device having the basic cell 50 having such a configuration, even if the horizontal wiring tracks exclude the VDD wiring 59 and the GND wiring 60, they can be configured by only seven (61 to 67). Further, since only three wiring tracks (not shown) in the vertical direction can be formed, the size of the basic cell 50 can be reduced.

  Next, with respect to the gate array semiconductor device having the basic cell 50 shown in FIG. 5, in order to increase the cross-sectional area of the wiring through which the current flows in order to enhance the resistance to electromigration as described above, FIG. 6 shows an example in which VDD wiring 59 and GND wiring 60 are formed in the source region 52B of the pair of PMOS transistors Q1 and Q2 and the source region 54B of the pair of NMOS transistors Q3 and Q4, respectively, which are large output terminals. To explain. In order to form the VDD wiring 59 and the GND wiring 60 in the same manner for the semiconductor device, the VDD wiring 59 is formed in the N well contact 57 of the basic cell 50 through the contact hole 57a as shown in FIG. These are formed through two contact holes 52c and 52d provided in a direction perpendicular to the P-type semiconductor region 52B serving as the source region. Similarly, the GND wiring 60 is formed in the P well contact 58 of the basic cell 50 through the contact hole 58a, and at the same time, two contact holes 54c provided in a direction perpendicular to the N-type semiconductor region 54B serving as the source region, 54d will be formed. According to such a configuration, since the VDD wiring 59 and the GND wiring 60 are formed by increasing the number of contact holes for each source region, the wiring through which current flows to the output terminal having a large current driving capability is cut off. The area can be increased and the resistance to electromigration can be enhanced.

  Further, in the gate array semiconductor device, in order to improve the arrangement efficiency of the basic cell, the power supply wiring is divided and arranged so as to sandwich the signal wiring on the basic cell. 2 is disclosed. As shown in FIG. 7, the semiconductor device has a configuration in which a plurality of basic cells arranged in a matrix on a semiconductor substrate are interconnected with a signal wiring 101 or a power wiring 102, etc., and the power wiring 102 is arranged on the basic cell. The first power supply wiring 102A and the second power supply wiring 102B are divided into two so as to sandwich the signal wiring 101. Reference numeral 103 denotes an N-type diffusion region (first diffusion region), 104 denotes a P-type diffusion region (second diffusion region), 105 denotes a gate electrode, 106 denotes a gate connection region, and 107 denotes a substrate electrode.

Also, in the gate array semiconductor device, in order to improve the wiring efficiency, the power line is divided into a plurality of parts, one of which is used for power supply and the rest is used for power supply or signal transmission. This is disclosed in, for example, Patent Document 3. In the gate array semiconductor device, as shown in FIG. 8, a power supply line 113 and a signal line 114 are provided on a PMOS group 112 disposed on an N well 111 of a P-type semiconductor substrate 110 with an insulating layer interposed therebetween. On the other hand, the ground line 116 and the signal line 117 are provided on the NMOS group 115 arranged on the P-type substrate 110 with an insulating layer interposed. As a result, the signal lines 114 and 117 are used for supplying a clock signal and the N well 111 is divided into, for example, a 5V power supply and a 3V power supply, and 5V is supplied via the power supply line 113 and the signal line 114 is supplied. By supplying 3V through the gate array semiconductor device, two kinds of power supply voltage mixed gate array semiconductor devices can be easily configured.
US Patent No. 5923059 JP-A-7-58301 JP 11-31803 A

However, the conventional gate array semiconductor device described in Patent Document 1 has a problem that the degree of integration cannot be improved and the resistance to electromigration cannot be enhanced.
That is, in the semiconductor device described in Patent Document 1, as described with reference to FIG. 5, since the size of the basic cell 50 can be reduced, the degree of integration can be improved. On the other hand, as described with reference to FIG. 6, when the semiconductor device is intended to enhance the resistance to electromigration, the P-type semiconductor region 52 </ b> B and the N-type semiconductor region 54 </ b> B serving as the source regions are each in the vertical direction. Since the VDD wiring 59 and the GND wiring 60 are formed by using the two contact holes 52c, 52d and 54c, 54d, respectively, an extra area is occupied in the vertical direction. Therefore, the arrangement area of the two wiring tracks 61 and 67 out of the seven wiring tracks 61 to 67 shown in FIG. 5 is lost. Therefore, in order to form the original seven wiring tracks 61 to 67, the arrangement area of the two wiring tracks 61 and 67 must be newly provided in the vertical direction, and this extra area is required. Therefore, the size of the basic cell 50 is increased, and the degree of integration cannot be improved.

  Next, Patent Documents 2 and 3 show semiconductor devices in which signal wirings and power supply wirings are arranged on the basic cells in order to improve the arrangement efficiency of the basic cells. In No. 3, no consideration is given to improving the degree of integration and enhancing the resistance to electromigration in the gate array semiconductor device which is the subject of the present invention.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a gate array semiconductor device capable of improving the degree of integration and enhancing the resistance to electromigration.

In order to solve the above-mentioned problem, the invention according to claim 1 is characterized in that a plurality of second conductive type semiconductor regions, first conductive type well contacts, and second conductive type formed in the first conductive type well along the horizontal direction. A first cell having a plurality of first conductivity type semiconductor regions and a second conductivity type well contact formed in the well of the mold along the horizontal direction, and formed in the horizontal direction of the first conductivity type well; A gate array semiconductor device having at least a basic cell comprising a plurality of second conductivity type semiconductor regions and a second cell having a plurality of first conductivity type semiconductor regions formed in a second conductivity type well along a horizontal direction. Therefore, the plurality of horizontal contacts are connected to any one of the plurality of second conductivity type semiconductor regions of the second cell and connected to the first conductivity type well contact of the first cell. A power supply line connected through a hole; and the second conductive type well contact of the first cell; and the one of the plurality of first conductive type semiconductor regions of the second cell. together comprising a horizontal direction of the plurality of connected ground wiring through a contact hole, the portion of the second above the power lines of cells are connected to the second conductivity type semiconductor region, the first cell Of the first conductivity type semiconductor region connected to the ground wiring of the second cell, while extending in a horizontal direction to a position corresponding to the position where the first conductivity type well contact is formed. part, is characterized that you have been formed to extend in a horizontal direction to a position corresponding to a formation position of the second conductivity type well contact of the first cell.

According to a second aspect of the present invention, a plurality of second conductivity type semiconductor regions and first conductivity type well contacts formed in the first conductivity type well along the horizontal direction, and the second conductivity type well in the horizontal direction. A first cell having a plurality of first conductivity type semiconductor regions and second conductivity type well contacts formed along the first conductivity type, and a plurality of second conductivity types formed in the first conductivity type well along the horizontal direction. A semiconductor region and a first conductivity type well contact; and a second cell having a plurality of first conductivity type semiconductor regions and a second conductivity type well contact formed in the second conductivity type well along the horizontal direction. According to a gate array semiconductor device having a basic cell, a plurality of horizontal cells are arranged in one of the first conductivity type well contact and the plurality of second conductivity type semiconductor regions of the first cell. A power supply connected through a contact hole and connected to one of the first conductivity type well contact and the plurality of second conductivity type semiconductor regions of the second cell through the plurality of horizontal contact holes. The wiring is connected to any one of the second conductivity type well contact and the plurality of first conductivity type semiconductor regions of the first cell through the plurality of horizontal contact holes, and the second cell together comprising a connected ground wiring through the cell of the second conductivity type well contact and the horizontal direction of the plurality of contact holes in any one region of the plurality of second conductivity type semiconductor region, the first A part of the second conductivity type semiconductor region to which the power supply wiring of the second cell is connected and the power supply wiring of the second cell are connected. A part of the second conductivity type semiconductor region is formed to extend in the horizontal direction, while a part of the first conductivity type semiconductor region to which the ground wiring of the first cell is connected and the portion of the second of said ground wiring is connected to the first conductivity type semiconductor region of the cell, it is characterized that you have been formed to extend in the horizontal direction.

The invention of claim 3, wherein relates to a gate array semiconductor device according to claim 2, and the second conductivity type well contact of the first of said second conductivity type well contact cell and the second cell Is characterized by comprising a common well contact.

According to a fourth aspect of the present invention, in the gate array semiconductor device according to the third aspect , the common well contact is disposed so as to overlap the first cell and the second cell. It is characterized by that.

A fifth aspect of the present invention relates to the gate array semiconductor device according to any one of the first to fourth aspects, wherein the first conductivity type is an N conductivity type and the second conductivity type is a P conductivity type. It is characterized by being.

  According to the gate array semiconductor device of the present invention, the power supply wiring connected to the first conductivity type well contact is connected to the second conductivity type semiconductor region through the plurality of contact holes without occupying an extra area in the vertical direction. In addition, the ground wiring connected to the second conductivity type well contact of the basic cell can be connected to the first conductivity type semiconductor region through a plurality of contact holes without occupying an extra area in the vertical direction. Therefore, the degree of integration can be improved and the resistance to electromigration can be enhanced.

  In the gate array semiconductor device of the present invention, a plurality of second conductivity type semiconductor regions and first conductivity type well contacts formed in the first conductivity type well along the horizontal direction, and the second conductivity type well in the horizontal direction. A first cell having a plurality of first conductivity type semiconductor regions and second conductivity type well contacts formed along the first conductivity type well, and a plurality of second conductivity type semiconductors formed in the first conductivity type well along the horizontal direction In a configuration having at least a basic cell comprising a region and a second cell having a plurality of first conductivity type semiconductor regions formed along a horizontal direction in a well of a second conductivity type, the first conductivity of the first cell A power supply wiring connected to the type well contact and connected to any one of the plurality of second conductivity type semiconductor regions of the second cell through a plurality of horizontal contact holes, and the first cell It is connected to the second conductivity type well contact, and includes a connection to a ground line through a horizontal direction of the plurality of contact holes in any one region of the plurality of first conductivity type semiconductor region of the second cell.

FIG. 1 is a plan view showing a basic cell constituting a gate array semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a plan view showing an example in which contact holes are formed at two locations in the same semiconductor region of the basic cell. It is.
In the gate array semiconductor device of this example, as shown in FIG. 1, the basic cell 9 includes a first cell 10 having four MOS transistors Q1 to Q4, and four MOS transistors Q5 to Q8. And a second cell 11 having The first cell 10 includes three substantially rectangular P-type semiconductor regions 2A to 2C formed along the horizontal direction in the N well 1 disposed at the top along the vertical direction, and the vertical direction. In the P well 3 disposed at the bottom, three substantially rectangular N-type semiconductor regions 4A to 4C formed along the horizontal direction, between the P-type semiconductor regions 2A and 2B, and the N-type semiconductor region 4C, A common first gate 5 extending along the vertical direction between 4B and between the P-type semiconductor regions 2B and 2C and between the N-type semiconductor regions 4B and 4A along the vertical direction. And a common second gate 6 extending in parallel, and an N well contact 7 and a P well contact 8 formed in the N well 1 and the P well 3, respectively. Here, as will be described later, the P-type semiconductor regions 2A and 2C constitute the drain regions of the pair of PMOS transistors Q1 and Q2, and the P-type semiconductor region 2B constitutes the common source region of Q1 and Q2. The N-type semiconductor regions 4A and 4C constitute drain regions of the pair of NMOS transistors Q3 and Q4, and the N-type semiconductor region 4B constitutes a common source region of Q3 and Q4.

  The second cell 11 includes two substantially rectangular P-type semiconductor regions 12A and 12C formed in the horizontal direction and an L-shaped P-type in the N-well 1 disposed in the upper portion along the vertical direction. Two substantially rectangular N-type semiconductor regions 14A and 14C and an L-shaped N-type semiconductor region formed along the horizontal direction in the semiconductor region 12B and the P-well 3 disposed below along the vertical direction. 14B, a common first gate 15 extending along the vertical direction between the P-type semiconductor regions 12A and 12B and between the N-type semiconductor regions 14C and 14B, and the P-type semiconductor regions 12B and 12C And a common second gate 16 extending along the vertical direction between the N-type semiconductor regions 14B and 14A. The N well contact 7 and the P well contact 8 formed in the first cell 10 are also used in common in the second cell 11. Of the three P-type semiconductor regions 12 </ b> A to 12 </ b> C, the upper end of the central L-shaped P-type semiconductor region 12 </ b> B extends in the horizontal direction to a position corresponding to the formation position of the N-well contact 7 of the first cell 10. Is formed. Similarly, of the three N-type semiconductor regions 14A to 14C, the lower end of the central L-shaped N-type semiconductor region 14B is horizontal to a position corresponding to the position where the P-well contact 8 of the first cell 10 is formed. It is formed extending in the direction.

  Here, as will be described later, in the first cell 10, the P-type semiconductor regions 2A and 2C are the drain regions of the pair of PMOS transistors Q1 and Q2, and the P-type semiconductor region 2B is the common source of Q1 and Q2. Configure the area. The N-type semiconductor regions 4A and 4C constitute drain regions of the pair of NMOS transistors Q3 and Q4, and the N-type semiconductor region 4B constitutes a common source region of Q3 and Q4. Similarly, in the second cell 11, the P-type semiconductor regions 12A and 12C constitute the drain regions of the pair of PMOS transistors Q5 and Q6, and the P-type semiconductor region 12B constitutes the common source region of Q5 and Q6. . The N-type semiconductor regions 14A and 14C constitute drain regions of the pair of NMOS transistors Q7 and Q8, and the N-type semiconductor region 14B constitutes a common source region of Q7 and Q8.

  In the first cell 10, contact holes 2a and 2b are formed in the P-type semiconductor region 2A from above along the vertical direction, and contact holes 2c to 2f are similarly formed in the P-type semiconductor region 2B. Contact holes 2g to 2i are respectively provided in the semiconductor region 2C. On the other hand, the N-type semiconductor region 4A has contact holes 4a and 4b from the bottom along the vertical direction, the N-type semiconductor region 4B has contact holes 4c to 4f, and the N-type semiconductor region 4C has the same structure. Contact holes 4g to 4i are respectively provided. The first gate 5 is provided with contact holes 5a and 5b from above along the vertical direction, and the second gate 6 is provided with contact holes 6a and 6b from below along the vertical direction. The first and second gates 5 and 6 are arranged point-symmetrically with respect to the central portion of the first cell 10. The N well contact 7 is provided with a contact hole 7a, and the P well contact 8 is provided with a contact hole 8a.

  In the second cell 11, contact holes 12a and 12b are formed from the top in the vertical direction in the P-type semiconductor region 12A, and contact holes 12c to 12f and 12j are similarly formed in the P-type semiconductor region 12B. Contact holes 12g to 12i are provided in the P-type semiconductor region 12C, respectively. On the other hand, the N-type semiconductor region 14A has contact holes 14a and 14b from the bottom along the vertical direction. Similarly, the N-type semiconductor region 14B has contact holes 14c to 14f and 14j, and the N-type semiconductor region 14C. Are provided with contact holes 14g to 14i, respectively. The first gate 15 is provided with contact holes 15a and 15b from above along the vertical direction, and the second gate 16 is provided with contact holes 16a and 16b from below along the vertical direction. The first and second gates 15 and 16 are arranged point-symmetrically with the central portion of the second cell 11 as the center.

  Further, a VDD (power supply) wiring 19 connected to the N well contact 7 common to the first and second cells 10 and 11 through a contact hole 7a is disposed along the horizontal direction, while the first and second cells The GND (ground) wiring 20 connected to the P well contact 8 common to the two cells 10 and 11 via the contact hole 8a is arranged in the horizontal direction. Further, contact holes corresponding to the P-type semiconductor regions 2A to 2C, 12A to 12C, the N-type semiconductor regions 4A, 4C, and 14A to 14C, the first gates 5 and 15, and the second gates 6 and 16, respectively. The seven wiring tracks 21 to 27 connected via the are arranged along the horizontal direction.

  With the above configuration, a pair of PMOS transistors Q1 and Q2 are formed in the N well 1 and a pair of NMOS transistors Q3 and Q4 are formed in the P well 3 in the first cell 10 of the basic cell 9. The Q1 and Q3 constitute a common first gate 5, and Q3 and Q4 constitute a common second gate 6 to constitute a CMOS circuit. Similarly, in the second cell 11 of the basic cell 9, a pair of PMOS transistors Q 5 and Q 6 are formed in the N well 1 and a pair of NMOS transistors Q 7 and Q 8 are formed in the P well 3. . Q5 and Q7 constitute a common first gate 15, and Q6 and Q8 constitute a common second gate 16 to form a CMOS circuit.

  Next, referring to FIG. 2, for the gate array semiconductor device having the basic cell 9 of this example, the pair of PMOS transistors Q5 and Q6 of the second cell 11 serving as an output terminal having a large current driving capability. An example in which the VDD wiring 19 is formed in the source region 12B and the GND wiring 20 is formed in the source region 14B of the pair of NMOS transistors Q7 and Q8 of the second cell 11 will be described. As shown in the figure, a VDD wiring 19 is formed in the N well contact 7 of the first cell 10 of the basic cell 9 through the contact hole 7 a and a P-type semiconductor region 12 B serving as the source region of the second cell 11. Are formed through two contact holes 12c and 12j provided in the horizontal direction. Similarly, the GND wiring 20 is formed in the P well contact 8 of the first cell 10 of the basic cell 9 through the contact hole 8a, and in the horizontal direction in the P-type semiconductor region 14B serving as the source region of the second cell 11. It is formed through the two contact holes 14c and 14j provided in.

  According to such a configuration, the VDD wiring 19 connected to the N-well contact 7 of the first cell 10 of the basic cell 9 can be connected to the source region of the second cell 11 without occupying an extra area in the vertical direction. The P-type semiconductor region 12B can be connected through two contact holes 12c and 12j, and the VSS wiring 20 connected to the P-well contact 8 of the first cell 10 of the basic cell 9 has an extra area in the vertical direction. Can be connected to the N-type semiconductor region 14B serving as the source region of the second cell 11 through the two contact holes 14c and 14j. Accordingly, since the number of contact holes can be increased for each source region after the formation regions of the seven wiring tracks 21 to 27 are secured, a current flows to an output terminal having a large current driving capability. Since the cross-sectional area of the wiring can be increased, the resistance to electromigration can be enhanced without reducing the degree of integration.

Thus, according to the gate array semiconductor device of this example, the three P-type semiconductor regions 2A to 2C formed in the N well 1 along the horizontal direction, the N well contact 7, and the P well 3 in the horizontal direction. A first cell 10 having at least three P-type semiconductor regions 4A to 4C and a P-well contact 8 formed along the three wells, and three N-type semiconductor regions 12A formed in the N-well 1 along the horizontal direction. In the configuration including the basic cell 9 including the second cell 11 including at least three N-type semiconductor regions 14A to 14C formed in the horizontal direction in the P well 3 and the P well 3, A VDD wiring 19 connected to the N-type well contact 7 and connected to the P-type semiconductor region 12B of the second cell 11 through two contact holes 12c and 12j in the horizontal direction; Since it has a GND wiring 20 connected to the P-type well contact 8 of the first cell 10 and connected to the N-type semiconductor region 14B of the second cell 11 through the contact holes 14c and 14j in the horizontal direction, In addition, the wirings 19 and 20 can be connected to the P-type semiconductor region 12B and the N-type semiconductor region 14B, which are source regions that function as output terminals having a large current driving capability, without occupying an excessive area.
Therefore, the degree of integration can be improved and the resistance to electromigration can be enhanced.

FIG. 3 is a plan view showing a basic cell constituting a gate array semiconductor device according to Embodiment 2 of the present invention, and FIG. 4 is a plan view showing an example in which contact holes are formed at two locations in the same semiconductor region of the basic cell. It is. The configuration of the gate array semiconductor device of this example is greatly different from the configuration of the first embodiment described above. In the configuration in which the basic cell is composed of the first cell and the second cell, the VDD wiring also in the first cell. And the GND wiring are respectively connected to the P-type semiconductor region and the N-type semiconductor region through two contact holes in the horizontal direction.
As shown in FIG. 3, the gate array semiconductor device of this example is basically characterized in that the first cell 10 and the second cell have a symmetrical positional relationship with respect to the central vertical axis. That is, as compared with the first embodiment, the N well contact 7A of the first cell 10 is arranged so as to move to the left along the horizontal direction, and the upper end of the P-type semiconductor region 2B is formed in the empty region generated thereby. It is formed extending in the horizontal direction toward N well contact 7A. In addition, a P-well contact 8 common to both the cells 10 and 11 is disposed at a position overlapping the first and second cells 10 and 11, and the lower end of the N-type semiconductor region 4B is formed in the empty region generated thereby. It extends in the horizontal direction toward the well contact 8. Similarly, the N-well contact 7B of the second cell 11 is arranged to move rightward along the horizontal direction, and the upper end of the P-type semiconductor region 12B faces the N-well contact 7B in the vacant region generated thereby. And extending in the horizontal direction. Further, the lower end of the N-type semiconductor region 14B extends in the horizontal direction toward the common P-well contact 8.

  In the first cell 10, contact holes 2c and 2k are provided at two locations along the horizontal direction at the upper end of the P-type semiconductor region 2B, and contact holes are provided at two locations along the horizontal direction at the lower end of the N-type semiconductor region 4B. 4c and 4k are respectively formed. Similarly, in the second cell 11, contact holes 12c and 12k are provided at two positions along the horizontal direction at the upper end of the P-type semiconductor region 12B, and two holes along the horizontal direction are provided at the lower end of the N-type semiconductor region 14B. Contact holes 14c and 14k are respectively formed at the locations. A contact hole 7b is formed in the N well contact 7B.

  Next, referring to FIG. 4, for the gate array semiconductor device having the basic cell 9 of this example, a pair of PMOS type of first and second cells 10 and 11 serving as output terminals having a large current driving capability. The VDD wiring 19 is formed in the source regions 2B and 12B of the transistors Q1, Q2 and Q5 and Q6, and the source region 4B of the pair of NMOS transistors Q3, Q4 and Q7 and Q8 of the first and second cells 10 and 11 is formed. , 14B, an example of forming the GND wiring 20 will be described. As shown in the figure, the VDD wiring 19 is formed in the N well contact 7A of the first cell 10 of the basic cell 9 through the contact hole 7a and through the two contact holes 12c and 12k in the P-type semiconductor region 2B. In addition, it is formed in the N well contact 7B of the second cell 11 through the contact hole 7b and at the two contact holes 12c and 12k in the P-type semiconductor region 12B.

Similarly, the GND wiring 20 is formed through the contact hole 8a of the common P well contact 8 of the first cell 10 of the basic cell 9 and through the two contact holes 4c and 4k of the N-type semiconductor region 4B. And formed in the N-type semiconductor region 14B of the second cell 11 through two contact holes 14c and 14k.
Except this, it is substantially the same as the first embodiment. Therefore, in FIG.3 and FIG.4, each part corresponding to the component of FIG.1 and FIG.2 is attached | subjected with the same number, and the description is abbreviate | omitted.

  According to such a configuration, the VDD wiring 19 connected to the N well contacts 7A and 7B of the first and second cells 10 and 11 of the basic cell 9 can be used without occupying an extra area in the vertical direction. Can be connected to the P-type semiconductor region 2B serving as the source region of the cell 10 through two contact holes 2c and 2k, and two contacts to the P-type semiconductor region 12B serving as the source region of the second cell 11. Connection can be made through the holes 12c and 12k. Similarly, the VDD wiring 19 connected to the common P-well contact 8 of the first and second cells 10 and 11 of the basic cell 9 does not occupy an extra area in the vertical direction, and the first cell 10 It can be connected to the N-type semiconductor region 4B serving as the source region through the two contact holes 4c and 4k, and the two contact holes 14c and 14k can be connected to the N-type semiconductor region 14B serving as the source region of the second cell 11. Will be able to connect through. Accordingly, since the number of contact holes can be increased for each source region after the formation regions of the seven wiring tracks 21 to 27 are secured, a current flows to an output terminal having a large current driving capability. Since the cross-sectional area of the wiring can be increased, the resistance to electromigration can be enhanced without reducing the degree of integration.

  As described above, in order to form contact holes in two locations in each of the P-type semiconductor regions 2B and 12B and the N-type semiconductor regions 4B and 14B, the minimum spacing between the contact holes determined by the design rule, It suffices if the minimum spacing with the diffusion region and the minimum spacing between the diffusion region and the well contact are satisfied, and the region where the contact hole can be disposed immediately below the VDD wiring 19 or the GND wiring 20 is not necessarily located on the wiring track. do not have to. If you are not satisfied with the spacing, try increasing the distance between the cells a little to satisfy the spacing. In general, in a gate array cell, the spacing between contact holes is smaller than the wiring pitch in the vertical direction. That is, (wiring pitch ≧ contact hole size + contact hole / gate minimum spacing × 2 + gate length). Therefore, even when the distance between the cells is increased, the above-mentioned minimum spacing can be satisfied only by increasing the distance smaller than one pitch, so that an increase in the cell size can be suppressed slightly. Note that if a contact hole having a rectangular cross section having a double cross-sectional area can be used, it is not necessary to consider the spacing between contact holes, and a narrower region can be used. Therefore, it is effective without increasing the cell area. Thus, the same effect as that of arranging the contact holes in two places can be obtained.

  In particular, according to the configuration of the second embodiment, contact holes can be formed in two locations with respect to the semiconductor region serving as the source region in each of the first and second cells. Since there is no restriction that the gate array can be formed only by the above-described method, there is an effect that the degree of freedom in designing the gate array can be improved.

As described above, the configuration of this example can provide substantially the same effect as that of the first embodiment.
In addition, according to the configuration of this example, the degree of freedom in designing the gate array can be improved.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the present invention can be changed even if there is a design change or the like without departing from the gist of the present invention. include. For example, in each embodiment, the example in which the basic cell is configured by the two cells of the first cell and the second cell has been described. However, the present invention is not limited to this, and the basic cell may be configured by three or more cells. In addition, the target region where the contact holes are formed at two locations is not necessarily limited to the source region. Further, for example, the MOS transistor used in each embodiment is not limited to an oxide film (Oxide) as a gate insulating film but may be a nitride film or a double film of an oxide film and a nitride film. It may be configured. That is, as long as it is a MIS (Metal Insulator Semiconductor) type transistor, it is not limited to a MOS type transistor but may be an MNS (Metal Nitride Semiconductor) type transistor or an MNOS (Metal Nitride Oxide Semiconductor) type transistor.

It is a top view which shows the basic cell which comprises the gate array semiconductor device which is Example 1 of this invention. It is a top view which shows the example which formed the contact hole in two places of the same semiconductor region of the basic cell. It is a top view which shows the basic cell which comprises the gate array semiconductor device which is Example 2 of this invention. It is a top view which shows the example which formed the contact hole in two places of the same semiconductor region of the basic cell. It is a top view which shows the basic cell which comprises the conventional gate array semiconductor device. It is a top view which shows the example which formed VDD wiring and GND wiring in the gate array semiconductor device, respectively. It is a top view which shows the structure of the conventional semiconductor device. It is a top view which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 N well 2A-2C, 12A-12C P-type semiconductor region 2a-2k, 4a-4k, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 12a-12k, 14a-14k Contact hole 3 P well 4A- 4C, 14 to 14C N-type semiconductor region 5, 15 First gate 6, 16 Second gate 7, 7A, 7B N well contact 8 P well contact (common well contact)
9 basic cell 10 first cell 11 second cell 19 VDD (power supply) wiring 20 GND (ground) wiring 21-27 wiring track Q1, Q2, Q5, Q6 PMOS type transistors Q3, Q4, Q7, Q8 NMOS type transistors

Claims (5)

A plurality of second conductivity type semiconductor regions and first conductivity type well contacts formed in the first conductivity type well along the horizontal direction, and a plurality of first conductivity type formed in the second conductivity type well along the horizontal direction. A first cell having a conductive type semiconductor region and a second conductive type well contact; and a plurality of second conductive type semiconductor regions and second conductive type wells formed along the horizontal direction in the first conductive type well. A gate array semiconductor device having a basic cell composed of at least a second cell having a plurality of first conductivity type semiconductor regions formed along a horizontal direction,
Connected to the first conductivity type well contact of the first cell, and connected to any one of the plurality of second conductivity type semiconductor regions of the second cell through the plurality of horizontal contact holes. Power supply wiring,
Connected to the second conductivity type well contact of the first cell, and connected to any one of the plurality of first conductivity type semiconductor regions of the second cell through the plurality of horizontal contact holes. together comprising a has been ground line,
A part of the second conductivity type semiconductor region to which the power supply wiring of the second cell is connected extends in a horizontal direction to a position corresponding to a formation position of the first conductivity type well contact of the first cell. A portion of the first conductivity type semiconductor region to which the ground wiring of the second cell is connected is formed at a position where the second conductivity type well contact of the first cell is formed. a gate array semiconductor device which is characterized that you have been formed to extend in the horizontal direction to correspond to a position in. A plurality of second conductivity type semiconductor regions and first conductivity type well contacts formed in the first conductivity type well along the horizontal direction, and a plurality of first conductivity type formed in the second conductivity type well along the horizontal direction. A first cell having a conductive type semiconductor region and a second conductive type well contact; a plurality of second conductive type semiconductor regions and first conductive type well contacts formed in the first conductive type well along the horizontal direction; A gate array semiconductor device having a basic cell comprising at least a plurality of first conductivity type semiconductor regions formed in a horizontal direction in a second conductivity type well and a second cell having a second conductivity type well contact. And
The first cell is connected to one of the first conductivity type well contact and the plurality of second conductivity type semiconductor regions of the first cell through the plurality of horizontal contact holes, and the second cell A power supply wiring connected to one of the first conductivity type well contact and the plurality of second conductivity type semiconductor regions through the plurality of horizontal contact holes;
The first cell is connected to one of the second conductivity type well contact and the plurality of first conductivity type semiconductor regions through the plurality of horizontal contact holes, and the second cell together comprising a connected ground wiring through the horizontal direction of the plurality of contact holes in one region or a second conductivity type well contact and the plurality of second conductivity type semiconductor region,
A part of the second conductivity type semiconductor region to which the power supply wiring of the first cell is connected and a part of the second conductivity type semiconductor region to which the power supply wiring of the second cell is connected are While extending in the horizontal direction, a part of the first conductivity type semiconductor region to which the ground wiring of the first cell is connected and the ground wiring of the second cell are connected It said portion of the first conductivity type semiconductor region, a gate array semiconductor device which is characterized that you have been formed to extend in the horizontal direction. 3. The gate array semiconductor device according to claim 2 , wherein the second conductivity type well contact of the first cell and the second conductivity type well contact of the second cell are formed of a common well contact. . 4. The gate array semiconductor device according to claim 3 , wherein the common well contact is disposed so as to overlap the first cell and the second cell. The first conductivity type is N conductivity type, a gate array semiconductor device according to any one of claims 1 to 4 wherein the second conductivity type characterized in that it is a P-type conductivity.

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