JP2013069953A - Nonvolatile semiconductor storage device and nonvolatile semiconductor storage device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit diffusion of an impurity which is doped to an impurity doped silicon layer, to an impurity undoped silicon layer.SOLUTION: A NAND cell NC1 comprises: word lines WL1 laminated on a select gate electrode SG1; and select gate electrodes SG2 formed on the word line WL1 in an uppermost layer, each of which is formed on each row. Each of the select gate electrodes SG1, SG2 and the word lines WL1 includes impurity doped silicon layers 2 and interlayer insulation films alternately laminated via a diffusion prevention layer 3. The word line WL1 includes the impurity doped silicon layer 2 sandwiched by the diffusion prevention layers 3.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device.

  In order to achieve high integration of the NAND flash memory, there is a method of stacking memory cells in the vertical direction. Here, in order to alternately laminate the electrode layer and the insulating layer, the impurity-added silicon layer and the impurity-free silicon layer are alternately stacked, and then the impurity-free silicon layer is selectively removed, and the insulator is provided there. There is a way to embed. At this time, in order to ensure the selectivity of the impurity-free silicon layer with respect to the impurity-added silicon layer, it is important to suppress diffusion of impurities added to the impurity-added silicon layer into the impurity-free silicon layer.

JP-A-6-151433

  An object of one embodiment of the present invention is to manufacture a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device capable of suppressing diffusion of impurities added to the impurity-added silicon layer into the impurity-free silicon layer. Is to provide a method.

  According to the nonvolatile semiconductor memory device of the embodiment, the stacked body, the through hole, the channel layer, the tunnel insulating film, the charge trap layer, and the block insulating film are provided. In the laminate, impurity-added silicon layers and interlayer insulating films are alternately laminated via diffusion prevention layers. The through hole is formed in the stacking direction of the stacked body. The channel layer is formed in the through hole along the stacking direction of the stacked body. The tunnel insulating film is formed between the inner surface of the through hole and the channel layer. The charge trap layer is formed between the inner surface of the through hole and the tunnel insulating film. The block insulating film is formed between the inner surface of the through hole and the charge trap layer.

FIG. 1A is a perspective view showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment, and FIG. 1B is a cross-sectional view showing a schematic configuration of a portion of the memory cell MC1 in FIG. FIG. FIG. 2 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG. 3 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG. 4 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG. 5 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG. 6A is a perspective view illustrating a schematic configuration of the nonvolatile semiconductor memory device according to the third embodiment, and FIG. 6B is a cross-sectional view illustrating a schematic configuration of a portion of the memory cell MC1 in FIG. FIG. FIG. 7 is a perspective view showing a schematic configuration of the nonvolatile semiconductor memory device according to the fourth embodiment, and FIG. 7B is a cross-sectional view showing a schematic configuration of a portion of the memory cell MC2 in FIG. . FIG. 8 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment. FIG. 9 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment. FIG. 10 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment. FIG. 11 is a cross-sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment.

  Hereinafter, a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device according to the embodiments will be described with reference to the drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1A is a perspective view showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment, and FIG. 1B is a cross-sectional view showing a schematic configuration of a portion of the memory cell MC1 in FIG. FIG. In the example of FIG. 1, a method of forming the NAND string NS1 by stacking four memory cells MC1 and connecting these four memory cells MC1 in series is shown. In FIG. 1, for the sake of simplicity, the interlayer insulating film formed between the impurity-added silicon layers 2 via the diffusion prevention layer 3 is omitted.

  In FIG. 1, a select gate electrode SG0 is formed on the base layer SB1. For example, a semiconductor substrate can be used as the base layer SB1. Four layers of word lines WL1 to WL4 are sequentially stacked on the select gate electrode SG0, and select gate electrodes SG1 to SG4 are formed for each row on the uppermost word line WL4. The word lines WL1 to WL4 and the select gate electrodes SG0 to SG4 are penetrated by the columnar body 12, whereby the NAND cell NC1 is configured. Here, in the select gate electrodes SG0 to SG4 and the word lines WL1 to WL4, the impurity-added silicon layer 2 and the interlayer insulating film can be alternately stacked via the diffusion prevention layer 3. Further, bit lines BL1 to BL3 are formed for each column on the select gate electrodes SG1 to SG4. The word lines WL <b> 1 to WL <b> 4 can be configured by the impurity-added silicon layer 2 sandwiched between the diffusion prevention layers 3. The impurity-added silicon layer 2 can be used as a control gate electrode of a NAND flash memory.

  Here, the diffusion prevention layer 3 can be an impurity-free silicon layer mixed with a diffusion inhibitor. As this diffusion inhibitor, a material having a lower diffusion rate in the silicon layer than the impurities in the impurity-added silicon layer 2 can be used. Further, the impurity of the impurity-added silicon layer 2 can be selected so that the etching rate of the impurity-added silicon layer 2 is lower than that of the impurity-free silicon layer. Specifically, the diffusion inhibitor can be selected from any one of boron nitride, nitrogen and carbon. The impurity of the doped silicon layer 2 can be selected from any one of boron and germanium.

  A through hole 4 is formed through the impurity-added silicon layer 2, the diffusion prevention layer 3, and the interlayer insulating film in the stacking direction. In the through hole 4, the select gate electrodes SG0 to SG4 and the word lines WL1 for four layers are formed. A columnar body 12 penetrating through WL4 is formed. A columnar insulator 11 is formed at the center of the columnar body 12. For example, a silicon oxide film can be used as the material of the columnar insulator 11. The columnar body 12 can be disposed at the intersections between the bit lines BL1 to BL3 and the select gate electrodes SG1 to SG4.

  A channel layer 7 is formed between the outer surface of the columnar insulator 11 and the inner surface of the through hole 4, and a tunnel insulating film 8 is formed between the inner surface of the through hole 4 and the channel layer 7. A charge trap layer 9 is formed between the inner surface of 4 and the tunnel insulating film 8, and a block insulating film 10 is formed between the inner surface of the through hole 4 and the charge trap layer 9. The channel layer 7, the tunnel insulating film 8, the charge trap layer 9, and the block insulating film 10 can be configured to penetrate the select gate electrodes SG0 to SG4 and the four word lines WL1 to WL4, respectively. For the channel layer 7, for example, a semiconductor such as Si can be used. As the tunnel insulating film 8 and the block insulating film 10, for example, a silicon oxide film can be used. For example, a silicon nitride film or an ONO film (a three-layer structure of silicon oxide film / silicon nitride film / silicon oxide film) can be used for the charge trap layer 9.

Here, the impurity-added silicon layer 2 is sandwiched between the diffusion-preventing layers 3 so that the impurities of the impurity-added silicon layer 2 can be prevented from diffusing up and down, and the impurity concentration of the impurity-added silicon layer 2 varies. Can be reduced.
Further, when nitrogen is added to the diffusion preventing layer 3, the breakdown voltage between the electrodes (control gate electrodes of the NAND flash memory) can be improved. Further, when carbon is added to the diffusion preventing layer 3, the dielectric constant between the electrodes can be lowered, and the threshold interference of the adjacent memory cell MC1 can be reduced.

In the embodiment of FIG. 1, the configuration in which the memory cells MC1 are stacked for four layers has been described. However, the memory cells MC1 may be stacked for n layers (n is an integer of 2 or more).
In the embodiment of FIG. 1, the method of forming the columnar insulator 11 at the center of the columnar body 12 passing through the select gate electrodes SG0 to SG4 and the four word lines WL1 to WL4 has been described. Instead of this, a columnar semiconductor may be embedded.

(Second Embodiment)
2 to 5 are cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. In the second embodiment, the case where the memory cells MC1 of FIG. 1 are stacked by four layers is taken as an example. Further, in the following description, a case where boron is selected as the impurity of the doped silicon layer 2 and nitrogen is selected as the diffusion preventing agent of the diffusion preventing layer 3 is taken as an example.
In FIG. 2A, the impurity-free silicon layer 1 and the impurity-added silicon layer 2 are alternately stacked on the base layer SB1 via the diffusion prevention layer 3 by a method such as CVD.
At this time, in the film formation of the impurity-free silicon layer 1, for example, the film formation temperature is set to a range of 400 to 650 degrees, SiH ₄ is used as the silicon gas, and the pressure is set to a reduced pressure environment of about 1 to 10 torr. can do.
In the film formation of the diffusion prevention layer 3, for example, the film formation temperature is set in the range of 400 to 650 degrees, SiH ₄ is used as the silicon gas, ammonia NH ₃ is used as the nitrogen-based gas, and the pressure is reduced to about 1 to 10 torr. Can be set in the environment.
The formation of the doped silicon layer 2, for example, the deposition temperature is set to a range of 650 degrees from 400 degrees, SiH4 as a silicon gas, a BCl ₃ is used as the boron gas, the pressure in the vacuum environment of about 1~10torr Can be set.

  Here, by providing the diffusion prevention layer 3 between the impurity-free silicon layer 1 and the impurity-added silicon layer 2, it is possible to suppress diffusion of impurities in the impurity-added silicon layer 2 into the impurity-free silicon layer 1. Can do. For this reason, the impurity distribution of the impurity-added silicon layer 2 is maintained, and processing can be performed while maintaining the etching selectivity between the impurity-free silicon layer 1 and the impurity-added silicon layer 2. It becomes possible to suppress the yield drop due to the change. In addition, by suppressing the shape change of the impurity-added silicon layer 2, it is possible to suppress variations in processing of the electrodes and to prevent deterioration of the characteristics of the memory cell. Further, diffusion of impurities due to heat treatment can be suppressed, and the film formation temperature can be increased, so that the film formation rate can be increased and productivity can be improved.

  Next, as shown in FIG. 2B, a hard mask M provided with an opening H is formed on the uppermost impurity-added silicon layer 2. Then, the impurity-free silicon layer 1, the impurity-added silicon layer 2, and the diffusion prevention layer 3 are etched through the hard mask M, thereby stacking the impurity-free silicon layer 1, the impurity-added silicon layer 2, and the diffusion prevention layer 3. A through hole 4 penetrating in the direction is formed. As a material for the hard mask M, a silicon oxide film or a silicon nitride film can be used.

  Here, the impurity-free silicon layer 1, the impurity-added silicon layer 2, and the impurity-added silicon layer 2 are formed when the through-hole 4 is formed by configuring the impurity-free silicon layer 1, the impurity-doped silicon layer 2, and the diffusion prevention layer 3 with a silicon material. In addition, the side etching of the diffusion preventing layer 3 can be made uniform, and deterioration of the embedding property of the through hole 4 can be suppressed.

  Next, as shown in FIG. 3A, the sacrificial film 5 is embedded in the through hole 4 by a method such as CVD, and the hard mask M is removed after the sacrificial film 5 is planarized by a method such as CMP. To do. As a material for the sacrificial film 5, a silicon oxide film or a silicon nitride film can be used.

  Next, as shown in FIG. 3B, the impurity-free silicon layer 1 is removed by selectively etching the impurity-free silicon layer 1 by a method such as wet etching. In order to reduce the resistance of the impurity-added silicon layer 2, the impurity-added silicon layer 2 may be silicided after the impurity-free silicon layer 1 is removed.

  Next, as shown in FIG. 4A, an interlayer insulating film 6 is embedded in the removed portion of the impurity-free silicon layer 1 by a method such as ALD-CVD.

  Next, as shown in FIG. 4B, the sacrificial film 5 in the through hole 4 is removed, and the side walls of the impurity-added silicon layer 2, the diffusion prevention layer 3, and the interlayer insulating film 6 are exposed.

  Next, as shown in FIG. 5, a block insulating film 10 is formed on the inner surface of the through hole 4 along the stacking direction of the impurity-added silicon layer 2, the diffusion prevention layer 3 and the interlayer insulating film 6 by a method such as CVD. . Next, the charge trap layer 9 is formed on the surface of the block insulating film 10 in the through hole 4 by a method such as CVD. Next, a tunnel insulating film 8 is formed on the surface of the charge trap layer 9 in the through hole 4 by a method such as CVD. Next, the channel layer 7 is formed on the surface of the tunnel insulating film 8 in the through hole 4 by a method such as CVD.

  As a result, the memory cell MC1 can be stacked without repeating the formation of the through hole 4, the block insulating film 10, the charge trap layer 9, the tunnel insulating film 8 and the channel layer 7 for each layer. The NAND flash memory can be highly integrated while suppressing the increase.

In the embodiment described above, SiH ₄ is taken as an example of the silicon gas, but other gases such as Si ₂ H ₆ and SiH ₂ Cl ₂ may be used, and other source gases containing silicon may be used. Further, although BCl ₃ is taken as an example of the boron gas, other gases such as B ₂ H ₆ and TMB (trimethyl borate) which is an organic raw material may be used, or other raw material gas containing boron may be used. NH ₃ is taken as an example of the nitrogen-based gas, but other gases such as NO and N ₂ O may be used, and other gases containing nitrogen may be used.

In the above-described embodiment, the case where nitrogen is selected as the diffusion preventing agent for the diffusion preventing layer 3 is taken as an example. However, carbon may be selected as the diffusion preventing agent for the diffusion preventing layer 3. In this case, a carbon-based gas such as C ₂ H ₄ may be used instead of the nitrogen-based gas. Alternatively, boron nitride may be selected as the diffusion preventing agent for the diffusion preventing layer 3. In this case, a combination of NH ₃ and BCl ₃ or other nitrogen-based gas and boron gas may be used instead of the nitrogen-based gas. The silicon layer containing boron nitride may be a boron nitride layer. As a gas for forming the boron nitride layer, a combination of NH ₃ and BCl ₃ or other nitrogen-based gas and boron gas may be used.

In the above-described embodiment, the case where boron is selected as the impurity of the doped silicon layer 2 is taken as an example, but germanium may be selected as the impurity of the doped silicon layer 2. In this case, a germanium-based gas such as GeH ₄ may be used instead of the silicon gas.

  Further, the film formation temperature may be changed between the impurity-free silicon layer 1, the impurity-added silicon layer 2, and the diffusion prevention layer 3, or the film formation temperature may be set to be the same only by switching the gas. Further, each time the impurity-free silicon layer 1, the impurity-added silicon layer 2, and the diffusion prevention layer 3 are formed, they may be formed out of the film formation chamber and discontinuously, but continuously in the film formation chamber. A film may be formed. In addition to the above, film formation by PE-CVD (Plasma-Enhanced Chemical Vapor deposition) may be used.

  Further, in order to obtain a selection ratio between the impurity-free silicon layer 1 and the impurity-added silicon layer 2, the method of combining the impurity-free silicon layer 1 and the impurity-added silicon layer 2 is taken as an example. Instead of the layer 1, a silicon layer having a lower impurity concentration than the impurity-added silicon layer 2 may be used.

(Third embodiment)
FIG. 6A is a perspective view illustrating a schematic configuration of the nonvolatile semiconductor memory device according to the third embodiment, and FIG. 6B is a cross-sectional view illustrating a schematic configuration of a portion of the memory cell MC1 in FIG. FIG. In the first embodiment shown in FIG. 1, the case where the memory cell MC1 is applied to the I-shaped tube constituted by one columnar body 12 has been described. However, in the third embodiment shown in FIG. A case where the memory cell MC1 is applied to a U-shaped tube composed of the columnar bodies 12a and 12b will be described. Further, in the example of FIG. 6, a method of forming the NAND string NS3 by folding the memory cells MC1 stacked for four layers and connecting the eight memory cells MC1 in series is shown. In FIG. 6, for the sake of simplicity, the interlayer insulating film formed between the impurity-added silicon layers 2 via the diffusion prevention layer 3 is omitted.

  In FIG. 6, a connection layer CN is formed on the semiconductor substrate SB2, and a connection portion 13 is formed in the connection layer CN. On the connection layer CN, the columnar bodies 12 a and 12 b are arranged adjacent to each other, and the lower ends of the columnar bodies 12 a and 12 b are connected to each other via the connection portion 13. On the connection layer CN, four layers of word lines WL14 to WL11 are sequentially stacked, and four layers of word lines WL15 to WL18 are sequentially stacked so as to be adjacent to the word lines WL14 to WL11, respectively. Yes. A select gate electrode SG11 is formed on the uppermost word line WL18, and a select gate electrode SG12 is formed on the uppermost word line WL11. The select gate electrode SG11 and the word lines WL15 to WL18 are penetrated by the columnar body 12a, and the select gate electrode SG12 and the word lines WL11 to WL14 are penetrated by the columnar body 12b, whereby the NAND cell NC3 is configured. Yes. Here, in the select gate electrodes SG11 and SG12 and the word lines WL11 to WL18, the impurity-added silicon layer 2 and the interlayer insulating film can be alternately stacked via the diffusion prevention layer 3. Further, a source line SL connected to the upper end of the columnar body 12a is provided on the select gate electrode SG11, and a bit connected to the upper end of the columnar body 12b via the plug PG is provided on the source line SL. Lines BL11 to BL15 are formed for each column. The word lines WL11 to WL18 can be constituted by the impurity-added silicon layer 2 sandwiched between the diffusion prevention layers 3. The impurity-added silicon layer 2 can be used as a control gate electrode of a NAND flash memory.

  A through-hole 4 is formed through the impurity-added silicon layer 2, the diffusion prevention layer 3, and the interlayer insulating film in the stacking direction. In the through hole 4, a columnar body 12a that penetrates the select gate electrode SG11 and the word lines WL15 to WL18 for four layers is formed, and a columnar body that penetrates the select gate electrode SG12 and the word lines WL11 to WL14 for four layers. 12b is formed. A columnar insulator 11 is formed at the center of these columnar bodies 12a and 12b. For example, a silicon oxide film can be used as the material of the columnar insulator 11. The columnar bodies 12a and 12b can be arranged at the intersections between the bit lines BL11 to BL15 and the word lines WL11 to WL18.

  A channel layer 7 is formed between the outer surface of the columnar insulator 11 and the inner surface of the through hole 4, and a tunnel insulating film 8 is formed between the inner surface of the through hole 4 and the channel layer 7. A charge trap layer 9 is formed between the inner surface of 4 and the tunnel insulating film 8, and a block insulating film 10 is formed between the inner surface of the through hole 4 and the charge trap layer 9. The channel layer 7, the tunnel insulating film 8, the charge trap layer 9, and the block insulating film 10 of the columnar body 12a can be configured to penetrate the select gate electrode SG11 and the word lines WL15 to WL18 for four layers, respectively. . The channel layer 7, the tunnel insulating film 8, the charge trap layer 9, and the block insulating film 10 of the columnar body 12b can be configured to penetrate the select gate electrode SG12 and the four word lines WL11 to WL14, respectively.

Here, the impurity-added silicon layer 2 is sandwiched between the diffusion-preventing layers 3 so that the impurities of the impurity-added silicon layer 2 can be prevented from diffusing up and down, and the impurity concentration of the impurity-added silicon layer 2 varies. Can be reduced.
Further, when nitrogen is added to the diffusion preventing layer 3, the breakdown voltage between the electrodes (control gate electrodes of the NAND flash memory) can be improved. Further, when carbon is added to the diffusion preventing layer 3, the dielectric constant between the electrodes can be lowered, and the threshold interference of the adjacent memory cell MC1 can be reduced.

In the embodiment of FIG. 6, the configuration in which the memory cells MC1 are stacked for four layers has been described. However, the memory cells MC1 may be stacked for n layers (n is an integer of 2 or more).
In the embodiment of FIG. 6, the method of forming the columnar insulator 11 at the center of the columnar bodies 12 a and 12 b has been described. However, a columnar semiconductor may be embedded instead of the columnar insulator 11.

(Fourth embodiment)
FIG. 7 is a perspective view showing a schematic configuration of the nonvolatile semiconductor memory device according to the fourth embodiment, and FIG. 7B is a cross-sectional view showing a schematic configuration of a portion of the memory cell MC2 in FIG. . In the first embodiment, the method of sandwiching the impurity-added silicon layer 2 in the diffusion prevention layer 3 has been described in order to prevent the impurities of the impurity-added silicon layer 2 from spreading up and down, but the fourth embodiment has been described. Now, a method of adding a diffusion inhibitor to the impurity-added silicon layer 2a itself in order to prevent the impurities of the impurity-added silicon layer 2a from spreading up and down will be described. In the example of FIG. 7, a method of forming the NAND string NS2 by stacking four memory cells MC2 and connecting these four memory cells MC2 in series is shown. In FIG. 7, the interlayer insulating film formed between the impurity-added silicon layers 2a is omitted for simplicity.

  In FIG. 7, a select gate electrode SG0a is formed on the base layer SB1. For example, a semiconductor substrate can be used as the base layer SB1. Four word lines WL1a to WL4a are stacked on the select gate electrode SG0a, and select gate electrodes SG1a to SG4a are formed for each row on the uppermost word line WL4a. Then, the word line WL1a to WL4a and the select gate electrodes SG0a to SG4a are penetrated by the columnar body 12, whereby the NAND cell NC2 is configured. Here, in the word lines WL1a to WL4a and the select gate electrodes SG0a to SG4a, the impurity-added silicon layers 2a and the interlayer insulating films can be alternately stacked. Further, bit lines BL1 to BL3 are formed for each column on the select gate electrodes SG1a to SG4a. Note that the word lines WL1a to WL4a can be formed of the impurity-added silicon layer 2a. The impurity-added silicon layer 2a can be used as a control gate electrode of a NAND flash memory.

  Here, a diffusion inhibitor is mixed in the impurity-added silicon layer 2a. As this diffusion inhibitor, a material having a lower diffusion rate in the silicon layer than impurities in the impurity-added silicon layer 2a can be used. Further, the impurity of the impurity-added silicon layer 2a can be selected so that the etching rate of the impurity-added silicon layer 2a is lower than that of the impurity-free silicon layer 1. Specifically, the diffusion inhibitor can be selected from any one of boron nitride, nitrogen and carbon. The impurity of the doped silicon layer 2a can be selected from any one of boron and germanium.

  A through hole 4a is formed through the doped silicon layer 2a and the interlayer insulating film in the stacking direction. The columnar body 12 penetrates through the select gate electrodes SG1 and SG2 and the word line WL1 for four layers in the through hole 4a. Is formed. A columnar insulator 11 is formed at the center of the columnar body 12. For example, a silicon oxide film can be used as the material of the columnar insulator 11. The columnar body 12 can be disposed at the intersections between the bit lines BL1 to BL3 and the select gate electrodes SG1a to SG4a.

  A channel layer 7 is formed between the outer surface of the columnar insulator 11 and the inner surface of the through hole 4a. A tunnel insulating film 8 is formed between the inner surface of the through hole 4a and the channel layer 7, and the through hole A charge trap layer 9 is formed between the inner surface of 4 a and the tunnel insulating film 8, and a block insulating film 10 is formed between the inner surface of the through hole 4 a and the charge trap layer 9.

  Here, by adding a diffusion inhibitor to the impurity-added silicon layer 2a, it is possible to suppress the impurity of the impurity-added silicon layer 2a from diffusing up and down, thereby reducing the variation in the impurity concentration of the impurity-added silicon layer 2a. Can be reduced.

In the embodiment of FIG. 7, the configuration in which four memory cells MC2 are stacked has been described. However, the memory cells MC2 may be stacked in n layers.
In the embodiment of FIG. 7, the method of forming the columnar insulator 11 at the center of the columnar body 12 has been described, but a columnar semiconductor may be embedded instead of the columnar insulator 11.
In the embodiment of FIG. 7, the method of providing the select gate electrodes SG0, SG1 to SG4 above and below the NAND string NS2, respectively, has been described. However, the NAND string NS2 is folded at the lower end of the NAND string NS2, and the folded NAND string A select gate electrode may be provided at the upper end of NS2.

(Fifth embodiment)
8 to 11 are cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment. In the fifth embodiment, the case where the memory cells MC2 of FIG. 7 are stacked by four layers is taken as an example. Further, in the following description, a case where boron is selected as the impurity of the doped silicon layer 2a and carbon is selected as the diffusion preventing agent of the doped silicon layer 2a is taken as an example.
In FIG. 8A, the impurity-free silicon layer 1 and the impurity-added silicon layer 2a are alternately stacked on the base layer SB1 by a method such as CVD. Note that carbon is mixed in the impurity-added silicon layer 2a as a diffusion inhibitor.
At this time, in the film formation of the impurity-free silicon layer 1, for example, the film formation temperature is set to a range of 400 to 650 degrees, SiH ₄ is used as the silicon gas, and the pressure is set to a reduced pressure environment of about 1 to 10 torr. can do.
The formation of the doped silicon layer 2a, eg, a film formation temperature was set to a range of 650 degrees from 400 degrees, SiH4 as a silicon gas, BCl ₃ as a boron gas, using ethylene _(C 2 _{H 4)} as a carbon gas The pressure can be set to a reduced pressure environment of about 1 to 10 torr.

  Here, by adding carbon to the impurity-added silicon layer 2a as a diffusion inhibitor, it is possible to suppress the impurities of the impurity-added silicon layer 2a from diffusing into the impurity-free silicon layer 1. Therefore, the impurity distribution of the impurity-added silicon layer 2a is maintained, and processing can be performed while maintaining the etching selectivity between the impurity-free silicon layer 1 and the impurity-added silicon layer 2a. The shape of the impurity-added silicon layer 2a It becomes possible to suppress the yield drop due to the change. Further, by suppressing the change in shape of the impurity-added silicon layer 2a, it is possible to suppress variations in processing of the electrodes and to prevent deterioration of the memory cell characteristics. Further, diffusion of impurities due to heat treatment can be suppressed, and the film formation temperature can be increased, so that the film formation rate can be increased and productivity can be improved.

  Next, as shown in FIG. 8B, a hard mask M provided with openings H is formed on the uppermost impurity-added silicon layer 2a. Then, by etching the impurity-free silicon layer 1 and the impurity-added silicon layer 2a through the hard mask M, a through hole 4a penetrating the impurity-free silicon layer 1 and the impurity-added silicon layer 2a in the stacking direction is formed.

  Next, as shown in FIG. 9A, the sacrificial film 5 is embedded in the through hole 4a by a method such as CVD, and the sacrificial film 5 is planarized by a method such as CMP, and then the hard mask M is removed. To do.

  Next, as shown in FIG. 9B, the impurity-free silicon layer 1 is removed by selectively etching the impurity-free silicon layer 1 by a method such as wet etching. In order to reduce the resistance of the doped silicon layer 2a, the doped silicon layer 2a may be silicided after the undoped silicon layer 1 is removed.

  Next, as shown in FIG. 10A, an interlayer insulating film 6 is buried in the removed portion of the impurity-free silicon layer 1 by a method such as ALD-CVD.

  Next, as shown in FIG. 10B, the sacrificial film 5 in the through hole 4a is removed, and the side walls of the impurity-added silicon layer 2a and the interlayer insulating film 6 are exposed.

  Next, as shown in FIG. 11, a block insulating film 10 is formed on the inner surface of the through hole 4a along the stacking direction of the impurity-added silicon layer 2a and the interlayer insulating film 6 by a method such as CVD. Next, the charge trap layer 9 is formed on the surface of the block insulating film 10 in the through hole 4a by a method such as CVD. Next, the tunnel insulating film 8 is formed on the surface of the charge trap layer 9 in the through hole 4a by a method such as CVD. Next, the channel layer 7 is formed on the surface of the tunnel insulating film 8 in the through hole 4a by a method such as CVD.

  As a result, the memory cell MC2 can be stacked without repeating the formation of the through hole 4a, the block insulating film 10, the charge trap layer 9, the tunnel insulating film 8 and the channel layer 7 for each layer. The NAND flash memory can be highly integrated while suppressing the increase.

In the embodiment described above, SiH ₄ is taken as an example of the silicon gas, but other gases such as Si ₂ H ₆ and SiH ₂ Cl ₂ may be used, and other source gases containing silicon may be used. Further, although BCl ₃ is taken as an example of the boron gas, other gases such as B ₂ H ₆ and TMB (trimethyl borate) which is an organic raw material may be used, or other raw material gas containing boron may be used. Although C ₂ H ₄ is taken as an example of the carbon-based gas, other gases containing carbon may be used.

In the above-described embodiment, the case where carbon is selected as the diffusion preventing agent for the doped silicon layer 2a is taken as an example. However, nitrogen may be selected as the diffusion preventing agent for the doped silicon layer 2a. In this case, a nitrogen-based gas such as NH ₃ , NO, N ₂ O may be used instead of the carbon-based gas. At this time, boron nitride is generated because it is a combination of a nitrogen-based gas and a boron-based gas.

Further, in the above-described embodiment, the case where boron is selected as the impurity of the impurity-added silicon layer 2a is taken as an example, but germanium may be selected as the impurity of the impurity-added silicon layer 2a. In this case, a germanium-based gas such as GeH ₄ may be used instead of the silicon gas.

  Further, the film formation temperature may be changed between the impurity-free silicon layer 1 and the impurity-added silicon layer 2a, or the film formation temperature may be set to be the same only by switching the gas. In addition, the impurity-free silicon layer 1 and the impurity-added silicon layer 2a may be formed out of the film formation chamber each time the film is formed, but may be formed continuously in the film formation chamber. May be. In addition to the above, film formation by PE-CVD (Plasma-Enhanced Chemical Vapor deposition) may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  SB1 base layer, 1 impurity-free silicon layer, 2 and 2a impurity-doped silicon layer, 3 diffusion prevention layer, 4 and 4a through hole, 5 sacrificial film, 6 interlayer insulating film, 7 channel layer, 8 tunnel insulating film, and 9 charge Trap layer, 10 block insulating film, 11 columnar insulator, 12 columnar body, 13 connecting portion, WL1 to WL4, WL1a to WL4a, WL11 to WL18 word line, BL1 to BL3, BL11 to BL15 bit line, SG0 to SG4, SG0a SG4a, SG11, SG12 Select gate electrode, NS1 to NS3 NAND string, NC1 to NC3 NAND cell, MC1, MC2 memory cell, M hard mask, H opening, SB2 semiconductor substrate, CN connection layer, PG plug, SL source line

Claims (9)

A stacked body in which impurity-doped silicon layers and interlayer insulating films are alternately stacked via diffusion prevention layers;
A through-hole formed in the stacking direction of the laminate,
A channel layer formed in the through hole along the stacking direction of the stacked body;
A tunnel insulating film formed between the inner surface of the through hole and the channel layer;
A charge trap layer formed between the inner surface of the through hole and the tunnel insulating film;
A nonvolatile semiconductor memory device comprising: a block insulating film formed between an inner surface of the through hole and the charge trap layer. A laminated body in which impurity-doped silicon layers containing a diffusion inhibitor and interlayer insulating films are alternately laminated;
A through-hole formed in the stacking direction of the laminate,
A channel layer formed in the through hole along the stacking direction of the stacked body;
A tunnel insulating film formed between the inner surface of the through hole and the channel layer;
A charge trap layer formed between the inner surface of the through hole and the tunnel insulating film;
A nonvolatile semiconductor memory device comprising: a block insulating film formed between an inner surface of the through hole and the charge trap layer.   The nonvolatile semiconductor memory device according to claim 2, wherein the diffusion inhibitor is selected from any one of boron nitride, nitrogen, and carbon.   4. The nonvolatile semiconductor memory device according to claim 1, wherein the impurity of the impurity-added silicon layer is selected from any one of boron and germanium. 5. Alternately stacking a first silicon layer and a second silicon layer having an impurity concentration lower than that of the first silicon layer through a diffusion prevention layer;
Forming a through-hole penetrating the first silicon layer, the second silicon layer, and the diffusion prevention layer in the stacking direction;
Selectively removing the second silicon layer;
Embedding an interlayer insulating film in the portion where the second silicon layer is removed;
Forming a block insulating film on the inner surface of the through hole;
Forming a charge trap layer on the surface of the block insulating film in the through hole;
Forming a tunnel insulating film on the surface of the charge trap layer in the through hole;
And a step of forming a channel layer on the surface of the tunnel insulating film in the through-hole.   6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the diffusion prevention layer is an impurity-free silicon layer containing a diffusion inhibitor. A step of alternately laminating an impurity-added silicon layer mixed with a diffusion inhibitor and an impurity-free silicon layer;
Forming a through-hole penetrating the impurity-added silicon layer and the impurity-free silicon layer in the stacking direction;
Selectively removing the impurity-free silicon layer;
Embedding an interlayer insulating film in the portion where the impurity-free silicon layer is removed;
Forming a block insulating film on the inner surface of the through hole;
Forming a charge trap layer on the surface of the block insulating film in the through hole;
Forming a tunnel insulating film on the surface of the charge trap layer in the through hole;
And a step of forming a channel layer on the surface of the tunnel insulating film in the through-hole.   8. The method of manufacturing a nonvolatile semiconductor memory device according to claim 7, wherein the diffusion preventing agent is selected from any one of boron nitride, nitrogen, and carbon.   9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 7, wherein the impurity is selected from any one of boron and germanium.

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