TWI478254B - 引線上凸塊之倒裝晶片互連 - Google Patents

引線上凸塊之倒裝晶片互連 Download PDF

Info

Publication number
TWI478254B
TWI478254B TW101111925A TW101111925A TWI478254B TW I478254 B TWI478254 B TW I478254B TW 101111925 A TW101111925 A TW 101111925A TW 101111925 A TW101111925 A TW 101111925A TW I478254 B TWI478254 B TW I478254B
Authority
TW
Taiwan
Prior art keywords
bump
substrate
interconnect
semiconductor die
bumps
Prior art date
Application number
TW101111925A
Other languages
English (en)
Other versions
TW201237976A (en
Inventor
Rajendra D Pendse
Original Assignee
Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chippac Inc filed Critical Chippac Inc
Publication of TW201237976A publication Critical patent/TW201237976A/zh
Application granted granted Critical
Publication of TWI478254B publication Critical patent/TWI478254B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

引線上凸塊之倒裝晶片互連
本發明有關半導體封裝，尤共有關倒裝晶片互連。
倒裝晶片封裝包括黏在封裝基板上的半導體晶粒，其中晶粒的作用側面對基板。照慣例，藉由黏在晶粒之互連焊墊之陣列上及焊接至基板之互連焊墊(通常稱為「捕獲焊墊」)之對應(互補)陣列的凸塊，即可形成晶粒中電路和基板中電路的互連。
積體電路上電子特徵的面密度已大幅增加，具有較大之電路特徵密度的晶片也具有較大之用於和封裝基板互連之位置的密度。
此封裝係藉由封裝及底部電路之間的第二階互連(如接針)而連接至採用此封裝之裝置中的底部電路，如印刷電路板(如「主機板」)。第二階互連具有的間距比倒裝晶片互連大，因此基板上的配線照慣例會「成扇形散開」。重大的技術發展已經可以建構精細的線路及間隔；但在習用的配置中，相鄰焊墊之間的間隔卻會限制接線數而非避免陣列中更多向內的捕獲焊墊，且照慣例會在封裝基板內的多個金屬層上，在晶粒下的捕獲焊墊及封裝的外部接針之間形成成扇形散開的配線。對於複雜的互連陣列，可能需要使用具有多層的基板，才能達成封裝上晶粒焊墊及第二階互連之間的配線。
多層基板很昂貴，且在習用的倒裝晶片構想中，通常光是基板就佔去封裝成本的一半以上(在一些典型的例子中，約佔60%)。多層基板的高成本一直是限制主流產品之倒裝晶片技術發展的因素。
在習用的倒裝晶片構想中，散逸配線圖案通常會引起額外的電寄生現象，因為配線在信號傳輸路徑的線路層之間包括短程的未屏蔽線路及通道。電寄生現象將明顯限制封裝的效能。
根據本發明，將互連凸塊直接連接至引線，而非連接至焊墊，即可完成倒裝晶片互連。本發明可在基板上提供更有效的接線配線。尤其，可在基板的單一金屬層中整個形成信號配線。這可減少基板中的層數，且在單層中形成信號接線也可以擺脫一些基板必須符合的通道、線路及間隔設計規則。此基板簡化可大幅減少倒裝晶片封裝的總成本。引線上凸塊架構亦有助於消除基板設計如通道及「導孔(stub)」等特徵，及啟用信號傳輸微帶控制的阻抗電環境，藉此大幅提高效能。
在一個一般方面中，本發明具有倒裝晶片互連，該互連在晶粒上具有黏在互連焊墊上的焊料凸塊並在基板上嚙合至對應接線上。
在另一個一般方面，本發明具有一倒裝晶片封裝，其包括：一晶粒，其在一作用表面中具有黏在互連焊墊上的焊料凸塊；及一基板，其在一晶粒黏著表面中具有導電接線，其中該等凸塊係直接嚙合在該等接線上。
一般而言，根據本發明的方法形成引線上凸塊互連，且並未使用在程序中再熔化階段期間會限制熔化焊料的焊料遮罩。免除焊料遮罩的需求可以產生更精細的互連幾何形狀。
在部分具體實施例中，進一步提供該基板一焊料遮罩，該遮罩在引線的互連位置上具有開口。在部分具體實施例中，進一步提供該基板在互連位置之引線上的焊料膏。
在另一個一般方面，本發明具有一種用於形成倒裝晶片互連的方法，其係藉由：提供一基板，該基板具有：在一晶粒黏著表面中形成的接線、及在一作用表面中具有黏在互連焊墊上之凸塊的一晶粒；固定該基板及該晶粒；塗上大量可固化黏著劑於該基板上(覆蓋至少該等接線上的連接位置)或該晶粒之作用側上(覆蓋至少該等凸塊)；放置該晶粒，將該晶粒的作用側朝向該基板的晶粒黏著表面，及對準該晶粒及基板然後將其中一個移向另一個，致使該等凸塊接觸該基板上該等對應的接線(引線)；施力以將該等凸塊壓在該等嚙合接線上，足夠在該凸塊及該嚙合接線之間取代該黏著劑；至少部分固化該黏著劑；熔化然後再重新凝固該焊料，以在該凸塊及該接線之間形成一冶金互連。
在另一個一般方面，本發明具有一種用於形成倒裝晶片互連的方法，其係藉由：提供一基板，該基板具有：在晶粒黏著表面中形成的接線、在該引線之互連位置上具有開口的一焊料遮罩、及在一作用表面中具有黏在互連焊墊上之凸塊的一晶粒；固定該基板及該晶粒；放置該晶粒，將該晶粒的作用側朝向該基板的晶粒黏著表面，及對準該晶粒及基板然後將其中一個移向另一個，致使該等凸塊接觸該基板上該等對應的接線(引線)；熔化然後再重新凝固以在該凸塊及該接線之間形成一冶金互連。
在部分具體實施例中，該焊料凸塊包括一可壓扁的焊料部分，然後熔化及凝固步驟可熔化該凸塊以在該引線上形成互連。在部分具體實施例中，進一步提供該基板在該引線上的一焊料膏，及將該晶粒及該基板移向彼此的步驟可在該引線上的該等凸塊及該焊料之間形成一接觸，然後熔化及凝固步驟可熔化在該引線上的焊料以形成互連。
在另一個一般方面，本發明具有一種用於形成倒裝晶片互連的方法，其係藉由：提供一基板，該基板具有：在一晶粒黏著表面中形成的接線、在該引線之互連位置上具有開口的一焊料遮罩、在該互連位置之引線上的焊料膏、及在一作用表面中具有黏在互連焊墊上之凸塊的一晶粒；固定該基板及該晶粒；放置該晶粒，將該晶粒的作用側朝向該基板的晶粒黏著表面，及對準該晶粒及基板然後將其中一個移向另一個，致使該等凸塊接觸該基板上該等對應接線(引線)上的焊錫膏；熔化然後再重新凝固該焊料膏，以在該凸塊及該接線之間形成一冶金互連。
本發明現在將參考說明本發明替代具體實施例之圖式進一步詳細說明。圖式為概略圖，顯示本發明之特徵及與其他特徵及結構之關係，其均未按比例繪製。為清楚說明起見，在說明本發明具體實施例的圖式中，對應其他圖式中元件的元件並未全部特別重新標記，不過其在所有圖式中均可迅速識別。
習用的倒裝晶片互連係利用熔化程序形成，以將凸塊(照慣例，焊料凸塊)結合至對應之捕獲焊墊的嚙合表面上，因此，這可稱為「捕獲焊墊上凸塊」(「BOC」)互連。在BOC設計中明顯有兩個特徵：第一，需要使用比較大的捕獲焊墊以配合晶粒上的凸塊；第二，需要使用通常稱為「焊料遮罩」的絕緣材料以在互連程序期間限制焊料的流動。焊料遮罩開口可定義在捕獲焊墊之熔化焊料的輪廓(「焊料遮罩定義的」)，或是無法藉由遮罩開口定義焊料輪廓(「非焊料遮罩定義的」)；後一個情況如圖1的範例，下文將會詳述；焊料遮罩開口可明顯大於捕獲焊墊。用於定義焊料遮罩開口的技術具有寬廣的公差範圍。因此，對於焊料遮罩定義的凸塊組態，捕獲焊墊必須很大(通常大於遮罩開口的設計尺寸甚多)，以確保遮罩開口可位在焊墊的嚙合表面上；及對於非焊料遮罩定義的凸塊組態，焊料遮罩開口必須大於捕獲焊墊。捕獲焊墊的寬度(圓形焊墊則為直徑)通常約和球(或凸塊)直徑相同，且可以比接線寬度寬二到四倍。這會使頂部基板層損失許多配線間隔。尤其，例如，「散逸配線間距」會大於基板技術能夠提供的最細接線間距甚多。這表示，通常在晶粒的覆蓋區之下，必須藉由短導孔及通道在下方基板層上配線極大量的焊墊，以從所論焊墊放射。
圖1及2以截面圖顯示習用倒裝晶片封裝的部分10、20；圖1局部的截面圖係沿著圖2直線1-1'截取和封裝基板表面平行的平面；及圖2局部的截面圖係沿著圖1直線2-2'截取和封裝基板表面垂直的平面。特定特徵顯示猶如透明，但圖1中之許多特徵至少部分以覆蓋的特徵顯示成陰影。現在參考圖1及圖2，封裝基板的晶粒黏著表面包括在介電層12上形成的金屬或薄層。將金屬層圖案化可形成引線13及捕獲焊墊14。絕緣層16 ，通常又稱為「焊料遮罩」，可覆蓋基板的晶粒黏著表面；焊料遮罩通常以光可定義的材料構成及藉由習用的光阻圖案化技術進行圖案化，可曝露捕獲焊墊14的嚙合表面。黏在晶粒18 之作用側上之焊墊的互連凸塊15可結合至基板上對應捕獲焊墊14的嚙合表面，以在晶粒上的電路及基板上的引線之間形成適當的電互連。在回熔的焊料冷卻以建立電連接後，會將底部填膠材料17 引入晶粒18 及基板12 之間的間隔，以在機械上穩定互連並保護晶粒及基板之間的特徵。
如圖1舉例顯示，基板(引線13)上方金屬層中的信號散逸接線，從其個別捕獲焊墊14引導橫跨晶粒邊緣位置，如虛線11所示，並離開晶粒覆蓋區。在典型的範例中，信號接線可具有散逸間距PE 約112um。30um/30um的設計規則通常用於如圖1所示組態中的接線本身；亦即，接線標稱為30um寬，及其間隔相近30um。捕獲焊墊通常大於接線寬度三倍，因此，在此範例中，捕獲焊墊具有標稱90 um的寬度(或在此範例中，若約略為圓形，則是直徑)。還有，在此範例中，焊料遮罩中的開口大於焊墊，且具有135 um的標稱寬度(直徑)。
圖1及2顯示非焊料遮罩定義的焊料輪廓。隨著晶粒上凸塊的易熔材料熔化，熔化的焊料傾向於「弄濕」引線及捕獲焊墊的金屬，及焊料傾向於「跑出」任何未遮罩的連續金屬表面上。焊料傾向於沿著連續引線13流動，及在此焊料流動會受到焊料遮罩(如圖1的19)的限制。焊墊上非焊料遮罩定義的焊料輪廓在圖2中清楚可見，其中將凸塊15的材料顯示為在捕獲焊墊14的側面上流動的29並向下到達基板12之介電層的表面。這稱為「非焊料遮罩定義的輪廓」，因為焊料遮罩並不會限制焊料在表面上的流動及向下到達捕獲焊墊的側面，除非焊墊有大量過多的焊料，否則焊料的流動會受到以下事實的限制：基板的介電表面通常不會被熔化的焊料弄濕。在如圖1的習用配置中，除了其他因素之外，捕獲焊墊之密度的下限係由以下因素決定：對遮罩形成技術之能力的限制，以製造可靠的窄遮罩結構；及在相鄰遮罩開口之間提供遮罩結構的需求。除了其他因素之外，散逸密度的下限另外由以下因素決定：將位置更為集中之捕獲焊墊的散逸線路配線在位置更為週邊之捕獲焊墊之間的需求。
圖3以和圖2相同的截面圖顯示習用之焊料遮罩定義的焊料輪廓。所示的晶粒38 係藉由凸塊35附加到捕獲焊墊34的嚙合表面上；藉由圖案化在基板32 之介電層之晶粒黏著側上的金屬層，即可和接線(引線33)一起形成捕獲焊墊34。在回熔的焊料冷卻以建立電連接後，會將底部填膠材料37 引入晶粒38 及基板32 之間的間隔，以在機械上穩定互連並保護晶粒及基板之間的特徵。此處的捕獲焊墊34比圖1及2中的範例寬，且焊料遮罩開口小於捕獲焊墊，因此焊料遮罩材料可覆蓋各捕獲焊墊之嚙合表面的側面及部分(如39所示)及引線33。在使凸塊35和個別捕獲焊墊34之嚙合表面接觸，然後再加以熔化後，焊料遮罩材料39可限制熔化之焊料的流動，因此焊料輪廓的形狀可以藉由捕獲焊墊34上之遮罩開口的形狀及尺寸來定義。
圖4及6各根據本發明的一項具體實施例，分別以沿著圖5及7中直線4-4'及6-6'截取自和基板表面平行之平面的局部截面圖，顯示倒裝晶片互連之引線上凸塊(「BOL」的部分)。特定特徵顯示猶如透明。根據本發明，將凸塊直接嚙合至基板上個別的窄引線或接線上，即可達到互連，因此，這在此又稱為「引線上凸塊」(「BOL」)互連。焊料遮罩材料通常在這麼精細的幾何形狀無法解決，而根據本發明的這些具體實施例，並不用焊料遮罩。裝配程序的過程中不用焊料遮罩即可完成限制熔化之焊料流動的功能(說明如下)。圖5顯示圖4之封裝的局部截面圖，其係沿著圖4直線5-5'截取自和封裝基板表面之平面垂直的平面；及圖7顯示圖6之封裝的局部截面圖，其係沿著圖6直線7-7'截取自和封裝基板表面之平面垂直的平面。
圖4及6根據本發明，舉例顯示用於引線上凸塊(「BOL」)基板的散逸配線圖案：在圖4中，配置用於其上互連球之晶粒黏著焊墊在接近晶粒周圍排成一列的晶粒，會在接近晶粒覆蓋區邊緣排成一列的散逸接線43上，將凸塊45嚙合至對應的互連位置，如虛線41所示；在圖6中，配置用於其上晶粒黏著焊墊在接近晶粒周圍為平行列之陣列的晶粒，會在接近晶粒覆蓋區邊緣之互補陣列的散逸接線63上，將凸塊65嚙合至對應的互連位置，如虛線61所示。
如圖4及6顯示，利用根據本發明之引線上凸塊互連可達到的配線密度能夠等於基板技術所提供之最精細的接線間距。在所示的特定情況中，這可構成比習用之捕獲焊墊上凸塊配置所達到的配線密度高約90%。在BOL之周圍列具體實施例(如圖4)中，係按照精細的間距放置凸塊，該間距等於基板之最精細的接線間距。此配置對裝配程序將形成挑戰，因為凸塊形成及焊接的間距必須非常精細。在BOL的周圍陣列形式(如圖6)中，會將凸塊配置在區域陣列上，以對更大的凸塊形成及焊接間距提供更大的間隔，因而能夠因應裝配程序的技術挑戰。即使在陣列具體實施例中，基板上的配線接線和周圍列配置一樣係按照相同的有效間距，因此圖6的配置不用犧牲精細散逸配線間距的好處，即可因應精細間距凸塊形成及焊接的重責。
現在尤其請參考圖4及5，會在基板介電層42 的晶粒黏著表面上，藉由圖案化金屬層以形成引線43。根據本發明，將晶粒上的凸塊45直接結合至引線43上，即可形成晶粒48 的電互連。根據本發明，並不需要使用捕獲焊墊，及在如圖4及5的具體實施例中，也不需要使用焊料遮罩；此程序詳細說明如下。
習用的捕獲焊墊的寬度(直徑)通常和凸塊的相同，且通常是接線或引線寬度的二至四倍寬。正如所瞭解的，預期引線的寬度會有一些變化。如本文所用，多達標稱120%的接線寬度或接線設計規則寬度的接線寬度變化無法構成捕獲焊墊，及根據本發明的引線上凸塊互連包括在引線如此較寬部分上形成的凸塊。
同樣地，參考圖6及7，藉由在基板介電層62 的晶粒黏著表面上圖案化金屬層，即可形成引線63。信號散逸接線會引導橫跨晶粒邊緣位置，如虛線61所示，並離開晶粒覆蓋區。根據本發明，將晶粒上的凸塊65直接結合至引線63上，即可形成晶粒68 的電互連。從成列的互連位置引導橫跨晶粒邊緣位置到達晶粒覆蓋區之內部的特定散逸接線，如66，會在互連位置之較外圍列的凸塊65之間通過。根據本發明，並不需要使用捕獲焊墊，及在如圖6及7的具體實施例中，也不需要使用焊料遮罩；此程序詳細說明如下。
如圖4及6所示，根據本發明的引線上凸塊互連能夠提供明顯較高的信號接線散逸配線密度。還有，如圖4及6所示，根據本發明此方面的BOL互連並不需要使用焊料遮罩以定義互連位置的焊料輪廓。
如圖4、5、6及7舉例所示之具體實施例的BOL互連結構可以根據本發明數個方法中任何一項來產生，並不需要使用焊料遮罩。一般而言，互連凸塊(通常為焊料凸塊)係附加在晶粒之作用側的互連焊墊上。基板的晶粒黏著表面(稱為「上方」表面)具有圖案化的上方金屬層，以在特定晶粒上視需要提供和凸塊配置互連的接線。由於不需要使用捕獲焊墊，圖案化的接線(引線)只需要透過晶粒上和互補於凸塊配置之圖案對應的位置來配線。在本發明的較佳方法中，會採用封裝樹脂黏著劑以限制焊料在互連程序之熔化階段期間的流動。
圖8及9根據本發明的另一項具體實施例，顯示引線上凸塊之倒裝晶片互連之部分的兩個範例，其係為截取自和基板表面平行之平面的截面圖。特定特徵顯示猶如透明。根據本發明的此方面，會提供一焊料遮罩，其具有介於約80 um至90 um的標稱遮罩開口直徑。在此間距可解決焊料遮罩材料，尤其，可以比較便宜的方式製造具有含90 um開口及對準公差加減25 um之焊料遮罩的基板。在部分具體實施例中，可以使用根據標準設計規則所製造的層板基板(如4個金屬層層板)。例如，在圖8及9的具體實施例中，接線的間距可以是~90 um及互連位置的區域陣列可以是270 um，以提供橫跨晶粒覆蓋區的邊緣(如虛線81所示)之有效的散逸間距~90 um。
在如圖8及9的具體實施例中，不需要使用非流動的側填滿；可以採用習用的毛細管側填滿。
在如圖8的具體實施例中，在基板82之晶粒黏著表面的介電層上圖案化的窄引線或接線83上，將凸塊直接嚙合在互連位置84上，即可達到互連；其中並沒有焊墊，及焊料遮罩86 可用來限制焊料在遮罩開口88之界限內的流動，以防止焊料沿著焊料可濕性引線流動離開互連位置。此焊料遮罩另外可限制熔化的焊料在引線之間流動，或是這可在裝配程序的過程中完成。
在圖9的具體實施例中，如圖8，根據本發明，其中並沒有互連焊墊。在基板92的晶粒黏著表面上，會圖案化介電層上的窄引線或接線93。焊料膏係提供於引線93上的互連位置94，以提供用於互連的易熔媒介。焊料遮罩96 中的開口98可用來定義焊料膏。焊料膏可藉由如標準印刷程序塗上，然後回熔，然後視需要再加以鑄造，以提供配合球的均勻表面。如上述參考圖8，可在利用基板的裝配過程中塗上焊料膏；或可在裝配之前提供具有適當圖案化之焊料膏的基板。其他將焊料選擇性塗上互連位置的方法可用於本發明之具體實施例的引線上焊料，包括無電電鍍及電鍍技術。引線上焊料組態可提供額外用於互連的焊料量，因此能提供較高的產品良率，及也能提供較高的晶粒凸出物。
因此，在部分具體實施例中，根據本發明的引線上焊料組態可用於具有高熔化溫度焊料凸塊(如高鉛焊料，照慣例用於和陶瓷基板的互連)之晶粒和有機基板的互連。可以選擇具有熔化溫度夠低致使有機基板在回熔期間不會損壞的焊料膏。為了在此種具體實施例中形成互連，會將高熔化互連凸塊和引線上焊料位置接觸，且再熔化可將引線上焊料熔接至凸塊。和引線上焊料程序一起使用不可壓扁的凸塊時，不需要事先塗上黏著劑，因為各互連只有少量焊料的事實可限制焊料的取代或流動，因而不可壓扁的凸塊可防止裝配件跨掉。
在其他具體實施例中，根據本發明的引線上焊料組態可用於具有共熔焊料凸塊之晶粒的互連。
形成引線上凸塊互連之較佳方法的一項具體實施例如圖10A至10C所示。
參考圖式，會提供具有至少一介電層及在晶粒黏著表面113上具有金屬層的基板112，可將金屬層圖案化以提供電路，尤其接線或引線114在晶粒黏著表面上具有用於互連的位置。基板112係固定於載體或平台116上，其中基板表面對置面對固定體的晶粒黏著表面113。會將大量封裝樹脂122塗在基板的晶粒黏著表面113上，以覆蓋至少引線114上的互連位置。會在作用側103上，提供具有黏在晶粒焊墊上(圖中未顯示)之凸塊104的晶粒102。此凸塊包括可接觸引線之嚙合表面的易熔材料。取放工具108包括夾頭106，其可將夾頭106和晶粒的背面101接觸而拾取晶粒。利用拾取工具，可將晶粒放置面對基板，其中晶粒的作用側對著基板的晶粒黏著表面，如圖10A所示；及會將晶粒與基板彼此對準移動(箭頭M)，致使凸塊104接觸基板之接線(引線)114上的對應互連位置。然後會施力(箭頭F)，將凸塊105壓在引線115上互連位置的嚙合表面134上，如圖10B所示。該力必須足夠，至少可取代引線114上互連位置之凸塊及嚙合表面間的黏著劑122。凸塊會因此力而變形，使得凸塊之接觸表面及/或引線的嚙合表面上的氧化膜破裂。凸塊的變形會使凸塊的易熔材料壓在引線的頂部及其邊緣上。如藉由加熱至選定的溫度，可使黏著劑固化至少部分，如132所示。在此階段，黏著劑只需要部分固化，亦即，只要到達以下程度即可：實質上足以防止熔化的焊料沿著黏著劑及導電接線之間的介面流動。然後會熔化凸塊105的易熔材料，然後再重新凝固，以在凸塊105及引線115之間形成冶金互連，因而完成黏著劑固化，以完成晶粒黏著及穩固嚙合表面(現為互連介面)144的電互連，如圖10C的140概括所示。在圖10C所示截面圖的平面中，在特定引線155上，在特定凸塊145及對應的互連位置之間會形成互連，如圖6的組態所示。其他引線156係在其他位置互連，該等位置可見於其他截面圖中。所示為比較高的接線密度。黏著劑的固化可在熔化焊料之前、同時或之後完成。通常，黏著劑為可熱固化黏著劑，及藉由調整溫度，即可在程序中控制任何階段的固化程度。例如，藉由升高取放工具上之夾頭的溫度或基板固定體的溫度，即可加熱及固化成分。
此程序將在圖11A至11D中進一步詳細顯示。在圖11A中，會在晶粒黏著表面上提供具有導電(金屬)接線214的基板212，及會以黏著劑222覆蓋接線上的互連位置。晶粒202的位置和基板212的關係致使晶粒的作用側面對基板的晶粒黏著側，及其對準(箭頭A)致使晶粒上的凸塊204和接線214上對應的嚙合表面對準。晶粒及基板會移向彼此，致使凸塊接觸接線上的個別嚙合表面。然後，如圖11B所示，會施力以使凸塊205及接線215移向彼此，以取代圖11B之232所示的黏著劑，然後使凸塊在嚙合表面234及接線的邊緣上變形。接線上凸塊的變形會使凸塊之接觸表面及接線之嚙合表面上的氧化膜斷裂，以建立良好的電連接，及接線邊緣上凸塊的變形有助於建立良好的暫時機械連接。如圖10A至10C中的範例，特定接線216的互連位置會脫離圖11B的平面。會加熱以部分固化黏著劑，如圖11C的236所示。然後會加熱以升高凸塊的溫度，以足夠使凸塊的易熔材料熔化，如圖11D所示。這實質上(但不一定完全)可完成黏著劑246的固化，及在引線215的互連位置，完成凸塊245冶金互連至嚙合表面244上。已固化的黏著劑可穩定晶粒黏著。
在較佳方法的替代具體實施例中，可預先將黏著劑塗在晶粒表面上，或至少塗在晶粒表面的凸塊上，而非塗在基板上。例如，可將黏著劑裝在貯存器中，然後將晶粒的作用側浸入黏著劑再取出，致使凸塊上載有大量的黏著劑；然後，利用拾取工具將晶粒放置面對固定的基板，其中晶粒的作用側對著基板的晶粒黏著表面，然後對準晶粒及基板並使其移向彼此，致使凸塊接觸基板上對應的接線(引線)。此種方法說明於2004年8月24日的美國專利第6,780,682號，其內容在此以引用的方式併入本文中。然後如上述執行施力、固化、及熔化。
根據本發明之程序的力及溫度排程如圖12舉例所示。在此圖中，時間在水平軸上從左向右進展；力的輪廓310係顯示為粗線，及溫度輪廓320係顯示為虛線。溫度輪廓始於介於約80℃至約90℃的溫度。力的輪廓實質上始於零力。從初始時間ti 開始，力迅速(幾乎馬上)從Fi 升高312為取代/變形力Fd 並保持314在該力一段時間，如下文所述。Fd 是大到足以取代凸塊及引線嚙合表面間之黏著劑的力；及較佳，足以使凸塊的易熔(引線接觸)部分在嚙合表面上變形，使氧化膜斷裂及形成良好的金屬對金屬(冶金)接觸，以及，在部分具體實施例中，足以在引線的邊緣上建立凸塊及引線的機械連鎖(「扭曲」變形)。所需要的總力量取決於凸塊材料及尺寸，及取決於凸塊的數量，且不用過度實驗即可決定。隨著力的升高，溫度也會從初始的溫度Ti 迅速升高322至凝膠溫度Tg 。凝膠溫度Tg 是足以部分固化黏著劑(成為「凝膠」)的溫度。力及溫度斜面的設定較佳致使達到Fd 之後及達到Tg 之前的滯後時間tdef 很短，至少長到足以在黏著劑的局部固化開始之前，允許升高的力取代黏著劑及使凸塊變形。此裝配件會保持314、324在取代/變形壓力Fd 及凝膠溫度Tg 一段時間tgel ，以足夠實現黏著劑的局部固化。黏著劑應該變得夠穩固，使其在焊料重新熔化階段期間實質上維持良好的凸塊輪廓，亦即，夠穩固以免不必要地取代凸塊之熔化的易熔材料，或防止熔化的易熔材料沿著引線流動。在黏著劑部分固化至足夠的程度後，壓力會迅速下降318至實質上沒有任何力(成分的重量)。然後溫度會進一步升高323至溫度Tm ，以足夠重新熔化凸塊的易熔部分(焊料)，將裝配件保持325於重新熔化的溫度Tm 一段時間tmelt/cure ，至少足以在接線上完全形成焊料重新熔化，及較佳足以實質上(但不一定完全)固化黏著劑。然後，溫度會下降328至初始溫度Ti ，最後降至室溫。圖12所示程序執行其過程的時間週期為5-10秒。
如圖12之具體實施例的黏著劑可稱為「非流動側填滿」。在一些倒裝晶片互連的方法中，會先形成冶金互連，然後再讓側填滿材料流入晶粒及基板間的間隔。根據本發明的「非流動側填滿」可在將晶粒及基板接合一起前塗上，及藉由引線上凸塊的方法，及藉由晶粒及基板的對置表面，即可取代非流動側填滿。根據本發明之非流動側填滿黏著劑的黏著劑較佳為快速膠化黏著劑，亦即，在凝膠溫度持續1-2秒等級的時間週期膠化足夠的材料。非流動側填滿黏著劑的較佳材料包括如所謂的「非導電焊料膏」，如Toshiba Chemicals及Loktite-Henkel所銷售的黏著劑。
在根據本發明的引線上凸塊互連中也可以採用替代的凸塊結構。尤其，例如，可以使用所謂的「合成焊料凸塊」。合成焊料凸塊具有至少兩個凸塊部分(以不同的凸塊材料製成)，其包括在回熔條件下可壓扁的部分，及在回熔條件下實質上不可壓扁的部分。不可壓扁的部分係黏在晶粒的互連位置上；用於不可壓扁部分的典型習用材料包括各種具有高鉛(Pb)內容的焊料。可將可壓扁的部分和不可壓扁的部分相結合，及可壓扁的部分可形成和根據本發明之引線的連接。合成凸塊之可壓扁部分的典型習用材料包括如共熔焊料。
引線上凸塊互連的範例係採用如圖13之截面圖所示的合成凸塊。現在參考圖13，在晶粒之作用側中晶粒焊墊上所提供的晶粒302 具有包括不可壓扁的部分345及可壓扁的部分347的合成凸塊。可壓扁的部分如共熔焊料或相對的低溫熔化的焊料。可壓扁的部分可接觸引線的嚙合表面，在此，需要引線上凸塊之易熔部分的變形，凸塊的可壓扁的部分在施力的條件下會變形。不可壓扁的部分如具有高鉛(Pb)內容的焊料。不可壓扁的部分在晶粒於處理期間受壓移向基板時不會變形，且在程序的回熔階段期間不會熔化。因此，不可壓扁的部分具有的尺寸可在晶粒之作用表面及基板之晶粒黏著表面之間提供凸出物距離。
應明白，如圖4、5、6及7所示具體實施例的凸塊不一定要是完全可壓扁的凸塊。在這些圖式中顯示的結構可另外利用合成凸塊來製造，或利用如所說明的引線上焊料方法來製造。
其他具體實施例屬於以下申請專利範圍內。
10,20,30‧‧‧習用倒裝晶片封裝的部分
11‧‧‧晶粒邊絕位置
12‧‧‧介電層/基板
12 ‧‧‧基板
13‧‧‧引線
14‧‧‧捕獲焊墊
15‧‧‧互連凸塊
16 ‧‧‧絕緣層
17 ‧‧‧底部填膠材料
18 ‧‧‧晶粒
19‧‧‧焊料遮罩
29‧‧‧流動的凸塊材料
32 ‧‧‧基板
33‧‧‧引線
34‧‧‧捕獲焊墊
35‧‧‧凸塊
37 ‧‧‧底部填膠材料
38 ‧‧‧晶粒
39‧‧‧焊料遮罩材料
40．．．本發明之倒裝晶片封裝的部分
41．．．互連位置
42 ．．．基板介電層
43．．．引線/散逸接線
45．．．凸塊
48 ．．．晶粒
61．．．互連位置/信號散逸接線
62 ．．．基板介電層
63．．．引線/散逸接線
65．．．凸塊
66．．．散逸接線
68 ．．．晶粒
81．．．晶粒覆蓋區邊緣
82．．．基板
83．．．引線/接線
84．．．互連位置
86 ．．．焊料遮罩
88．．．遮罩開口
92．．．基板
93．．．引線/接線
94．．．互連位置
96 ．．．焊料遮罩
98．．．開口
101．．．晶粒背面
102．．．晶粒
103．．．作用側
104．．．凸塊
105．．．凸塊
106．．．夾頭
108．．．取放工具
112．．．基板
113．．．晶粒黏著表面
114．．．引線/接線
115．．．引線
116．．．載體或平台
122．．．黏著劑
132．．．黏著劑固化部分
134．．．嚙合表面
140．．．完成的倒裝晶片互連
144．．．嚙合表面
145．．．凸塊
155．．．引線
156．．．引線
202．．．晶粒
204．．．凸塊
205．．．凸塊
212．．．基板
214．．．導電(金屬)接線
215．．．引線/接線
216．．．接線
222．．．黏著劑
232．．．黏著劑
234．．．嚙合表面
236．．．黏著劑固化部分
244．．．嚙合表面
245．．．凸塊
246．．．黏著劑
302 ．．．晶粒
310．．．力的輪廓
312．．．力的輪廓之升高
314．．．力的輪廓之保持
318．．．力的輪廓之下降
320．．．溫度輪廓
322．．．溫度輪廓之升高
323．．．溫度輪廓之升高
324．．．溫度輪廓之保持
325．．．溫度輪廓之保持
328．．．溫度輪廓之下降
345．．．不可壓扁的部分
347．．．可壓扁的部分
圖1為習用之捕獲焊墊上凸塊之倒裝晶片互連之部分的示意圖，其係為和封裝基板表面平面平行的截面圖，如圖2中的箭頭1-1'所示。
圖2為顯示習用之捕獲焊墊上凸塊之倒裝晶片互連之部分的示意圖，其係為和封裝基板表面平面垂直的截面圖，如圖1中的箭頭2-2'所示。
圖3為顯示另一個習用之捕獲焊墊上凸塊之倒裝晶片互連之部分的示意圖，其係為和封裝基板表面平面垂直的截面圖。
圖4為根據本發明之引線上凸塊之倒裝晶片互連之一項具體實施例之部分的示意圖，其係為和封裝基板表面平面平行的截面圖。
圖5為根據如圖4的本發明顯示引線上凸塊之倒裝晶片互連之一項具體實施例之部分的示意圖，其係為和封裝基板表面平面垂直的截面圖，如圖4中的箭頭5-5'所示。
圖6為根據本發明之引線上凸塊之倒裝晶片互連之另一項具體實施例之部分的示意圖，其係為和封裝基板表面平面平行的截面圖。
圖7為根據如圖6的本發明顯示引線上凸塊之倒裝晶片互連之一項具體實施例之部分的示意圖，其係為和封裝基板表面平面垂直的截面圖，如圖6中的箭頭7-7'所示。
圖8及9為根據本發明之引線上凸塊之倒裝晶片互連之另一項具體實施例之各部分的示意圖，其係為和封裝基板表面平面平行的截面圖。
圖10A至10C以截面圖顯示用於形成根據本發明之倒裝晶片互連之程序步驟的示意圖。
圖11A至11D以截面圖顯示用於形成根據本發明之倒裝晶片互連之程序步驟的示意圖。
圖12為顯示用於形成根據本發明之倒裝晶片互連之程序之力及溫度排程的示意圖。
圖13以截面圖顯示具有合成凸塊之根據本發明之引線上凸塊之倒裝晶片互連的示意圖。
40．．．本發明之倒裝晶片封裝的部分
41．．．互連位置
42 ．．．基板介電層
43．．．引線
45．．．凸塊

Claims (55)

  1. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒；提供一具有接線之基板，該接線包含一互連位置；及於該互連位置以及該半導體晶粒上之一凸塊焊墊之間形成一合成互連，該合成互連具有一可熔部分以及一不可熔部分，該可熔部分相鄰於該接線，該不可熔部分相鄰於該半導體晶粒上之該凸塊焊墊，其中該互連位置在該合成互連下之寬度小於該接線離開該合成互連之寬度的1.2倍。
  2. 如請求項1之方法，其中該合成互連之該不可熔部分包含一含鉛焊料材料。
  3. 如請求項1之方法，其中該合成互連之該可熔部分包含一低熔點焊料材料。
  4. 如請求項1之方法，其中該基板包含一有機基板，其中該合成互連之該可熔部分包含一焊料材料，該焊料材料係於回焊過程中避免該有機基板受損之一溫度下熔化。
  5. 如請求項1之方法，其中該合成互連包含一焊料墊。
  6. 如請求項1之方法，其中該互連位置之邊緣係與該接線平行。
  7. 如請求項1之方法，其中該互連位置在該合成互連下之寬度不大於該接線離開該合成互連之寬度。
  8. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒； 提供一具有接線之基板；於該接線上一互連位置以及該半導體晶粒上之一凸塊焊墊之間形成一合成凸塊材料，該接線在該互連位置處之寬度不大於該接線之一接線設計規則之120%，該合成凸塊材料具有一可熔部分以及一不可熔部分；及回焊(reflow)該合成凸塊材料以在該互連位置以及該半導體晶粒上之一凸塊焊墊之間形成一合成互連，該互連位置定義成該接線之一部分，該部分直接物理接觸該合成互連。
  9. 如請求項8之方法，其中該合成凸塊材料之該不可熔部分包含一含鉛焊料材料。
  10. 如請求項8之方法，其中該合成凸塊材料之該可熔部分包含一低熔點焊料材料。
  11. 如請求項8之方法，其中該基板包含一有機基板，其中該合成凸塊材料之該可熔部分包含一焊料材料，該焊料材料係於回焊過程中避免該有機基板受損之一溫度下熔化。
  12. 如請求項8之方法，其另包含：形成該合成凸塊材料之該可熔部分相鄰於該接線上該互連位置處；及形成該合成凸塊材料之該不可熔部分相鄰於該半導體晶粒上之一凸塊焊墊處。
  13. 一種形成具有改良之散逸繞線密度的引線上凸塊之倒裝晶片互連的方法，其包含： 提供一晶粒；提供一具有接線之封裝基板，該等接線係形成於該封裝基板之晶粒黏合端；將複數個合成凸塊黏著在該晶粒之一主動端的焊墊上，每一合成凸塊包含一不可壓扁凸塊部分以及一可熔凸塊部分，該合成凸塊貼合至該等接線上對應的互連位置，使得該不可壓扁凸塊部分在該焊墊與該接線之間延伸且該可熔凸塊部分熔化以將該不可壓扁凸塊部分固接至該互連位置，該等互連位置之平行邊緣定義一互連位置寬度，該互連位置寬度係小於貼合至該互連位置之該合成凸塊一寬度。
  14. 如請求項13之方法，其另包含：將該等焊墊置成一列，該列靠近該晶粒之一邊緣；及將相對應之該等互連位置置成一列，該列靠近晶粒接腳之一邊緣。
  15. 如請求項13之方法，其另包含：將該等焊墊置成一陣列，該陣列靠近該晶粒之一邊緣；及將相對應之該等互連位置置成一陣列，該陣列靠近晶粒接腳之一邊緣。
  16. 如請求項13之方法，其另包含於該封裝基板之該晶粒黏合端形成一遮罩，該遮罩於該等互連位置處具有數個開口。
  17. 如請求項13之方法，其中該不可壓扁凸塊部分包含鉛焊料。
  18. 如請求項13之方法，其中該可熔凸塊部分包含一焊料，該焊料係於回焊過程中避免該封裝基板受損之一溫度下熔化。
  19. 如請求項13之方法，其中該可熔凸塊部分包含一低熔點焊料。
  20. 一種形成一半導體裝置的方法，其包含：提供一半導體晶粒；於該半導體晶粒上提供複數個凸塊；提供一基板；及於該基板上形成複數個導電接線，每一接線具有一互連位置以與該等凸塊貼合，該等互連位置之平行邊緣的寬度係小於該凸塊之直徑之一半，其中該等凸塊之一者具有一不可壓扁部分及一可熔部分，該不可壓扁部分用於黏至該半導體晶粒上一接觸墊，該可熔部分用於黏至該互連位置。
  21. 如請求項20之方法，其中該不可壓扁部分包含一鉛焊料，該可熔部分包含低熔點焊料。
  22. 如請求項20之方法，其中該可熔部分係於回焊過程中避免該基板受損之一溫度下熔化。
  23. 如請求項20之方法，其中該等凸塊之一者係與該等互連位置之一者的側牆接觸。
  24. 如請求項20之方法，其另包含在該半導體晶粒與基板之 間置入一底部填膠材料。
  25. 如請求項20之方法，其中該互連位置之寬度小於該導電接線寬度的1.2倍。
  26. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒；於該半導體晶粒上形成一凸塊；及提供一具有導電接線之基板，該導電接線係形成於該基板之一晶粒黏合表面上以與該凸塊貼合，該導電接線具有一互連位置，該互連位置之寬度係小於該凸塊之直徑的一半，其中該凸塊具有一不可壓扁部分及一可熔部分，該不可壓扁部分包含用於黏至該半導體晶粒上一接觸墊的鉛焊料，該可熔部分包含用於黏至該互連位置的低熔點焊料。
  27. 如請求項26之方法，其中該可熔部分係於回焊過程中避免該基板受損之一溫度下熔化。
  28. 如請求項28之方法，其另包含在該半導體晶粒與基板之間置入一底部填膠材料。
  29. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒；於該半導體晶粒上形成一凸塊；及提供一具有導電接線之基板，該導電接線係形成於該基板之一晶粒黏合表面上，該導電接線具有一互連位置以與該凸塊貼合，該互連位置之寬度係小於該凸塊之寬度的一半，其中該凸塊具有一不可壓扁部分及一可熔 部分，該不可壓扁部分係用於黏至該半導體晶粒上一接觸墊，該可熔部分係用於黏至該互連位置。
  30. 如請求項29之方法，其中該可熔部分係於回焊過程中避免該基板受損之一溫度下熔化。
  31. 如請求項29之方法，其中該不可壓扁部分包含鉛焊料，且該可熔部分包含低熔點焊料。
  32. 如請求項29之方法，其中該凸塊係與該互連位置之一側牆接觸。
  33. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒；於該半導體晶粒之一表面上形成複數個凸塊，該凸塊包含一不可壓扁部分及一可熔部分；提供一基板；形成複數條導電接線，其包含該基板之一表面上之多個互連位置，其中該等互連位置之寬度係小於該等凸塊之寬度的一半；及藉由使該可熔部分在該等互連位置上形變，以將該等凸塊之該可熔部分固接至該等互連位置之一表面，而該等凸塊之該不可壓扁部分在該半導體晶粒與該基板間維持垂直支座(standoff)。
  34. 如請求項33之方法，其中該等凸塊之該不可壓扁部分包含鉛焊料，以用於黏至該半導體晶粒之一接觸焊墊，且該等凸塊之該可熔部分包含低熔點焊料，以用於黏至該等互連位置之一表面。
  35. 如請求項33之方法，其另包含在該半導體晶粒與基板之間置入一底部填膠材料。
  36. 如請求項33之方法，其中該等凸塊之一者的該可熔部分係與該等互連位置之一者的側牆接觸。
  37. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒；於該半導體晶粒之一表面上形成一凸塊，該凸塊包含一不可壓扁部分及一可熔部分；提供一基板；於該基板之一表面上形成一互連位置，其中該互連位置之寬度係小於該凸塊之寬度的一半；及將該凸塊之該可熔部分固接至該互連位置之一表面，而該凸塊之該不可壓扁部分在該半導體晶粒與該基板間維持垂直支座。
  38. 如請求項37之方法，其中該凸塊之該不可壓扁部分包含鉛焊料，以用於黏至該半導體晶粒之一接觸焊墊。
  39. 如請求項37之方法，其中該凸塊之該可熔部分包含低熔點焊料，以用於黏至該互連位置之該表面。
  40. 如請求項37之方法，其另包含在該半導體晶粒與基板之間置入一底部填膠材料。
  41. 如請求項37之方法，其中該凸塊之該可熔部分係與該互連位置之側牆接觸。
  42. 一種製造一半導體裝置的方法，其包含：提供一半導體晶粒； 提供具有一互連位置之一基板，該互連位置係形成於該基板之一表面上；提供一凸塊，該凸塊具有一不可壓扁部分及一可熔部分，其中該互連位置之寬度係小於該凸塊之寬度的一半；及將該凸塊固接至該基板之該表面與該互連位置之一表面之間，該凸塊之該不可壓扁部分在該半導體晶粒與該基板間維持垂直支座。
  43. 如請求項42之方法，其中該凸塊之該不可壓扁部分包含鉛焊料，以用於黏至該半導體晶粒之一接觸焊墊。
  44. 如請求項42之方法，其中該凸塊之該可熔部分包含低熔點焊料，以用於黏至該互連位置之該表面。
  45. 如請求項42之方法，其另包含在該半導體晶粒與基板之間置入一底部填膠材料。
  46. 如請求項42之方法，其中該凸塊之該可熔部分係與該互連位置之側牆接觸。
  47. 一種半導體裝置，其包含：一半導體晶粒；複數個凸塊，其係形成於該半導體晶粒上；一基板；及形成於該基板上之複數條導電接線，每一接線具有一互連位置以與該等凸塊貼合，該等互連位置之平行邊緣之寬度係小於該等凸塊寬度之一半，其中該等凸塊之一者具有一不可壓扁部分及一可熔部分，該不可壓扁部 分係用於黏至該半導體晶粒之一接觸焊墊，該可熔部份係用於黏至該互連位置。
  48. 如請求項47之半導體裝置，其中該不可壓扁部分包含鉛焊料。
  49. 如請求項47之半導體裝置，其中該可熔部分包含低熔點焊料。
  50. 如請求項47之半導體裝置，其中該等互連位置之寬度係小於該導電接線之寬度的1.2倍。
  51. 如請求項47之半導體裝置，其中該等凸塊之一間距係由該基板上可達到之相鄰導電接線之最小距離來決定。
  52. 一種半導體裝置，其包含：一半導體晶粒；一具有一互連位置之基板，該互連位置係形成於該基板之一表面上；及一凸塊，其具有一不可壓扁部分及一可熔部分，其中該凸塊係固接於該互連位置與該半導體晶粒之間，該該凸塊之該不可壓扁部分在該半導體晶粒與該基板間維持垂直支座，其中該互連位置之一接線的寬度係小於該凸塊寬度之一半。
  53. 如請求項52之半導體裝置，其中該凸塊之該不可壓扁部分包含用於黏至該半導體晶粒之一接觸焊墊的鉛焊料，該凸塊之該可熔部份包含用於黏至該互連位置之一表面之低熔點焊料。
  54. 如請求項52之半導體裝置，其另包含在該半導體晶粒與 基板之間的一底部填膠材料。
  55. 如請求項52之半導體裝置，其中該凸塊之該可熔部分係與該互連位置之側牆接觸。
TW101111925A 2003-11-10 2004-11-10 引線上凸塊之倒裝晶片互連 TWI478254B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51886403P 2003-11-10 2003-11-10
US53391803P 2003-12-31 2003-12-31

Publications (2)

Publication Number Publication Date
TW201237976A TW201237976A (en) 2012-09-16
TWI478254B true TWI478254B (zh) 2015-03-21

Family

ID=34594933

Family Applications (3)

Application Number Title Priority Date Filing Date
TW093134366A TWI378516B (en) 2003-11-10 2004-11-10 Bump-on-lead flip chip interconnection
TW101111925A TWI478254B (zh) 2003-11-10 2004-11-10 引線上凸塊之倒裝晶片互連
TW101133048A TWI534915B (zh) 2003-11-10 2004-11-10 引線上凸塊之倒裝晶片互連

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW093134366A TWI378516B (en) 2003-11-10 2004-11-10 Bump-on-lead flip chip interconnection

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW101133048A TWI534915B (zh) 2003-11-10 2004-11-10 引線上凸塊之倒裝晶片互連

Country Status (5)

Country Link
US (10) US7368817B2 (zh)
JP (1) JP4928945B2 (zh)
KR (3) KR101249555B1 (zh)
TW (3) TWI378516B (zh)
WO (1) WO2005048311A2 (zh)

Families Citing this family (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8674500B2 (en) * 2003-12-31 2014-03-18 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
KR101249555B1 (ko) 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8076232B2 (en) 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US7521781B2 (en) * 2005-04-25 2009-04-21 Stats Chippac Ltd. Integrated circuit package system with mold clamp line critical area having widened conductive traces
US8154131B2 (en) 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7560813B2 (en) 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7494924B2 (en) * 2006-03-06 2009-02-24 Freescale Semiconductor, Inc. Method for forming reinforced interconnects on a substrate
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US20080123335A1 (en) * 2006-11-08 2008-05-29 Jong Kun Yoo Printed circuit board assembly and display having the same
US8081484B2 (en) 2006-11-30 2011-12-20 Cisco Technology, Inc. Method and apparatus for supporting a computer chip on a printed circuit board assembly
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US20080246147A1 (en) * 2007-04-09 2008-10-09 Chao-Yuan Su Novel substrate design for semiconductor device
KR100871710B1 (ko) * 2007-04-25 2008-12-08 삼성전자주식회사 플립 칩 패키지 및 그 패키지 제조방법
US8604624B2 (en) * 2008-03-19 2013-12-10 Stats Chippac Ltd. Flip chip interconnection system having solder position control mechanism
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) * 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US20100096754A1 (en) * 2008-10-17 2010-04-22 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor module, and method for fabricating the semiconductor package
US8659172B2 (en) 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
KR101632399B1 (ko) * 2009-10-26 2016-06-23 삼성전자주식회사 반도체 패키지 및 그 제조방법
US8420950B2 (en) * 2010-03-02 2013-04-16 Stats Chippac Ltd. Circuit system with leads and method of manufacture thereof
US8367467B2 (en) * 2010-04-21 2013-02-05 Stats Chippac, Ltd. Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process
US8241964B2 (en) 2010-05-13 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
US8228682B1 (en) * 2010-08-20 2012-07-24 Xilinx, Inc. Electronic assembly with trenches for underfill material
US8435834B2 (en) * 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US8642446B2 (en) 2010-09-27 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming protective structure around semiconductor die for localized planarization of insulating layer
WO2012056661A1 (ja) * 2010-10-25 2012-05-03 パナソニック株式会社 電子部品の接合形態
TWI527178B (zh) * 2010-12-15 2016-03-21 史達晶片有限公司 在無焊料遮罩的回焊期間的導電凸塊材料的自我局限的半導體裝置和方法
US8673761B2 (en) * 2011-02-19 2014-03-18 International Business Machines Corporation Reflow method for lead-free solder
JP5127946B2 (ja) * 2011-03-31 2013-01-23 株式会社東芝 電子機器、電子部品、および基板アセンブリの製造方法
US20120267779A1 (en) * 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US8441127B2 (en) * 2011-06-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace structures with wide and narrow portions
US9024438B2 (en) 2011-07-28 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligning conductive bump structure and method of making the same
US8598691B2 (en) 2011-09-09 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing and packaging thereof
DE112012004185T5 (de) * 2011-10-07 2014-06-26 Volterra Semiconductor Corp. Leistungsmanagements-Anwendungen von Zwischenverbindungssubstraten
US9786622B2 (en) * 2011-10-20 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US9978656B2 (en) * 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
US9466696B2 (en) 2012-01-24 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9281378B2 (en) 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US9171925B2 (en) 2012-01-24 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices with replaced-channels and methods for forming the same
CN104221480B (zh) 2012-04-19 2017-09-08 松下知识产权经营株式会社 电子零件安装方法及电子零件安装线
US9202714B2 (en) 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US8970034B2 (en) 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures
US9177899B2 (en) * 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US9287245B2 (en) 2012-11-07 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Contoured package-on-package joint
US9349837B2 (en) 2012-11-09 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase Fin height in Fin-first process
US9443962B2 (en) 2012-11-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase fin height in fin-first process
US9773724B2 (en) 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
US9609752B1 (en) 2013-03-15 2017-03-28 Lockheed Martin Corporation Interconnect structure configured to control solder flow and method of manufacturing of same
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
WO2015092579A1 (en) 2013-12-18 2015-06-25 Koninklijke Philips N.V. Reflective solder mask layer for led phosphor package
US9275967B2 (en) 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9508637B2 (en) * 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9305890B2 (en) 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
EP2940729A1 (en) 2014-04-28 2015-11-04 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic assembly comprising a carrier structure made from a printed circuit board
KR101640773B1 (ko) * 2014-09-15 2016-07-19 (주) 에스에스피 전자파 차폐막을 구비한 반도체 패키지의 제조 방법 및 이를 위한 장치
CN104393097B (zh) * 2014-09-30 2017-02-08 中国空空导弹研究院 一种铟柱倒焊互连的方法
US9859200B2 (en) 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
KR101614721B1 (ko) * 2015-03-24 2016-04-22 (주)씨앤아이테크놀로지 점착패드를 이용하여 전자파 차폐막 형성을 위한 반도체 패키지 부착 및 분리 방법
KR101689018B1 (ko) * 2015-04-28 2016-12-22 (주) 씨앤아이테크놀로지 포켓을 이용한 반도체 패키지의 전자파 차폐막 형성 방법
KR101662069B1 (ko) * 2015-09-18 2016-10-10 (주) 씨앤아이테크놀로지 반도체 패키지의 전자파 차폐막 형성 방법
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
TWI607327B (zh) * 2015-12-25 2017-12-01 矽創電子股份有限公司 半導體元件
US10531575B2 (en) 2016-04-01 2020-01-07 Intel Corporation Systems and methods for replaceable bail grid array (BGA) packages on board substrates
US10504827B2 (en) 2016-06-03 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10037970B2 (en) * 2016-09-08 2018-07-31 Nxp Usa, Inc. Multiple interconnections between die
KR20180137888A (ko) 2017-06-20 2018-12-28 주식회사 프로텍 반도체 칩 본딩 장치 및 반도체 칩 본딩 방법
US20190067232A1 (en) 2017-08-31 2019-02-28 Micron Technology, Inc. Method for Solder Bridging Elimination for Bulk Solder C2S Interconnects
CN109671693A (zh) * 2017-10-16 2019-04-23 矽创电子股份有限公司 电路引脚结构
KR102456322B1 (ko) * 2017-11-08 2022-10-19 삼성전기주식회사 기판 스트립 및 이를 포함하는 전자소자 패키지
KR102555721B1 (ko) 2018-08-20 2023-07-17 삼성전자주식회사 플립 칩 본딩 방법
DE102020135088A1 (de) 2020-03-27 2021-09-30 Samsung Electronics Co., Ltd. Halbleitervorrichtung
US11404390B2 (en) * 2020-06-30 2022-08-02 Micron Technology, Inc. Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
KR20220034596A (ko) 2020-09-11 2022-03-18 삼성전자주식회사 반도체 패키지

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5519580A (en) * 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
JPH11145176A (ja) * 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
JP2001156203A (ja) * 1999-11-24 2001-06-08 Matsushita Electric Works Ltd 半導体チップ実装用プリント配線板
US6383916B1 (en) * 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
US6409073B1 (en) * 1998-07-15 2002-06-25 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method for transfering solder to a device and/or testing the device
JP2002270732A (ja) * 2001-03-13 2002-09-20 Sharp Corp アンダーフィル材付き電子部品
US6458622B1 (en) * 1999-07-06 2002-10-01 Motorola, Inc. Stress compensation composition and semiconductor component formed using the stress compensation composition
TW530398B (en) * 2002-03-19 2003-05-01 Chipmos Technologies Inc Method for manufacturing bumps of chip scale package (CSP)

Family Cites Families (231)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719737B2 (ja) 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JPH04355933A (ja) 1991-02-07 1992-12-09 Nitto Denko Corp フリツプチツプの実装構造
US5186383A (en) 1991-10-02 1993-02-16 Motorola, Inc. Method for forming solder bump interconnections to a solder-plated circuit trace
US5219117A (en) 1991-11-01 1993-06-15 Motorola, Inc. Method of transferring solder balls onto a semiconductor device
US5383916A (en) 1991-11-12 1995-01-24 Puretan International, Inc. Support member for a tanning bed or comparable device
JP2678958B2 (ja) * 1992-03-02 1997-11-19 カシオ計算機株式会社 フィルム配線基板およびその製造方法
US5314651A (en) * 1992-05-29 1994-05-24 Texas Instruments Incorporated Fine-grain pyroelectric detector material and method
JP3152796B2 (ja) 1993-05-28 2001-04-03 株式会社東芝 半導体装置およびその製造方法
US5386624A (en) * 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
US5772451A (en) 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
US5427382A (en) 1994-05-09 1995-06-27 Pate; Elvis O. Repair kit for three-dimensional animal targets
JP3353508B2 (ja) * 1994-12-20 2002-12-03 ソニー株式会社 プリント配線板とこれを用いた電子装置
JPH08236654A (ja) 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
US5650595A (en) * 1995-05-25 1997-07-22 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
US5796591A (en) 1995-06-07 1998-08-18 International Business Machines Corporation Direct chip attach circuit card
EP0747954A3 (en) 1995-06-07 1997-05-07 Ibm Solder ball comprising a metal cover with low melting point
JPH0997791A (ja) * 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US5697148A (en) 1995-08-22 1997-12-16 Motorola, Inc. Flip underfill injection technique
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
KR0182073B1 (ko) * 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JPH09260552A (ja) * 1996-03-22 1997-10-03 Nec Corp 半導体チップの実装構造
JP2751912B2 (ja) 1996-03-28 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
KR100216839B1 (ko) * 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US5854514A (en) * 1996-08-05 1998-12-29 International Buisness Machines Corporation Lead-free interconnection for electronic devices
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5729896A (en) * 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
US5775569A (en) 1996-10-31 1998-07-07 Ibm Corporation Method for building interconnect structures by injection molded solder and structures built
US5796590A (en) 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
US5894173A (en) 1996-11-27 1999-04-13 Texas Instruments Incorporated Stress relief matrix for integrated circuit packaging
US5795818A (en) 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
KR100467897B1 (ko) 1996-12-24 2005-01-24 닛토덴코 가부시키가이샤 반도체 장치 및 이의 제조방법
US6002172A (en) 1997-03-12 1999-12-14 International Business Machines Corporation Substrate structure and method for improving attachment reliability of semiconductor chips and modules
JP3500032B2 (ja) 1997-03-13 2004-02-23 日本特殊陶業株式会社 配線基板及びその製造方法
JPH10270496A (ja) 1997-03-27 1998-10-09 Hitachi Ltd 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法
JP3346263B2 (ja) * 1997-04-11 2002-11-18 イビデン株式会社 プリント配線板及びその製造方法
WO1999000842A1 (en) * 1997-06-26 1999-01-07 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
JPH1126919A (ja) * 1997-06-30 1999-01-29 Fuji Photo Film Co Ltd プリント配線板
US6070321A (en) 1997-07-09 2000-06-06 International Business Machines Corporation Solder disc connection
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5985456A (en) * 1997-07-21 1999-11-16 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
US6441473B1 (en) 1997-09-12 2002-08-27 Agere Systems Guardian Corp. Flip chip semiconductor device
US6335222B1 (en) 1997-09-18 2002-01-01 Tessera, Inc. Microelectronic packages with solder interconnections
US6448665B1 (en) * 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
JP3819576B2 (ja) * 1997-12-25 2006-09-13 沖電気工業株式会社 半導体装置及びその製造方法
US6326241B1 (en) 1997-12-29 2001-12-04 Visteon Global Technologies, Inc. Solderless flip-chip assembly and method and material for same
US6303408B1 (en) * 1998-02-03 2001-10-16 Tessera, Inc. Microelectronic assemblies with composite conductive elements
JPH11233571A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びアンダーフィル材並びに熱硬化性フィルム材
US6324754B1 (en) * 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
US6329605B1 (en) * 1998-03-26 2001-12-11 Tessera, Inc. Components with conductive solder mask layers
US6297564B1 (en) 1998-04-24 2001-10-02 Amerasia International Technology, Inc. Electronic devices employing adhesive interconnections including plated particles
JPH11330162A (ja) 1998-05-19 1999-11-30 Sony Corp 半導体チップの実装方法
JP2000031204A (ja) 1998-07-07 2000-01-28 Ricoh Co Ltd 半導体パッケージの製造方法
JP3420076B2 (ja) 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
DE19839760A1 (de) 1998-09-01 2000-03-02 Bosch Gmbh Robert Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung
JP2000133667A (ja) 1998-10-22 2000-05-12 Citizen Watch Co Ltd 突起電極の形成方法
JP2000133672A (ja) * 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP3346320B2 (ja) * 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
JP4024958B2 (ja) * 1999-03-15 2007-12-19 株式会社ルネサステクノロジ 半導体装置および半導体実装構造体
US6556268B1 (en) 1999-03-31 2003-04-29 Industrial Technology Research Institute Method for forming compact LCD packages and devices formed in which first bonding PCB to LCD panel and second bonding driver chip to PCB
JP4121665B2 (ja) 1999-04-19 2008-07-23 株式会社ルネサステクノロジ 半導体基板の接合方法
US6268568B1 (en) 1999-05-04 2001-07-31 Anam Semiconductor, Inc. Printed circuit board with oval solder ball lands for BGA semiconductor packages
US6225206B1 (en) 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
JP2000323534A (ja) 1999-05-13 2000-11-24 Sony Corp 半導体素子の実装構造及び実装方法
JP2000349194A (ja) 1999-06-08 2000-12-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
US6122171A (en) 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
JP2001068836A (ja) * 1999-08-27 2001-03-16 Mitsubishi Electric Corp プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法
US6303400B1 (en) 1999-09-23 2001-10-16 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
TW429492B (en) * 1999-10-21 2001-04-11 Siliconware Precision Industries Co Ltd Ball grid array package and its fabricating method
US6774474B1 (en) 1999-11-10 2004-08-10 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
JP3865989B2 (ja) 2000-01-13 2007-01-10 新光電気工業株式会社 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置
US20010012644A1 (en) 2000-01-14 2001-08-09 I-Ming Chen Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate
JP2001230339A (ja) 2000-02-18 2001-08-24 Nec Corp 半導体装置
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
JP2001313314A (ja) 2000-04-28 2001-11-09 Sony Corp バンプを用いた半導体装置、その製造方法、および、バンプの形成方法
US6661084B1 (en) 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
JP2001332583A (ja) 2000-05-22 2001-11-30 Fujitsu Ltd 半導体チップの実装方法
US6573610B1 (en) * 2000-06-02 2003-06-03 Siliconware Precision Industries Co., Ltd. Substrate of semiconductor package for flip chip package
US6787918B1 (en) * 2000-06-02 2004-09-07 Siliconware Precision Industries Co., Ltd. Substrate structure of flip chip package
JP2001351945A (ja) 2000-06-05 2001-12-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6201305B1 (en) * 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
JP3506233B2 (ja) 2000-06-28 2004-03-15 シャープ株式会社 半導体装置及びその製造方法
JP3554533B2 (ja) * 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
CA2426330A1 (en) 2000-11-01 2002-05-10 3M Innovative Properties Company Electrical sensing and/or signal application device
JP2002151532A (ja) 2000-11-08 2002-05-24 Sharp Corp 電子部品、半導体装置の実装方法および半導体装置の実装構造
JP2002151551A (ja) 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US6552436B2 (en) 2000-12-08 2003-04-22 Motorola, Inc. Semiconductor device having a ball grid array and method therefor
US20020079595A1 (en) 2000-12-21 2002-06-27 Carpenter Burton J. Apparatus for connecting a semiconductor die to a substrate and method therefor
DE10163799B4 (de) 2000-12-28 2006-11-23 Matsushita Electric Works, Ltd., Kadoma Halbleiterchip-Aufbausubstrat und Verfahren zum Herstellen eines solchen Aufbausubstrates
US6518678B2 (en) 2000-12-29 2003-02-11 Micron Technology, Inc. Apparatus and method for reducing interposer compression during molding process
US6800169B2 (en) 2001-01-08 2004-10-05 Fujitsu Limited Method for joining conductive structures and an electrical conductive article
US6458623B1 (en) 2001-01-17 2002-10-01 International Business Machines Corporation Conductive adhesive interconnection with insulating polymer carrier
US6577014B2 (en) 2001-01-19 2003-06-10 Yu-Nung Shen Low-profile semiconductor device
US6780682B2 (en) 2001-02-27 2004-08-24 Chippac, Inc. Process for precise encapsulation of flip chip interconnects
US6737295B2 (en) 2001-02-27 2004-05-18 Chippac, Inc. Chip scale package with flip chip interconnect
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US7242099B2 (en) * 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
ATE458249T1 (de) 2001-03-15 2010-03-15 Halo Inc Doppelbit monos speicherzellgebrauch für breite programbandbreite
US7331502B2 (en) * 2001-03-19 2008-02-19 Sumitomo Bakelite Company, Ltd. Method of manufacturing electronic part and electronic part obtained by the method
US6495397B2 (en) 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection
TW498506B (en) 2001-04-20 2002-08-11 Advanced Semiconductor Eng Flip-chip joint structure and the processing thereof
US6664483B2 (en) 2001-05-15 2003-12-16 Intel Corporation Electronic package with high density interconnect and associated methods
US6510976B2 (en) 2001-05-18 2003-01-28 Advanpack Solutions Pte. Ltd. Method for forming a flip chip semiconductor package
JP4445163B2 (ja) 2001-07-13 2010-04-07 パナソニック株式会社 電子部品の実装装置
US7296727B2 (en) 2001-06-27 2007-11-20 Matsushita Electric Industrial Co., Ltd. Apparatus and method for mounting electronic components
US7294457B2 (en) 2001-08-07 2007-11-13 Boehringer Ingelheim (Canada) Ltd. Direct binding assay for identifying inhibitors of HCV polymerase
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US6660560B2 (en) * 2001-09-10 2003-12-09 Delphi Technologies, Inc. No-flow underfill material and underfill method for flip chip devices
US6853076B2 (en) 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
TW507341B (en) * 2001-11-01 2002-10-21 Siliconware Precision Industries Co Ltd Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate
US7202556B2 (en) 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
JP3891838B2 (ja) 2001-12-26 2007-03-14 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6870276B1 (en) * 2001-12-26 2005-03-22 Micron Technology, Inc. Apparatus for supporting microelectronic substrates
WO2003071842A1 (en) * 2001-12-26 2003-08-28 Motorola, Inc. Method of mounting a semiconductor die on a substrate without using a solder mask
US6644536B2 (en) 2001-12-28 2003-11-11 Intel Corporation Solder reflow with microwave energy
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6974659B2 (en) 2002-01-16 2005-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a solder ball using a thermally stable resinous protective layer
JP3687610B2 (ja) 2002-01-18 2005-08-24 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
TWI268581B (en) 2002-01-25 2006-12-11 Advanced Semiconductor Eng Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material
JP2003264256A (ja) 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
JP2003273145A (ja) * 2002-03-12 2003-09-26 Sharp Corp 半導体装置
US6767411B2 (en) 2002-03-15 2004-07-27 Delphi Technologies, Inc. Lead-free solder alloy and solder reflow process
TW557536B (en) 2002-05-27 2003-10-11 Via Tech Inc High density integrated circuit packages and method for the same
TW550800B (en) 2002-05-27 2003-09-01 Via Tech Inc Integrated circuit package without solder mask and method for the same
US6780673B2 (en) * 2002-06-12 2004-08-24 Texas Instruments Incorporated Method of forming a semiconductor device package using a plate layer surrounding contact pads
US6659512B1 (en) 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
JP2004063524A (ja) 2002-07-25 2004-02-26 Toshiba Corp 実装装置及びその実装方法若しくはプリント配線基板
US6696644B1 (en) * 2002-08-08 2004-02-24 Texas Instruments Incorporated Polymer-embedded solder bumps for reliable plastic package attachment
US6974330B2 (en) 2002-08-08 2005-12-13 Micron Technology, Inc. Electronic devices incorporating electrical interconnections with improved reliability and methods of fabricating same
US7182241B2 (en) 2002-08-09 2007-02-27 Micron Technology, Inc. Multi-functional solder and articles made therewith, such as microelectronic components
US6811892B2 (en) * 2002-08-22 2004-11-02 Delphi Technologies, Inc. Lead-based solder alloys containing copper
JP2004095923A (ja) * 2002-09-02 2004-03-25 Murata Mfg Co Ltd 実装基板およびこの実装基板を用いた電子デバイス
TW561602B (en) 2002-09-09 2003-11-11 Via Tech Inc High density integrated circuit packages and method for the same
JP2004111676A (ja) * 2002-09-19 2004-04-08 Toshiba Corp 半導体装置、半導体パッケージ用部材、半導体装置の製造方法
JP2004134648A (ja) 2002-10-11 2004-04-30 Seiko Epson Corp 回路基板、ボール・グリッド・アレイの実装構造、及び電気光学装置、並びに電子機器
TW543923U (en) 2002-10-25 2003-07-21 Via Tech Inc Structure of chip package
JP2004165283A (ja) * 2002-11-11 2004-06-10 Fujitsu Ltd 半導体装置
US7173342B2 (en) * 2002-12-17 2007-02-06 Intel Corporation Method and apparatus for reducing electrical interconnection fatigue
TW586199B (en) 2002-12-30 2004-05-01 Advanced Semiconductor Eng Flip-chip package
JP4114483B2 (ja) 2003-01-10 2008-07-09 セイコーエプソン株式会社 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器
US6821878B2 (en) * 2003-02-27 2004-11-23 Freescale Semiconductor, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US6943058B2 (en) 2003-03-18 2005-09-13 Delphi Technologies, Inc. No-flow underfill process and material therefor
US6774497B1 (en) 2003-03-28 2004-08-10 Freescale Semiconductor, Inc. Flip-chip assembly with thin underfill and thick solder mask
US20040232560A1 (en) 2003-05-22 2004-11-25 Chao-Yuan Su Flip chip assembly process and substrate used therewith
US20040232562A1 (en) * 2003-05-23 2004-11-25 Texas Instruments Incorporated System and method for increasing bump pad height
US6888255B2 (en) * 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
US6849944B2 (en) * 2003-05-30 2005-02-01 Texas Instruments Incorporated Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad
TW572361U (en) * 2003-06-03 2004-01-11 Via Tech Inc Flip-chip package carrier
JP2005028037A (ja) 2003-07-11 2005-02-03 Fuji Photo Film Co Ltd 医用画像処理装置及び医用画像処理方法
TWI227556B (en) * 2003-07-15 2005-02-01 Advanced Semiconductor Eng Chip structure
TWI241702B (en) * 2003-07-28 2005-10-11 Siliconware Precision Industries Co Ltd Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
KR100523330B1 (ko) * 2003-07-29 2005-10-24 삼성전자주식회사 Ｓｍｄ 및 ｎｓｍｄ 복합형 솔더볼 랜드 구조를 가지는ｂｇａ 반도체 패키지
TWI234258B (en) * 2003-08-01 2005-06-11 Advanced Semiconductor Eng Substrate with reinforced structure of contact pad
TWI241675B (en) 2003-08-18 2005-10-11 Siliconware Precision Industries Co Ltd Chip carrier for semiconductor chip
KR100541394B1 (ko) * 2003-08-23 2006-01-10 삼성전자주식회사 비한정형 볼 그리드 어레이 패키지용 배선기판 및 그의제조 방법
TWI221336B (en) 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US7271484B2 (en) * 2003-09-25 2007-09-18 Infineon Technologies Ag Substrate for producing a soldering connection
US20050095835A1 (en) 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7112524B2 (en) 2003-09-29 2006-09-26 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
JP3877717B2 (ja) * 2003-09-30 2007-02-07 三洋電機株式会社 半導体装置およびその製造方法
JP2005109187A (ja) * 2003-09-30 2005-04-21 Tdk Corp フリップチップ実装回路基板およびその製造方法ならびに集積回路装置
TWI245389B (en) 2003-10-02 2005-12-11 Siliconware Precision Industries Co Ltd Conductive trace structure and semiconductor package having the conductive trace structure
JP2005116685A (ja) 2003-10-06 2005-04-28 Seiko Epson Corp プリント配線基板、電子部品モジュール及び電子機器
US7462942B2 (en) 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US7736950B2 (en) 2003-11-10 2010-06-15 Stats Chippac, Ltd. Flip chip interconnection
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
KR101249555B1 (ko) * 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US7294451B2 (en) 2003-11-18 2007-11-13 Texas Instruments Incorporated Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
JP3863161B2 (ja) 2004-01-20 2006-12-27 松下電器産業株式会社 半導体装置
JP3981089B2 (ja) 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
WO2005093817A1 (ja) 2004-03-29 2005-10-06 Nec Corporation 半導体装置及びその製造方法
JP4024773B2 (ja) 2004-03-30 2007-12-19 シャープ株式会社 配線基板、半導体装置およびその製造方法並びに半導体モジュール装置
TWI240389B (en) 2004-05-06 2005-09-21 Advanced Semiconductor Eng High-density layout substrate for flip-chip package
US7224073B2 (en) * 2004-05-18 2007-05-29 Ultratera Corporation Substrate for solder joint
US7183493B2 (en) 2004-06-30 2007-02-27 Intel Corporation Electronic assembly having multi-material interconnects
US7057284B2 (en) * 2004-08-12 2006-06-06 Texas Instruments Incorporated Fine pitch low-cost flip chip substrate
JP2006108313A (ja) 2004-10-04 2006-04-20 Rohm Co Ltd 実装基板および半導体装置
DE102004050178B3 (de) 2004-10-14 2006-05-04 Infineon Technologies Ag Flip-Chip-Bauelement
US7488896B2 (en) 2004-11-04 2009-02-10 Ngk Spark Plug Co., Ltd. Wiring board with semiconductor component
US8067823B2 (en) 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
US20060131758A1 (en) 2004-12-22 2006-06-22 Stmicroelectronics, Inc. Anchored non-solder mask defined ball pad
TWI261329B (en) 2005-03-09 2006-09-01 Phoenix Prec Technology Corp Conductive bump structure of circuit board and method for fabricating the same
US7361990B2 (en) 2005-03-17 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US7148086B2 (en) 2005-04-28 2006-12-12 Stats Chippac Ltd. Semiconductor package with controlled solder bump wetting and fabrication method therefor
US20060255473A1 (en) 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP4190525B2 (ja) 2005-08-22 2008-12-03 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4971769B2 (ja) 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
TWI286830B (en) 2006-01-16 2007-09-11 Siliconware Precision Industries Co Ltd Electronic carrier board
TWI294682B (en) 2006-02-03 2008-03-11 Siliconware Precision Industries Co Ltd Semiconductor package substrate
US20070200234A1 (en) 2006-02-28 2007-08-30 Texas Instruments Incorporated Flip-Chip Device Having Underfill in Controlled Gap
US7317245B1 (en) 2006-04-07 2008-01-08 Amkor Technology, Inc. Method for manufacturing a semiconductor device substrate
US7541681B2 (en) 2006-05-04 2009-06-02 Infineon Technologies Ag Interconnection structure, electronic component and method of manufacturing the same
JP2007305881A (ja) 2006-05-12 2007-11-22 Sharp Corp テープキャリアおよび半導体装置並びに半導体モジュール装置
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
KR100764055B1 (ko) 2006-09-07 2007-10-08 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법
TWI378540B (en) 2006-10-14 2012-12-01 Advanpack Solutions Pte Ltd Chip and manufacturing method thereof
US20080093749A1 (en) 2006-10-20 2008-04-24 Texas Instruments Incorporated Partial Solder Mask Defined Pad Design
TWI331388B (en) 2007-01-25 2010-10-01 Advanced Semiconductor Eng Package substrate, method of fabricating the same and chip package
JP4618260B2 (ja) 2007-02-21 2011-01-26 日本テキサス・インスツルメンツ株式会社 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置
US7521284B2 (en) 2007-03-05 2009-04-21 Texas Instruments Incorporated System and method for increased stand-off height in stud bumping process
TWI361482B (en) 2007-05-10 2012-04-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package structure and package substrate applicable thereto
US8178392B2 (en) 2007-05-18 2012-05-15 Stats Chippac Ltd. Electronic system with expansion feature
US20090057378A1 (en) 2007-08-27 2009-03-05 Chi-Won Hwang In-situ chip attachment using self-organizing solder
EP2206145A4 (en) 2007-09-28 2012-03-28 Tessera Inc FLIP-CHIP CONNECTION WITH DOUBLE POSTS
TWI357137B (en) 2007-10-19 2012-01-21 Advanced Semiconductor Eng Flip chip package structure and carrier thereof
TWI358113B (en) 2007-10-31 2012-02-11 Advanced Semiconductor Eng Substrate structure and semiconductor package usin
TW200921868A (en) 2007-11-07 2009-05-16 Advanced Semiconductor Eng Substrate structure
US7847399B2 (en) 2007-12-07 2010-12-07 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
JP5107012B2 (ja) 2007-12-12 2012-12-26 新光電気工業株式会社 配線基板及び電子部品の実装構造の製造方法
TWI340615B (en) 2008-01-30 2011-04-11 Advanced Semiconductor Eng Surface treatment process for circuit board
JP5106197B2 (ja) 2008-03-25 2012-12-26 京セラＳｌｃテクノロジー株式会社 半導体装置およびその製造方法
US7670939B2 (en) 2008-05-12 2010-03-02 Ati Technologies Ulc Semiconductor chip bump connection apparatus and method
US7851928B2 (en) 2008-06-10 2010-12-14 Texas Instruments Incorporated Semiconductor device having substrate with differentially plated copper and selective solder
TWI425896B (zh) 2008-06-11 2014-02-01 Advanced Semiconductor Eng 具有內埋式導電線路之電路板及其製造方法
KR100979497B1 (ko) 2008-06-17 2010-09-01 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
US7790509B2 (en) 2008-06-27 2010-09-07 Texas Instruments Incorporated Method for fine-pitch, low stress flip-chip interconnect
JP2010118534A (ja) 2008-11-13 2010-05-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
TWI384600B (zh) 2008-12-09 2013-02-01 Advanced Semiconductor Eng 內埋線路基板及其製造方法
JP2010141055A (ja) 2008-12-10 2010-06-24 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US20110049703A1 (en) 2009-08-25 2011-03-03 Jun-Chung Hsu Flip-Chip Package Structure
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5519580A (en) * 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
JPH11145176A (ja) * 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
US6409073B1 (en) * 1998-07-15 2002-06-25 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method for transfering solder to a device and/or testing the device
US6383916B1 (en) * 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
US6458622B1 (en) * 1999-07-06 2002-10-01 Motorola, Inc. Stress compensation composition and semiconductor component formed using the stress compensation composition
JP2001156203A (ja) * 1999-11-24 2001-06-08 Matsushita Electric Works Ltd 半導体チップ実装用プリント配線板
JP2002270732A (ja) * 2001-03-13 2002-09-20 Sharp Corp アンダーフィル材付き電子部品
TW530398B (en) * 2002-03-19 2003-05-01 Chipmos Technologies Inc Method for manufacturing bumps of chip scale package (CSP)

Also Published As

Publication number Publication date
USRE44431E1 (en) 2013-08-13
US8188598B2 (en) 2012-05-29
WO2005048311A2 (en) 2005-05-26
KR101286379B1 (ko) 2013-07-15
TW201237976A (en) 2012-09-16
US7368817B2 (en) 2008-05-06
US20120211887A1 (en) 2012-08-23
TWI534915B (zh) 2016-05-21
USRE44524E1 (en) 2013-10-08
KR20120041775A (ko) 2012-05-02
US7973406B2 (en) 2011-07-05
USRE44355E1 (en) 2013-07-09
KR20070009973A (ko) 2007-01-19
TW201304026A (zh) 2013-01-16
US9922915B2 (en) 2018-03-20
USRE44377E1 (en) 2013-07-16
US20130328189A1 (en) 2013-12-12
US20110215468A1 (en) 2011-09-08
TW200525666A (en) 2005-08-01
US20100164100A1 (en) 2010-07-01
TWI378516B (en) 2012-12-01
KR101249555B1 (ko) 2013-04-01
US7700407B2 (en) 2010-04-20
JP2007511103A (ja) 2007-04-26
KR20130006532A (ko) 2013-01-16
US8558378B2 (en) 2013-10-15
US20080213941A1 (en) 2008-09-04
WO2005048311A3 (en) 2006-01-05
US20050110164A1 (en) 2005-05-26
KR101237172B1 (ko) 2013-02-25
JP4928945B2 (ja) 2012-05-09

Similar Documents

Publication Publication Date Title
TWI478254B (zh) 引線上凸塊之倒裝晶片互連
US9545013B2 (en) Flip chip interconnect solder mask
TWI404114B (zh) 具有在基板上之窄互連部位之倒裝晶片互連
US7901983B2 (en) Bump-on-lead flip chip interconnection
JP4051570B2 (ja) 半導体装置の製造方法