WO2012056661A1 - 電子部品の接合形態 - Google Patents

電子部品の接合形態 Download PDF

Info

Publication number
WO2012056661A1
WO2012056661A1 PCT/JP2011/005895 JP2011005895W WO2012056661A1 WO 2012056661 A1 WO2012056661 A1 WO 2012056661A1 JP 2011005895 W JP2011005895 W JP 2011005895W WO 2012056661 A1 WO2012056661 A1 WO 2012056661A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
wiring
electronic
convex body
wirings
Prior art date
Application number
PCT/JP2011/005895
Other languages
English (en)
French (fr)
Inventor
博光 高下
剛 武田
優子 今野
弘明 藤原
愼悟 吉岡
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to CN201180051390XA priority Critical patent/CN103180944A/zh
Publication of WO2012056661A1 publication Critical patent/WO2012056661A1/ja
Priority to US13/869,553 priority patent/US9204530B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16113—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/32147—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the layer connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/32148—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the layer connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09245—Crossing layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09263—Meander
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Definitions

  • the present invention relates to a joining form (assembly) of electronic parts, and more particularly to improvement of electrical connection between electronic parts.
  • connection pads of the semiconductor chip and the connection pads of the substrate are joined via bumps, for example, and the two are electrically connected.
  • the land of the package and the land of the circuit board are joined through, for example, bumps, and the two are electrically connected.
  • impedance mismatch occurs due to reflection loss or the like in the connection portion, resulting in a decrease in impedance. It can happen. This problem is particularly noticeable in the high-speed signal transmission region such as the GHz band.
  • Patent Document 1 discloses that a substrate and a semiconductor chip are electrically connected by facing and joining a joint wiring formed on the substrate and a chip joint of a semiconductor chip.
  • the joint wiring and the chip joint described in Patent Document 1 are different in size.
  • Patent Document 2 discloses that a surface mounting component is mounted on a circuit board by connecting wiring on the upper surface of the circuit board and wiring on the upper surface of the surface mounting component via a slope of the surface mounting component. . Both the circuit board wiring and the surface mounting component wiring described in Patent Document 2 face upward, and the ends of each wiring are butted together and connected.
  • JP 2000-183231 (paragraph 0053, FIG. 1) Japanese Patent Laying-Open No. 2010-21505 (paragraphs 0021 to 0022, FIG. 4)
  • This invention makes it a subject to reduce the mismatch of the impedance in a connection part by the structure which is not in the past, when electrically connecting electronic components.
  • an electronic component refers to a component that can be electrically connected to another electronic component, and includes, for example, a semiconductor chip, a substrate, a package, a circuit substrate, and the like.
  • the electronic components include, for example, a semiconductor chip and a semiconductor chip, a semiconductor chip and a substrate, a package and a package, a package and a circuit board, a circuit board and a circuit board, and the like. Moreover, what combined these variously is also included.
  • One aspect of the present invention is an assembly of electronic components in which electronic components are electrically connected to each other, the wiring formed on the surface of the first electronic component and the wiring formed on the surface of the second electronic component.
  • the electronic component assembly is characterized in that the first electronic component and the second electronic component are electrically connected by facing each other and being joined with a conductor interposed therebetween. .
  • the conductor is preferably a resin composition containing solder or a conductive filler.
  • a convex body is formed on the surface of the first electronic component and / or the surface of the second electronic component, and a wiring is formed at the tip of the convex body, and the tip of the convex body.
  • the wiring of the first electronic component and the wiring of the second electronic component are preferably joined.
  • the convex body is a support in which the surface of the first electronic component or the surface of the second electronic component is formed into a convex shape, or the first electronic component or the second electronic component. Formed by covering the body with an insulator, formed by covering the convex shape of the surface of the first electronic component or the surface of the second electronic component with an insulator, and / or The convex shape of the surface of the first electronic component or the surface of the second electronic component is preferably formed of an insulator.
  • the wiring of the first electronic component and / or the wiring of the second electronic component is preferably partially or entirely embedded in the surface of the electronic component.
  • Another aspect of the present invention is an electronic component connection method for electrically connecting electronic components to each other, the wiring formed on the surface of the first electronic component and the surface of the second electronic component.
  • the first electronic component and the second electronic component are electrically connected to each other by facing each other and being joined with a conductor interposed therebetween. Is the method.
  • the wirings are joined without using a pad or a land, so that impedance mismatch at the connection portion can be reduced.
  • FIG. 1 is a side view for explaining the joining form of the electronic component according to the first embodiment.
  • FIG. 2A is a plan view showing the surface of the first electronic component according to the first embodiment
  • FIG. 2B is the surface of the second electronic component according to the first embodiment. It is a top view for showing.
  • FIG. 3 is a side view for explaining a joining form of the electronic component according to the second embodiment.
  • FIG. 4 is an explanatory diagram of a method for obtaining a joining form of electronic components according to the second embodiment.
  • FIG. 5 is a side view for explaining the joining form of the electronic component according to the third embodiment.
  • FIG. 6 is a plan view illustrating the surface of the second electronic component according to the third embodiment.
  • FIG. 7 is an explanatory diagram of a method of obtaining a joining form of electronic components according to the third embodiment.
  • FIG. 8 is an explanatory diagram of a method for obtaining the second electronic component according to the third embodiment.
  • FIG. 9 is a side view for explaining the joining form of the electronic component according to the fourth embodiment.
  • FIG. 10 is an explanatory diagram of a method for obtaining a bonded form of electronic components according to the fourth embodiment.
  • FIG. 11 is an explanatory diagram of a method for obtaining the second electronic component according to the fourth embodiment.
  • FIG. 12 is an explanatory diagram of a modification in which wiring is formed at the tip of the convex body.
  • FIG. 13 is an explanatory diagram of a fail-safe function for wiring misalignment.
  • FIG. 14 is an explanatory diagram of another fail-safe function of wiring misalignment.
  • FIG. 15 is a perspective view for explaining a joining form of the electronic component according to the fifth embodiment.
  • FIG. 16 is an explanatory diagram when the wiring is not embedded in the surface of the electronic component.
  • FIG. 17 is an explanatory diagram when a part of the wiring is embedded in the surface of the electronic component.
  • the first electronic component and the second electronic component are, for example, a semiconductor chip and a semiconductor chip, a semiconductor chip and a substrate, a package and a package, a package and a circuit board, a circuit board and a circuit board, and the like. is there. Moreover, what combined these variously is also contained in this embodiment.
  • an assembly of electronic components means an assembly of electronic components in which two or more electronic components are electrically connected, as referred to in the drawings and the like described later.
  • reference numeral 1 is the first electronic component
  • reference numeral 2 is the second electronic component
  • reference numeral 1a is the surface of the first electronic component
  • reference numeral 2a is the surface of the second electronic component
  • reference numeral 11 is the first electronic component.
  • Wiring of components reference numeral 12 is wiring of the second electronic component
  • reference numeral 13 is solder as a conductor.
  • the wiring 11 is formed on the surface 1a of the first electronic component 1
  • the wiring 12 is formed on the surface 2a of the second electronic component 2
  • the first electronic component 1 The wiring 11 and the wiring 12 of the second electronic component face each other and are joined with the solder 13 as a conductor interposed therebetween, so that the first electronic component 1 and the second electronic component 2 are electrically connected. Connected.
  • the wirings 11 and 12 are routed from the inside of the first and second electronic components 1 and 2 and exposed on the surfaces 1a and 1b.
  • a plurality of wirings 11 are formed on the surface 1 a of the first electronic component 1.
  • a plurality of wirings 12 are formed on the surface 2a of the second electronic component 2 at positions corresponding to the wirings 11 of the first electronic component.
  • the corresponding wirings 11 and 12 are overlapped and joined to each other.
  • the width of the wirings 11 and 12 is, for example, 20 ⁇ m.
  • the solder 13 is used as the conductor.
  • the solder 13 achieves electrical connection and mechanical coupling between the first electronic component 1 and the second electronic component 2.
  • the solder 13 is substantially contained within the width of the wirings 11 and 12.
  • the wiring 11 of the first electronic component and the wiring 12 of the second electronic component may extend in the same direction and be joined at a relatively long distance, or may extend in a different direction from each other. For example, they may be joined at a short distance.
  • reference numeral 14 is ACP (anisotropic conductive paste) or ACF (anisotropic conductive film) as a conductor
  • reference numeral 14a is a conductive filler
  • reference numeral 14b is a resin composition. is there.
  • ACP or ACF 14 is used as a conductor.
  • ACP and ACF 14 are a resin composition 14b containing a conductive filler 14a.
  • the ACP or ACF 14 achieves electrical connection and mechanical coupling between the first electronic component 1 and the second electronic component 2.
  • the ACP or ACF 14 fills the gap between the first and second electronic components 1 and 2.
  • the ACP or ACF 14 has anisotropy with respect to conduction. That is, only the wirings in the connection direction (overlapping direction) conduct, and there is a property that insulation is maintained between adjacent wirings.
  • the conductive filler 14 a that functions as a conductor is sandwiched between the overlapping wirings 11 and 12 and is substantially contained within the width of the wirings 11 and 12.
  • ACP or ACF 14 is applied or formed on the surface 1 a of the first electronic component 1.
  • the wiring 11 of the first electronic component is covered with ACP or ACF 14.
  • the surface 1a of the first electronic component 1 and the surface 2a of the second electronic component 2 are faced, and the wiring 11 of the first electronic component and the wiring 12 of the second electronic component are faced.
  • the first electronic component 1 and the second electronic component 2 are thermocompression bonded.
  • the ACP or ACF 14 fills the gap between the first and second electronic components 1 and 2, but only the wirings 11 and 12 in the connection direction (overlapping direction) are electrically connected to each other, and the superimposed wirings 11 and 12 are connected. Only one another is joined.
  • reference numeral 15 denotes a convex body
  • reference numeral 18 denotes an insulating substrate
  • reference numeral 19 denotes a resin film
  • reference numeral 20 denotes a wiring pattern groove.
  • the convex body 15 is formed on the surface 2 a of the second electronic component 2, and the wiring 12 is formed at the tip of the convex body 15.
  • the wiring 11 of the first electronic component and the wiring 12 of the second electronic component are joined to each other at the front end portion.
  • the convex body 15 is obtained by forming the surface 2a of the second electronic component 2 into a convex shape.
  • the convex body 15 has a truncated cone shape.
  • the shape is not limited to this, and other shapes such as a truncated pyramid shape, a cylindrical shape, a prism shape, a hemispherical shape, and the like may be used.
  • a plurality of wirings 12 are formed on the surface 2 a of the second electronic component 2.
  • the wiring 12 passes through the tip of the convex body 15.
  • a plurality of wires 11 are formed on the surface 1a of the first electronic component 1 at positions corresponding to the wires 12 of the second electronic component.
  • the corresponding wirings 11 and 12 are overlapped and joined to each other.
  • the joining form of the electronic component shown in FIG. 5 can be obtained as follows. As shown in FIG. 7, ACP or ACF 14 is applied or formed on the surface 1 a of the first electronic component 1. The wiring 11 of the first electronic component is covered with ACP or ACF 14. The surface 1a of the first electronic component 1 and the surface 2a of the second electronic component 2 are faced, and the wiring 11 of the first electronic component and the wiring 12 of the second electronic component are faced. In this state, the first electronic component 1 and the second electronic component 2 are thermocompression bonded. In that case, the tip of the convex body 15 of the second electronic component 2 presses the surface 1 a of the first electronic component 1. The ACP or ACF 14 fills the gap between the first and second electronic components 1 and 2, but only the wirings 11 and 12 in the connection direction (overlapping direction) are electrically connected to each other, and the superimposed wirings 11 and 12 are connected. Only one another is joined.
  • the second electronic component 2 can be obtained as follows. First, as shown in FIG. 8A, an insulating substrate 18 whose surface is formed in a convex shape is prepared. Those whose surface is formed into a convex shape constitutes a convex body 15.
  • a resin film 19 is formed on the surface of the insulating substrate 18.
  • the surface of the resin film 19 follows the insulating base material 18 and exhibits an uneven shape.
  • a wiring pattern groove having a depth equal to or exceeding the thickness of the resin film 19 from the surface side of the resin film 19 (the example in the figure is the same depth as the thickness of the resin film 19).
  • Wiring pattern groove) 20 is formed.
  • the wiring pattern groove 20 includes a communication hole that communicates with the inside of the second electronic component 2.
  • Such a wiring pattern groove 20 can be formed with high accuracy, for example, by laser processing from the surface side of the resin film 19.
  • a plating catalyst or a precursor thereof is deposited on the surface of the wiring pattern groove 20.
  • the resin film 19 is removed by dissolving or swelling.
  • a plating film is formed only on the portion where the plating catalyst formed from the plating catalyst or its precursor remains.
  • the plating film constitutes the wiring 12.
  • wirings 12 are formed on the surface 2a of the second electronic component 2 along the wiring pattern grooves 20.
  • the convex body 15 is formed on the surface 2a of the second electronic component 2, and the wiring 12 is formed at the tip of the convex body 15.
  • the first The convex body 15 may be formed on the surface 1 a of one electronic component 1, and the wiring 11 may be formed at the tip of the convex body 15.
  • reference numeral 15 denotes a convex body
  • reference numeral 16 denotes a support
  • reference numeral 16a denotes a convex shape
  • reference numeral 17 denotes an insulator (insulating resin)
  • reference numeral 18 denotes an insulating substrate
  • reference numeral 18a denotes an internal circuit
  • reference numeral 19 denotes a resin.
  • symbol 20 are wiring pattern grooves.
  • the convex body 15 is formed on the surface 2 a of the second electronic component 2, and the wiring 12 is formed at the tip of the convex body 15.
  • the wiring 11 of the first electronic component and the wiring 12 of the second electronic component are joined to each other at the front end portion.
  • the convex body 15 is formed by covering the support 16 built in the second electronic component 2 with the insulator 17, and the convex shape of the surface of the second electronic component 2.
  • 16a is formed by covering with an insulator 17, and the convex shape of the surface of the second electronic component 2 is 16b formed of an insulator 17 (two or more types of convex bodies 15). Is a mixed pattern).
  • the present invention is not limited to this, and the convex body 15 is only the surface of the second electronic component 2 formed by covering the support 16 built in the second electronic component 2 with the insulator 17. Only those formed by covering the convex shape 16 a with the insulator 17, or only the convex shape 16 b formed with the insulator 17 on the surface of the second electronic component 2 may be used.
  • the convex body 15 has a truncated cone shape.
  • the shape is not limited to this, and other shapes such as a truncated pyramid shape, a cylindrical shape, a prism shape, a hemispherical shape, and the like may be used.
  • ACP or ACF 14 is applied or formed on the surface 1 a of the first electronic component 1.
  • the wiring 11 of the first electronic component is covered with ACP or ACF 14.
  • the surface 1a of the first electronic component 1 and the surface 2a of the second electronic component 2 are faced, and the wiring 11 of the first electronic component and the wiring 12 of the second electronic component are faced.
  • the first electronic component 1 and the second electronic component 2 are thermocompression bonded.
  • the tip of the convex body 15 of the second electronic component 2 presses the surface 1 a of the first electronic component 1.
  • the ACP or ACF 14 fills the gap between the first and second electronic components 1 and 2, but only the wirings 11 and 12 in the connection direction (overlapping direction) are electrically connected to each other, and the superimposed wirings 11 and 12 are connected. Only one another is joined.
  • the second electronic component 2 can be obtained as follows. First, as shown in FIG. 11 (A), the insulating base material 18 having the tip portions of the plurality of supports 16 protruding from the surface, the plurality of convex shapes 16a formed on the surface, and the internal circuit 18a formed on the surface. prepare.
  • an insulator 17 is formed on the surface of the insulating base 18.
  • the surface of the insulator 17 has an uneven shape following the tip of the support 16 and the convex shape 16a.
  • the convex shape 16b formed of the insulator 17 is formed.
  • a resin film 19 is formed on the surface of the insulator 17.
  • the surface of the resin film 19 follows the insulator 17 and exhibits an uneven shape.
  • a wiring pattern groove having a depth equal to or exceeding the thickness of the resin film 19 from the surface side of the resin film 19 (the illustrated example has the same depth as the thickness of the resin film 19).
  • Wiring pattern groove) 20 is formed.
  • the wiring pattern groove 20 includes a communication hole that communicates with the inside of the second electronic component 2.
  • the communication hole reaches the internal circuit 18 a on the surface of the insulating base 18.
  • Such a wiring pattern groove 20 can be formed with high accuracy, for example, by laser processing from the surface side of the resin film 19.
  • a plating catalyst or a precursor thereof is deposited on the surface of the wiring pattern groove 20.
  • the resin film 19 is removed by dissolving or swelling.
  • a plating film is formed only on the portion where the plating catalyst formed from the plating catalyst or its precursor remains.
  • the plating film constitutes the wiring 12.
  • wirings 12 are formed on the surface 2a of the second electronic component 2 in the manner of wiring pattern grooves 20.
  • the wiring 12 is connected to the internal circuit 18a.
  • the convex body 15 is formed on the surface 2a of the second electronic component 2, and the wiring 12 is formed at the tip of the convex body 15.
  • the first The convex body 15 may be formed on the surface 1 a of one electronic component 1, and the wiring 11 may be formed at the tip of the convex body 15.
  • FIG. 12 is an explanatory diagram of a modification in which the wiring 12 is formed at the tip of the convex body 15.
  • the wiring 12 of the second electronic component passing through the tip of the convex body 15 is indicated by a solid line
  • the wiring 11 of the first electronic component joined to the wiring 12 is indicated by a broken line.
  • the number of wirings 12 of the second electronic component passing through the tip of the convex body 15 is not limited to one, and may be two or three or more.
  • the wiring 11 of the first electronic component is not limited to one, but may be two or three or more.
  • FIG. 13 and FIG. 14 are explanatory diagrams of the fail-safe function of wiring misalignment.
  • the wiring 12 of the second electronic component passing through the tip of the convex body 15 is indicated by a solid line
  • the wiring 11 of the first electronic component joined to the wiring 12 is indicated by a broken line.
  • the wiring 11 of the first electronic component and the wiring 12 of the second electronic component may extend in the same direction and be joined at a relatively long distance, or may be in different directions. It may extend and be joined at a relatively short distance. In the former case, if a positional shift occurs between the wirings 11 and 12, the wirings 11 and 12 may not be overlapped, resulting in poor bonding. Therefore, it is preferable to ensure the overlap between the wirings 11 and 12 by meandering the wirings 11 and 12 as shown in FIG. 13 or bending one wiring as shown in FIG.
  • a convex body 15 is formed on the surface 2 a of the second electronic component 2, the wiring 12 is formed at the tip of the convex body 15, and the first A convex body 15 is also formed on the surface 1a of the electronic component 1, and a wiring 11 is formed at the tip of the convex body 15, so that the convex body 15 of the second electronic component 2 and the first The wiring 11 of the first electronic component and the wiring 12 of the second electronic component are joined at the tip of the electronic component 1 with the convex body 15.
  • the convex bodies 15, 15 are all formed by the insulators 17, 17 that form the surface 1a of the first electronic component 1 or the surface 2a of the second electronic component 2.
  • the convex body 15 has a convex shape having a predetermined length.
  • a plurality of wirings 11... 11 are formed at the tip of the convex body 15 of the first electronic component 1.
  • a plurality of wirings 12... 12 are also formed at positions corresponding to the tip of the convex body 15 of the second electronic component 2.
  • the corresponding wirings 11... 11, 12... 12 are overlapped and joined to each other.
  • the wirings 11 and 12 may not be embedded in the surfaces 1a and 2a of the electronic components 1 and 2 as illustrated in FIG. Part or all of the surfaces 1a and 2a may be embedded (partially embedded in the illustrated example).
  • the wirings 11 and 12 that are not embedded in the surfaces 1a and 2a of the electronic components 1 and 2 are, for example, wiring pattern grooves having the same depth as the thickness of the resin film 19 from the surface side of the resin film 19 in FIG. 20 can be obtained.
  • the wirings 11 and 12 embedded in the surfaces 1a and 2a of the electronic components 1 and 2 have a depth exceeding the thickness of the resin film 19 from the surface side of the resin film 19 in FIG. It can be obtained by forming the wiring pattern groove 20.
  • the grooves 1b and 2b are formed on the surfaces of the insulators 17 and 17 that form the surfaces 1a and 2a of the electronic components 1 and 2, and the plating films that constitute the wirings 11 and 12 in the grooves 1b and 2b. Will enter.
  • the present invention is not limited to this, and the cross-sectional shape may be another shape, for example, a triangular shape or a quadrangular shape (see the chain line in the figure). .
  • the joining form (assembly) of the electronic components 1 and 2 according to the present embodiment is the same as the wiring 11 formed on the surface 1a of the first electronic component 1 and the second one.
  • the wiring 12 formed on the surface 2a of the electronic component 2 faces each other and is joined with the conductors 13 and 14 interposed therebetween, whereby the first electronic component 1 and the second electronic component 2 are electrically connected. Connected.
  • the wirings 11 and 12 having the same size and the same size can be connected to each other without using pads and lands having different sizes. Since the bonding is performed, impedance mismatch at the connection portion can be reduced.
  • solder 13 or the conductive filler 14a as a conductor is substantially contained within the width of the wirings 11 and 12, even if the conductors 13 and 14 are included, impedance mismatching at the connection portion is not achieved. Reduction is achieved.
  • the resin composition 14b (ACP or ACF14) containing the solder 13 or the conductive filler 14a as the conductor, the electrical connection and the mechanical connection between the first electronic component 1 and the second electronic component 2 are achieved. Both binding and are achieved.
  • the convex body 15 is formed on the surface 1a of the first electronic component 1 and / or the surface 2a of the second electronic component 2.
  • Wirings 11 and 12 are formed at the tip of the convex body 15, and the wiring 11 of the first electronic component and the wiring 12 of the second electronic component are joined at the tip of the convex body 15. It is.
  • the convex body 15 is obtained by forming the surface 1a of the first electronic component 1 or the surface 2a of the second electronic component 2 into a convex shape, the first electronic component 1 or the second electronic component. 2 is formed by covering the support 16 built in 2 with the insulator 17, and the convex shape 16 a on the surface of the first electronic component 1 or the surface of the second electronic component 2 is covered with the insulator 17. What is formed by this, and / or what the convex shape of the surface of the 1st electronic component 1 or the surface of the 2nd electronic component 2 was formed of the insulator 17 may be used.
  • the convex body 15 may be entirely formed by the insulator 17 that forms the surfaces 1 a and 2 a of the electronic components 1 and 2.
  • the convex body 15 may be a mixture of any one of these or any two or more of them.
  • the formation pattern of the convex body 15 can be selected from these.
  • the wirings 11 and 12 are embedded in the surfaces 1a and 2a of the electronic components 1 and 2, respectively. This is because misalignment and dropping of the wirings 11 and 12 are suppressed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

【課題】電子部品同士を電気的に接続する場合に、接続部でのインピーダンスの不整合を低減する。 【解決手段】電子部品１，２同士を電気的に接続する電子部品の接合形態において、第１の電子部品１の表面１ａに形成された配線１１と第２の電子部品２の表面２ａに形成された配線１２とが向き合され、導電体１３を間に挟んで接合されることにより、第１の電子部品１と第２の電子部品２とが電気的に接続されている。導電体１３は半田又は導電性フィラーを含有する樹脂組成物である。

Description

電子部品の接合形態
　本発明は、電子部品の接合形態（アセンブリ）、より詳しくは、電子部品同士の電気的接続の改良に関する。
　例えば、半導体チップを基板に搭載してパッケージを作製する場合、半導体チップの接続パッドと基板の接続パッドとを例えばバンプを介して接合し、両者を電気的に接続している。また、パッケージを回路基板に実装する場合、パッケージのランドと回路基板のランドとを例えばバンプを介して接合し、両者を電気的に接続している。いずれも、パッドやランドまで引き回した配線と、パッド、ランド、あるいはバンプとのサイズの違いに起因して、接続部において、反射損失等によるインピーダンスの不整合が生じ、インピーダンスが低下するという問題が起り得る。この問題は、例えばＧＨｚ帯等の高速信号伝送の領域で特に顕著となる。
　特許文献１には、基板上に形成した接合部配線と半導体チップのチップ接合部とを向き合せて接合することにより、基板と半導体チップとを電気的に接続することが開示されている。特許文献１に記載の接合部配線とチップ接合部とはサイズが相違している。
　特許文献２には、回路基板の上面の配線と表面実装部品の上面の配線とを表面実装部品の斜面を介して接続することにより、回路基板に表面実装部品を実装することが開示されている。特許文献２に記載の回路基板の配線と表面実装部品の配線とは共に上方を向いており、各配線の端部同士を突き合せて接続している。
特開２０００－１８３２３１号公報（段落００５３、図１） 特開２０１０－２１５０５号公報（段落００２１～００２２、図４）
　本発明は、電子部品同士を電気的に接続する場合に、従来にない構成により、接続部でのインピーダンスの不整合を低減することを課題とする。
　なお、本発明において、電子部品とは、他の電子部品と電気的に接続し得るものをいい、例えば、半導体チップ、基板、パッケージ、回路基板等を含む。そして、電子部品同士とは、例えば、半導体チップと半導体チップ、半導体チップと基板、パッケージとパッケージ、パッケージと回路基板、回路基板と回路基板等を含む。また、これらが種々組み合されたものも含む。
　本発明の一局面は、電子部品同士が電気的に接続された電子部品のアセンブリであって、第１の電子部品の表面に形成された配線と第２の電子部品の表面に形成された配線とが向き合され、導電体を間に挟んで接合されることにより、第１の電子部品と第２の電子部品とが電気的に接続されていることを特徴とする電子部品のアセンブリである。
　本発明においては、導電体は、半田又は導電性フィラーを含有する樹脂組成物であることが好ましい。
　本発明においては、第１の電子部品の表面及び／又は第２の電子部品の表面に凸形状体が形成され、この凸形状体の先端部に配線が形成され、この凸形状体の先端部において第１の電子部品の配線と第２の電子部品の配線とが接合されていることが好ましい。
　本発明においては、凸形状体は、第１の電子部品の表面又は第２の電子部品の表面が凸形状に成形されたもの、第１の電子部品又は第２の電子部品に内蔵された支持体が絶縁体で被覆されることによって形成されたもの、第１の電子部品の表面又は第２の電子部品の表面の凸形状が絶縁体で被覆されることによって形成されたもの、及び／又は、第１の電子部品の表面又は第２の電子部品の表面の凸形状が絶縁体で形成されたものであることが好ましい。
　本発明においては、第１の電子部品の配線及び／又は第２の電子部品の配線は、一部又は全部が電子部品の表面に埋設されていることが好ましい。
　本発明の他の一局面は、電子部品同士を電気的に接続する電子部品の接続方法であって、第１の電子部品の表面に形成された配線と第２の電子部品の表面に形成された配線とが向き合され、導電体を間に挟んで接合されることにより、第１の電子部品と第２の電子部品とが電気的に接続されていることを特徴とする電子部品の接続方法である。
　本発明によれば、電子部品同士を電気的に接続する場合に、パッドやランドを介さずに配線同士を接合するので、接続部でのインピーダンスの不整合の低減が図られる。
図１は、第１の実施形態に係る電子部品の接合形態を説明するための側面図である。 図２（ａ）は、第１の実施形態に係る第１の電子部品の表面を示すための平面図、図２（ｂ）は、第１の実施形態に係る第２の電子部品の表面を示すための平面図である。 図３は、第２の実施形態に係る電子部品の接合形態を説明するための側面図である。 図４は、第２の実施形態に係る電子部品の接合形態を得る方法の説明図である。 図５は、第３の実施形態に係る電子部品の接合形態を説明するための側面図である。 図６は、第３の実施形態に係る第２の電子部品の表面を示すための平面図である。 図７は、第３の実施形態に係る電子部品の接合形態を得る方法の説明図である。 図８は、第３の実施形態に係る第２の電子部品を得る方法の説明図である。 図９は、第４の実施形態に係る電子部品の接合形態を説明するための側面図である。 図１０は、第４の実施形態に係る電子部品の接合形態を得る方法の説明図である。 図１１は、第４の実施形態に係る第２の電子部品を得る方法の説明図である。 図１２は、凸形状体の先端部に配線が形成される変形例の説明図である。 図１３は、配線ズレのフェールセーフ機能の説明図である。 図１４は、配線ズレの別のフェールセーフ機能の説明図である。 図１５は、第５の実施形態に係る電子部品の接合形態を説明するための斜視図である。 図１６は、配線が電子部品の表面に埋設されていない場合の説明図である。 図１７は、配線の一部が電子部品の表面に埋設されている場合の説明図である。
　以下に示す各実施形態において、第１の電子部品及び第２の電子部品は、例えば、半導体チップと半導体チップ、半導体チップと基板、パッケージとパッケージ、パッケージと回路基板、回路基板と回路基板等である。また、これらが種々組み合されたものも本実施形態に含まれる。
　＜第１の実施形態＞
　本発明に係る電子部品のアセンブリでは、電子部品同士を電気的に接続する場合に、パッドやランドを介さずに配線同士を接合する接合形態を有するため、接続部でのインピーダンスの不整合の低減が図られる。なお、本発明において「電子部品のアセンブリ」とは、後述の図面等に参照されるように、２以上の電子部品が電気的に接続された電子部品の接合体を意味する。
　具体的には、図１及び図２を参照し、本発明の第１の実施形態を説明する。図中、符号１は第１の電子部品、符号２は第２の電子部品、符号１ａは第１の電子部品の表面、符号２ａは第２の電子部品の表面、符号１１は第１の電子部品の配線、符号１２は第２の電子部品の配線、符号１３は導電体としての半田である。
　図１に示すように、本実施形態では、第１の電子部品１の表面１ａに配線１１が形成され、第２の電子部品２の表面２ａに配線１２が形成され、第１の電子部品の配線１１と第２の電子部品の配線１２とが向き合され、導電体としての半田１３を間に挟んで接合されることにより、第１の電子部品１と第２の電子部品２とが電気的に接続されている。配線１１，１２は、第１、第２の電子部品１，２の内部から引き回され、表面１ａ，１ｂに露出している。
　図２（ａ）に示すように、第１の電子部品１の表面１ａには配線１１が複数形成されている。図２（ｂ）に示すように、第２の電子部品２の表面２ａにも第１の電子部品の配線１１に対応した位置に配線１２が複数形成されている。そして、対応し合う配線１１，１２同士が相互に重ね合されて接合されている。配線１１，１２の幅は、例えば２０μｍ等である。
　本実施形態では、導電体として半田１３が用いられている。この半田１３によって、第１の電子部品１と第２の電子部品２との電気的接続と機械的結合とが達成されている。半田１３は、配線１１，１２の幅内に略収められている。
　なお、第１の電子部品の配線１１と第２の電子部品の配線１２とは、相互に同じ方向に延びて相対的に長い距離で接合されてもよいし、相互に異なる方向に延びて相対的に短い距離で接合されてもよい。
　＜第２の実施形態＞
　図３及び図４を参照し、本発明の第２の実施形態を説明する。第１の実施形態と異なる部分のみ説明する。図中、符号１４は導電体としてのＡＣＰ（異方性導電ペースト：anisotropic conductive paste）又はＡＣＦ（異方性導電フィルム：anisotropic conductive film）、符号１４ａは導電性フィラー、符号１４ｂは樹脂組成物である。
　図３に示すように、本実施形態では、導電体としてＡＣＰ又はＡＣＦ１４が用いられている。ＡＣＰ及びＡＣＦ１４は、導電性フィラー１４ａを含有する樹脂組成物１４ｂである。このＡＣＰ又はＡＣＦ１４によって、第１の電子部品１と第２の電子部品２との電気的接続と機械的結合とが達成されている。ＡＣＰ又はＡＣＦ１４は、第１、第２の電子部品１，２間の間隙に充満している。ＡＣＰ又はＡＣＦ１４は、導通に関して異方性を有している。すなわち、接続方向（重ね合せ方向）の配線同士のみが導通し、隣接する配線間は絶縁を保つという性質がある。ＡＣＰ又はＡＣＦ１４の構成要素の中でもまさに導電体として機能する導電性フィラー１４ａは、重ね合された配線１１，１２間に挟み込まれ、配線１１，１２の幅内に略収められている。
　図３に示す電子部品の接合形態は、次のようにして得ることができる。図４に示すように、第１の電子部品１の表面１ａにＡＣＰ又はＡＣＦ１４を塗布又は形成する。第１の電子部品の配線１１がＡＣＰ又はＡＣＦ１４で被覆される。第１の電子部品１の表面１ａと第２の電子部品２の表面２ａとを向き合せ、第１の電子部品の配線１１と第２の電子部品の配線１２とを向き合せる。この状態で、第１の電子部品１と第２の電子部品２とを熱圧着する。ＡＣＰ又はＡＣＦ１４は、第１、第２の電子部品１，２間の間隙に充満するが、接続方向（重ね合せ方向）の配線１１，１２同士のみが導通し、重ね合された配線１１，１２同士のみが接合される。
　＜第３の実施形態＞
　図５～図８を参照し、本発明の第３の実施形態を説明する。第１、第２の実施形態と異なる部分のみ説明する。図中、符号１５は凸形状体、符号１８は絶縁基材、符号１９は樹脂皮膜、符号２０は配線パターン溝である。
　図５に示すように、本実施形態では、第２の電子部品２の表面２ａに凸形状体１５が形成され、この凸形状体１５の先端部に配線１２が形成され、この凸形状体１５の先端部において第１の電子部品の配線１１と第２の電子部品の配線１２とが接合されている。
　本実施形態では、凸形状体１５は、第２の電子部品２の表面２ａが凸形状に成形されたものである。本実施形態では、凸形状体１５は、円錐台形状である。ただし、これに限らず、他の形状、例えば角錐台形状、円柱形状、角柱形状、半球形状等でもよい。
　図６に示すように、第２の電子部品２の表面２ａには配線１２が複数形成されている。配線１２は、凸形状体１５の先端部を通過している。第１の電子部品１の表面１ａにも第２の電子部品の配線１２に対応した位置に配線１１が複数形成されている。そして、対応し合う配線１１，１２同士が相互に重ね合されて接合されている。
　図５に示す電子部品の接合形態は、次のようにして得ることができる。図７に示すように、第１の電子部品１の表面１ａにＡＣＰ又はＡＣＦ１４を塗布又は形成する。第１の電子部品の配線１１がＡＣＰ又はＡＣＦ１４で被覆される。第１の電子部品１の表面１ａと第２の電子部品２の表面２ａとを向き合せ、第１の電子部品の配線１１と第２の電子部品の配線１２とを向き合せる。この状態で、第１の電子部品１と第２の電子部品２とを熱圧着する。その場合、第２の電子部品２の凸形状体１５の先端部が第１の電子部品１の表面１ａを押圧することになる。ＡＣＰ又はＡＣＦ１４は、第１、第２の電子部品１，２間の間隙に充満するが、接続方向（重ね合せ方向）の配線１１，１２同士のみが導通し、重ね合された配線１１，１２同士のみが接合される。
　第２の電子部品２は、次のようにして得ることができる。まず、図８（Ａ）に示すように、表面が凸形状に成形された絶縁基材１８を準備する。表面が凸形状に成形されたものは凸形状体１５を構成する。
　次に、図８（Ｂ）に示すように、絶縁基材１８の表面に樹脂皮膜１９を形成する。樹脂皮膜１９の表面は、絶縁基材１８に追従して凹凸形状を呈する。
　次に、図８（Ｃ）に示すように、樹脂皮膜１９の表面側から樹脂皮膜１９の厚みと同じ又は厚みを超える深さの配線パターン溝（図例は樹脂皮膜１９の厚みと同じ深さの配線パターン溝）２０を形成する。配線パターン溝２０は、第２の電子部品２の内部に通じる連通孔を含む。このような配線パターン溝２０は、例えば樹脂皮膜１９の表面側からレーザー加工等することにより精度よく形成することができる。
　次に、配線パターン溝２０の表面にメッキ触媒又はその前駆体を被着させる。次に、樹脂皮膜１９を溶解又は膨潤させることにより除去する。次に、無電解メッキを行うことによりメッキ触媒又はその前駆体から形成されるメッキ触媒が残留する部分のみにメッキ膜を形成する。メッキ膜は配線１２を構成する。これにより、図８（Ｄ）に示すように、第２の電子部品２の表面２ａに配線パターン溝２０通りに配線１２が形成される。
　なお、本実施形態では、第２の電子部品２の表面２ａに凸形状体１５が形成され、凸形状体１５の先端部に配線１２が形成されたが、これに代えて又はこれと共に、第１の電子部品１の表面１ａに凸形状体１５が形成され、凸形状体１５の先端部に配線１１が形成されてもよい。
　＜第４の実施形態＞
　図９～図１１を参照し、本発明の第４の実施形態を説明する。第１～第３の実施形態と異なる部分のみ説明する。図中、符号１５は凸形状体、符号１６は支持体、符号１６ａは凸形状、符号１７は絶縁体（絶縁性樹脂）、符号１８は絶縁基材、符号１８ａは内部回路、符号１９は樹脂皮膜、符号２０は配線パターン溝である。
　図９に示すように、本実施形態では、第２の電子部品２の表面２ａに凸形状体１５が形成され、この凸形状体１５の先端部に配線１２が形成され、この凸形状体１５の先端部において第１の電子部品の配線１１と第２の電子部品の配線１２とが接合されている。
　本実施形態では、凸形状体１５は、第２の電子部品２に内蔵された支持体１６が絶縁体１７で被覆されることによって形成されたもの、第２の電子部品２の表面の凸形状１６ａが絶縁体１７で被覆されることによって形成されたもの、及び、第２の電子部品２の表面の凸形状が絶縁体１７で形成されたもの１６ｂである（２種以上の凸形状体１５が混載されたパターン）。ただし、これに限らず、凸形状体１５は、第２の電子部品２に内蔵された支持体１６が絶縁体１７で被覆されることによって形成されたもののみ、第２の電子部品２の表面の凸形状１６ａが絶縁体１７で被覆されることによって形成されたもののみ、又は、第２の電子部品２の表面の凸形状が絶縁体１７で形成されたもの１６ｂのみでもよい。
　本実施形態では、凸形状体１５は、円錐台形状である。ただし、これに限らず、他の形状、例えば角錐台形状、円柱形状、角柱形状、半球形状等でもよい。
　図９に示す電子部品の接合形態は、次のようにして得ることができる。図１０に示すように、第１の電子部品１の表面１ａにＡＣＰ又はＡＣＦ１４を塗布又は形成する。第１の電子部品の配線１１がＡＣＰ又はＡＣＦ１４で被覆される。第１の電子部品１の表面１ａと第２の電子部品２の表面２ａとを向き合せ、第１の電子部品の配線１１と第２の電子部品の配線１２とを向き合せる。この状態で、第１の電子部品１と第２の電子部品２とを熱圧着する。その場合、第２の電子部品２の凸形状体１５の先端部が第１の電子部品１の表面１ａを押圧することになる。ＡＣＰ又はＡＣＦ１４は、第１、第２の電子部品１，２間の間隙に充満するが、接続方向（重ね合せ方向）の配線１１，１２同士のみが導通し、重ね合された配線１１，１２同士のみが接合される。
　第２の電子部品２は、次のようにして得ることができる。まず、図１１（Ａ）に示すように、表面から複数の支持体１６の先端部が突出し、表面に複数の凸形状１６ａが形成され、表面に内部回路１８ａが形成された絶縁基材１８を準備する。
　次に、図１１（Ｂ）に示すように、絶縁基材１８の表面に絶縁体１７を形成する。絶縁体１７の表面は、支持体１６の先端部及び凸形状１６ａに追従して凹凸形状を呈する。また、このとき、絶縁体１７で形成された凸形状１６ｂが形成される。
　次に、図１１（Ｃ）に示すように、絶縁体１７の表面に樹脂皮膜１９を形成する。樹脂皮膜１９の表面は、絶縁体１７に追従して凹凸形状を呈する。
　次に、図１１（Ｄ）に示すように、樹脂皮膜１９の表面側から樹脂皮膜１９の厚みと同じ又は厚みを超える深さの配線パターン溝（図例は樹脂皮膜１９の厚みと同じ深さの配線パターン溝）２０を形成する。配線パターン溝２０は、第２の電子部品２の内部に通じる連通孔を含む。連通孔は絶縁基材１８の表面の内部回路１８ａに到達している。このような配線パターン溝２０は、例えば樹脂皮膜１９の表面側からレーザー加工等することにより精度よく形成することができる。
　次に、配線パターン溝２０の表面にメッキ触媒又はその前駆体を被着させる。次に、樹脂皮膜１９を溶解又は膨潤させることにより除去する。次に、無電解メッキを行うことによりメッキ触媒又はその前駆体から形成されるメッキ触媒が残留する部分のみにメッキ膜を形成する。メッキ膜は配線１２を構成する。これにより、図１１（Ｅ）に示すように、第２の電子部品２の表面２ａに配線パターン溝２０通りに配線１２が形成される。配線１２は内部回路１８ａと接続している。
　なお、本実施形態では、第２の電子部品２の表面２ａに凸形状体１５が形成され、凸形状体１５の先端部に配線１２が形成されたが、これに代えて又はこれと共に、第１の電子部品１の表面１ａに凸形状体１５が形成され、凸形状体１５の先端部に配線１１が形成されてもよい。
　図１２は、凸形状体１５の先端部に配線１２が形成される変形例の説明図である。凸形状体１５の先端部を通過する第２の電子部品の配線１２を実線で示し、この配線１２と接合される第１の電子部品の配線１１を破線で示してある。図示するように、凸形状体１５の先端部を通過する第２の電子部品の配線１２は、１本に限らず、２本でもよく、３本以上でも構わない。そして、これに対応して、第１の電子部品の配線１１もまた、１本に限らず、２本でもよく、３本以上でも構わない。
　図１３、図１４は、配線ズレのフェールセーフ機能の説明図である。凸形状体１５の先端部を通過する第２の電子部品の配線１２を実線で示し、この配線１２と接合される第１の電子部品の配線１１を破線で示してある。前述したように、第１の電子部品の配線１１と第２の電子部品の配線１２とは、相互に同じ方向に延びて相対的に長い距離で接合されてもよいし、相互に異なる方向に延びて相対的に短い距離で接合されてもよい。前者の場合、配線１１，１２間で位置ズレが起きると、配線１１，１２同士のオーバーラップが足りずに接合不良となり得る。そこで、図１３に示すように、配線１１，１２を蛇行させたり、図１４に示すように、一方の配線を曲折させることにより、配線１１，１２同士のオーバーラップを確保することが好ましい。
　＜第５の実施形態＞
　図１５を参照し、本発明の第５の実施形態を説明する。第１～第４の実施形態と異なる部分のみ説明する。
　図１５に示すように、本実施形態では、第２の電子部品２の表面２ａに凸形状体１５が形成され、この凸形状体１５の先端部に配線１２が形成されていると共に、第１の電子部品１の表面１ａにも凸形状体１５が形成され、この凸形状体１５の先端部に配線１１が形成されて、これらの第２の電子部品２の凸形状体１５と第１の電子部品１の凸形状体１５との先端部において第１の電子部品の配線１１と第２の電子部品の配線１２とが接合されている。
　本実施形態では、凸形状体１５，１５は、第１の電子部品１の表面１ａ又は第２の電子部品２の表面２ａを形成する絶縁体１７，１７により全部が形成されている。本実施形態では、凸形状体１５は、所定長さの凸条形状である。
　図１５に示すように、第１の電子部品１の凸形状体１５の先端部に複数の配線１１…１１が形成されている。第２の電子部品２の凸形状体１５の先端部にもこれらに対応した位置に複数の配線１２…１２が形成されている。そして、対応し合う配線１１…１１，１２…１２同士が相互に重ね合されて接合される。
　ところで、配線１１，１２は、図１６に例示するように、電子部品１，２の表面１ａ，２ａに埋設されていなくてもよいし、図１７に例示するように、電子部品１，２の表面１ａ，２ａに一部又は全部が埋設されていてもよい（図例は一部が埋設）。
　電子部品１，２の表面１ａ，２ａに埋設されない配線１１，１２は、例えば、前述の図１１（Ｄ）において、樹脂皮膜１９の表面側から樹脂皮膜１９の厚みと同じ深さの配線パターン溝２０を形成することにより得ることができる。一方、電子部品１，２の表面１ａ，２ａに埋設される配線１１，１２は、例えば、前述の図１１（Ｄ）において、樹脂皮膜１９の表面側から樹脂皮膜１９の厚みを超える深さの配線パターン溝２０を形成することにより得ることができる。後者の場合、電子部品１，２の表面１ａ，２ａを形成する絶縁体１７，１７の表面に凹溝１ｂ，２ｂが形成され、この凹溝１ｂ，２ｂに配線１１，１２を構成するメッキ膜が入り込むことになる。
　なお、図１７は、断面形状が半円形状の凹溝１ｂ，２ｂを例示するが、これに限らず、断面形状が他の形状、例えば三角形状や四角形状等でもよい（図中鎖線参照）。
　＜実施形態の作用効果＞
　以上、具体例を挙げて詳しく説明したように、本実施形態に係る電子部品１，２の接合形態（アセンブリ）は、第１の電子部品１の表面１ａに形成された配線１１と第２の電子部品２の表面２ａに形成された配線１２とが向き合され、導電体１３，１４を間に挟んで接合されることにより、第１の電子部品１と第２の電子部品２とが電気的に接続されているものである。
　これにより、第１の電子部品１と第２の電子部品２とを電気的に接続する場合に、サイズが異なるパッドやランドを介さずに、サイズが同様で一様の配線１１，１２同士を接合するので、接続部でのインピーダンスの不整合の低減が図られる。
　しかも、導電体としての半田１３又は導電性フィラー１４ａは、配線１１，１２の幅内に略収められているから、この導電体１３，１４を含めても、接続部でのインピーダンスの不整合の低減が図られる。
　また、導電体として半田１３又は導電性フィラー１４ａを含有する樹脂組成物１４ｂ（ＡＣＰ又はＡＣＦ１４）を用いることにより、第１の電子部品１と第２の電子部品２との電気的接続と機械的結合との両方が達成される。
　また、本実施形態に係る電子部品１，２の接合形態（アセンブリ）は、第１の電子部品１の表面１ａ及び／又は第２の電子部品２の表面２ａに凸形状体１５が形成され、この凸形状体１５の先端部に配線１１，１２が形成され、この凸形状体１５の先端部において第１の電子部品の配線１１と第２の電子部品の配線１２とが接合されているものである。
　これにより、第１の電子部品１と第２の電子部品２とを熱圧着する場合に、一方の電子部品の凸形状体１５の先端部が他方の電子部品の表面を押圧し、又は、両方の電子部品の凸形状体１５、１５の先端部同士が相互に押圧し合うことになる。そのため、押圧力が接続部に集中して、第１の電子部品の配線１１と第２の電子部品の配線１２との接合促進が図られる。
　その場合に、凸形状体１５は、第１の電子部品１の表面１ａ又は第２の電子部品２の表面２ａが凸形状に成形されたもの、第１の電子部品１又は第２の電子部品２に内蔵された支持体１６が絶縁体１７で被覆されることによって形成されたもの、第１の電子部品１の表面又は第２の電子部品２の表面の凸形状１６ａが絶縁体１７で被覆されることによって形成されたもの、及び／又は、第１の電子部品１の表面又は第２の電子部品２の表面の凸形状が絶縁体１７で形成されたもの１６ｂであってよい。あるいは、凸形状体１５は、電子部品１，２の表面１ａ，２ａを形成する絶縁体１７により全部が形成されていてもよい。凸形状体１５は、これらのうちのいずれか１種又は任意の２種以上が混載されたものであってよい。電子部品１，２が、例えば、半導体チップ、基板、パッケージ、回路基板等のいずれであるかに応じて、凸形状体１５の形成パターンがこれらの中から選択可能となる。
　また、配線１１，１２は、一部又は全部が電子部品１，２の表面１ａ，２ａに埋設されていることが好ましい。配線１１，１２の位置ズレや脱落が抑制されるからである。
　また、配線ズレのフェールセーフ機能を備えることにより、配線１１，１２間で位置ズレが起きても、配線１１，１２同士のオーバーラップを確保することができ、接合不良を回避することができる。
１　第１の電子部品
２　第２の電子部品
１ａ，２ａ　電子部品の表面
１ｂ，２ｂ　凹溝
１１，１２　配線
１３　半田（導電体）
１４　ＡＣＰ、ＡＣＦ（導電体）
１４ａ　導電性フィラー
１４ｂ　樹脂組成物
１５　凸形状体
１６　支持体
１６ａ　凸形状
１６ｂ　絶縁体で形成された凸形状
１７　絶縁体（絶縁性樹脂）
１８　絶縁基材
１８ａ　内部回路
１９　樹脂皮膜
２０　配線パターン溝

Claims (6)

  1. 　電子部品同士が電気的に接続された電子部品のアセンブリであって、
    　第１の電子部品の表面に形成された配線と第２の電子部品の表面に形成された配線とが向き合され、導電体を間に挟んで接合されることにより、第１の電子部品と第２の電子部品とが電気的に接続されていることを特徴とする電子部品のアセンブリ。
  2. 　導電体は、半田又は導電性フィラーを含有する樹脂組成物であることを特徴とする請求項１に記載の電子部品のアセンブリ。
  3. 　第１の電子部品の表面及び／又は第２の電子部品の表面に凸形状体が形成され、この凸形状体の先端部に配線が形成され、この凸形状体の先端部において第１の電子部品の配線と第２の電子部品の配線とが接合されていることを特徴とする請求項１又は２に記載の電子部品のアセンブリ。
  4. 　凸形状体は、第１の電子部品の表面又は第２の電子部品の表面が凸形状に成形されたもの、第１の電子部品又は第２の電子部品に内蔵された支持体が絶縁体で被覆されることによって形成されたもの、第１の電子部品の表面又は第２の電子部品の表面の凸形状が絶縁体で被覆されることによって形成されたもの、及び／又は、第１の電子部品の表面又は第２の電子部品の表面の凸形状が絶縁体で形成されたものであることを特徴とする請求項３に記載の電子部品のアセンブリ。
  5. 　第１の電子部品の配線及び／又は第２の電子部品の配線は、一部又は全部が電子部品の表面に埋設されていることを特徴とする請求項１から４のいずれか１項に記載の電子部品のアセンブリ。
  6. 　電子部品同士を電気的に接続する電子部品の接続方法であって、
    　第１の電子部品の表面に形成された配線と第２の電子部品の表面に形成された配線とが向き合され、導電体を間に挟んで接合されることにより、第１の電子部品と第２の電子部品とが電気的に接続されていることを特徴とする電子部品の接続方法。
PCT/JP2011/005895 2010-10-25 2011-10-20 電子部品の接合形態 WO2012056661A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201180051390XA CN103180944A (zh) 2010-10-25 2011-10-20 电子元件的接合方式
US13/869,553 US9204530B2 (en) 2010-10-25 2013-04-24 Electronic components assembly

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010238942 2010-10-25
JP2010-238942 2010-10-25

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/869,553 Continuation-In-Part US9204530B2 (en) 2010-10-25 2013-04-24 Electronic components assembly

Publications (1)

Publication Number Publication Date
WO2012056661A1 true WO2012056661A1 (ja) 2012-05-03

Family

ID=45993409

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/005895 WO2012056661A1 (ja) 2010-10-25 2011-10-20 電子部品の接合形態

Country Status (4)

Country Link
US (1) US9204530B2 (ja)
CN (1) CN103180944A (ja)
TW (1) TWI470710B (ja)
WO (1) WO2012056661A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9560738B2 (en) * 2012-11-22 2017-01-31 Lg Innotek Co., Ltd. Touch window

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595210A (ja) * 1991-10-03 1993-04-16 Mitsubishi Electric Corp モノリシツクマイクロ波集積回路
JPH08298272A (ja) * 1995-04-26 1996-11-12 Rohm Co Ltd 半導体装置の製法
JPH08321671A (ja) * 1995-05-26 1996-12-03 Nec Corp バンプ電極の構造およびその製造方法
JP2000150575A (ja) * 1998-11-13 2000-05-30 Sony Corp 半導体装置の実装方法および半導体装置組立体
JP2005136402A (ja) * 2003-10-09 2005-05-26 Seiko Epson Corp 半導体装置とその製造方法、回路基板、電気光学装置、及び電子機器
JP2008294318A (ja) * 2007-05-28 2008-12-04 Nec Corp 半導体装置およびその製造方法
JP2010056202A (ja) * 2008-08-27 2010-03-11 Kyocera Corp 積層型半導体パッケージおよびそれに用いられるコンデンサ、並びに積層型半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
SE516748C2 (sv) * 1996-12-19 2002-02-26 Ericsson Telefon Ab L M Sammansättningsstruktur innefattande minst ett flip-chip och ett substrat
JP2000183467A (ja) * 1998-12-14 2000-06-30 Oki Electric Ind Co Ltd 半田付着防止機構
JP3216622B2 (ja) 1998-12-18 2001-10-09 日本電気株式会社 半導体装置
KR100370398B1 (ko) * 2000-06-22 2003-01-30 삼성전자 주식회사 전자 및 ｍｅｍｓ 소자의 표면실장형 칩 규모 패키징 방법
DE10233641B4 (de) 2002-07-24 2007-08-23 Infineon Technologies Ag Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung
FR2859725B1 (fr) 2003-09-16 2006-03-10 Neovacs Procede a haut rendement pour l'obtention d'anticorps humains neutralisant l'activite biologique d'une cytokine humaine
KR101286379B1 (ko) * 2003-11-10 2013-07-15 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
JP5259095B2 (ja) * 2006-06-19 2013-08-07 新光電気工業株式会社 半導体装置
GB2453765A (en) * 2007-10-18 2009-04-22 Novalia Ltd Product packaging with printed circuit and means for preventing a short circuit
JP5622137B2 (ja) * 2007-10-29 2014-11-12 デクセリアルズ株式会社 電気的接続体及びその製造方法
JP4656212B2 (ja) 2008-06-13 2011-03-23 ソニー株式会社 接続方法
US8198186B2 (en) * 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US8378485B2 (en) * 2009-07-13 2013-02-19 Lsi Corporation Solder interconnect by addition of copper

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595210A (ja) * 1991-10-03 1993-04-16 Mitsubishi Electric Corp モノリシツクマイクロ波集積回路
JPH08298272A (ja) * 1995-04-26 1996-11-12 Rohm Co Ltd 半導体装置の製法
JPH08321671A (ja) * 1995-05-26 1996-12-03 Nec Corp バンプ電極の構造およびその製造方法
JP2000150575A (ja) * 1998-11-13 2000-05-30 Sony Corp 半導体装置の実装方法および半導体装置組立体
JP2005136402A (ja) * 2003-10-09 2005-05-26 Seiko Epson Corp 半導体装置とその製造方法、回路基板、電気光学装置、及び電子機器
JP2008294318A (ja) * 2007-05-28 2008-12-04 Nec Corp 半導体装置およびその製造方法
JP2010056202A (ja) * 2008-08-27 2010-03-11 Kyocera Corp 積層型半導体パッケージおよびそれに用いられるコンデンサ、並びに積層型半導体装置

Also Published As

Publication number Publication date
US20130265729A1 (en) 2013-10-10
US9204530B2 (en) 2015-12-01
TW201240000A (en) 2012-10-01
TWI470710B (zh) 2015-01-21
CN103180944A (zh) 2013-06-26

Similar Documents

Publication Publication Date Title
KR100896248B1 (ko) 프린트 배선판의 접속 구조체
JP5657217B2 (ja) 集合ケーブル
WO2016072338A1 (ja) 伝送線路ケーブル
JP2007071980A (ja) 光モジュール
US11956903B2 (en) Transmission line, method of manufacturing transmission line, and electronic apparatus
US10181662B2 (en) Switching device having a push button
US20130334684A1 (en) Substrate structure and package structure
WO2019146252A1 (ja) 基板接合構造、および基板の接合方法
JP5544102B2 (ja) 基板の接続方式および基板の接続方法
JP4825075B2 (ja) フレキシブル配線基板間の接続構造及びフレキシブル配線基板間の接続方法
WO2019131647A1 (ja) 基板、および基板接合構造
WO2021039325A1 (ja) モジュール
US7598608B2 (en) Mounting substrate
WO2019146253A1 (ja) 基板接合構造
WO2012056661A1 (ja) 電子部品の接合形態
KR100671808B1 (ko) 반도체 장치
WO2017150060A1 (ja) 実装構造及びモジュール
JP6683264B2 (ja) 電子機器
KR100516815B1 (ko) 반도체장치
JP2007165752A (ja) プリント配線板およびその接続構造
WO2021060161A1 (ja) モジュール
CN114188312B (zh) 封装屏蔽结构和屏蔽结构制作方法
JP5582618B2 (ja) プローブ基板の製造方法
JP4430419B2 (ja) 平行導電回路シートを用いた電子回路及びその製造方法
CN116130995A (zh) 电连接器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11835808

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11835808

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP