ATE458249T1 - Doppelbit monos speicherzellgebrauch für breite programbandbreite - Google Patents

Doppelbit monos speicherzellgebrauch für breite programbandbreite

Info

Publication number
ATE458249T1
ATE458249T1 AT02368025T AT02368025T ATE458249T1 AT E458249 T1 ATE458249 T1 AT E458249T1 AT 02368025 T AT02368025 T AT 02368025T AT 02368025 T AT02368025 T AT 02368025T AT E458249 T1 ATE458249 T1 AT E458249T1
Authority
AT
Austria
Prior art keywords
memory cell
bit line
program
cell use
monos memory
Prior art date
Application number
AT02368025T
Other languages
English (en)
Inventor
Ogura Seiki
Tomoko Ogura
Original Assignee
Halo Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Halo Inc filed Critical Halo Inc
Application granted granted Critical
Publication of ATE458249T1 publication Critical patent/ATE458249T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
AT02368025T 2001-03-15 2002-03-14 Doppelbit monos speicherzellgebrauch für breite programbandbreite ATE458249T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US27587001P 2001-03-15 2001-03-15
US27915101P 2001-03-27 2001-03-27
US28875601P 2001-05-04 2001-05-04

Publications (1)

Publication Number Publication Date
ATE458249T1 true ATE458249T1 (de) 2010-03-15

Family

ID=27402765

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02368025T ATE458249T1 (de) 2001-03-15 2002-03-14 Doppelbit monos speicherzellgebrauch für breite programbandbreite

Country Status (7)

Country Link
US (1) US6459622B1 (de)
EP (1) EP1246196B1 (de)
JP (1) JP4153222B2 (de)
KR (1) KR20030009082A (de)
AT (1) ATE458249T1 (de)
DE (1) DE60235335D1 (de)
TW (1) TW548841B (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531350B2 (en) * 2001-02-22 2003-03-11 Halo, Inc. Twin MONOS cell fabrication method and array organization
JP3640175B2 (ja) * 2001-04-13 2005-04-20 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP4715024B2 (ja) * 2001-05-08 2011-07-06 セイコーエプソン株式会社 不揮発性半導体記憶装置のプログラム方法
TW508590B (en) * 2001-05-09 2002-11-01 Macronix Int Co Ltd Operating method of flash memory with symmetrical dual channel
JP2002334588A (ja) * 2001-05-11 2002-11-22 Seiko Epson Corp 不揮発性半導体記憶装置のプログラム方法
JP2003141889A (ja) 2001-07-06 2003-05-16 Halo Lsi Inc 記憶サイト選択方法、コントロール・ゲート線デコーダ、及びコントロール・ゲート信号デコード装置
EP1274095A3 (de) 2001-07-06 2005-05-25 Halo Lsi Design and Device Technology Inc. Doppel-MONOS-Zellenmatrix mit Metall-Bitleitungsorganisation und Einzelzellenbetrieb
US6631089B1 (en) 2001-07-06 2003-10-07 Halo Lsi, Inc. Bit line decoding scheme and circuit for dual bit memory array
ATE392697T1 (de) 2001-07-06 2008-05-15 Halo Lsi Design & Device Tech Bitzeilen-selektions-dekodierung und schaltung für doppelbitspeicher mit doppelbitselektion
US6897522B2 (en) * 2001-10-31 2005-05-24 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6925007B2 (en) * 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
JP3867624B2 (ja) * 2002-06-06 2007-01-10 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
US7630237B2 (en) 2003-02-06 2009-12-08 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
US6856551B2 (en) * 2003-02-06 2005-02-15 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9029196B2 (en) * 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
KR101237172B1 (ko) 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
WO2005109438A2 (en) * 2004-05-06 2005-11-17 Halo Lsi, Inc. Non-volatile memory dynamic operations
JP5007017B2 (ja) * 2004-06-30 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US7272040B2 (en) * 2005-04-29 2007-09-18 Infineon Technologies Ag Multi-bit virtual-ground NAND memory device
KR100727411B1 (ko) * 2005-12-29 2007-06-13 삼성전자주식회사 오픈 비트라인 구조의 메모리 셀 어레이를 가지는 반도체메모리 장치의 승압전압 발생회로 및 승압전압 발생방법
KR100902008B1 (ko) * 2007-02-09 2009-06-12 삼성전자주식회사 메모리 셀에 멀티 비트 데이터를 저장하는 플래시 메모리를 포함한 메모리 시스템
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
JP5164520B2 (ja) * 2007-10-19 2013-03-21 ルネサスエレクトロニクス株式会社 不揮発性半導体メモリ及びデータプログラム／消去方法
JP5355980B2 (ja) * 2008-09-29 2013-11-27 株式会社東芝 不揮発性半導体記憶装置及びその駆動方法
JP5462461B2 (ja) * 2008-09-30 2014-04-02 株式会社東芝 不揮発性半導体記憶装置及びその駆動方法
US9947687B2 (en) 2016-06-08 2018-04-17 Micron Technology, Inc. Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator
US10790304B2 (en) 2018-07-26 2020-09-29 Micron Technology, Inc. Integrated assemblies comprising ferroelectric transistors and non-ferroelectric transistors

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6215148B1 (en) * 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6388293B1 (en) 1999-10-12 2002-05-14 Halo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, operating method of the same and nonvolatile memory array
US6255166B1 (en) 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
JP2003508920A (ja) 1999-08-27 2003-03-04 マクロニックス・アメリカ・インコーポレーテッド ２ビット保存用の不揮発性記憶装置構造体及びその製造方法
US6248633B1 (en) 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
US6172905B1 (en) * 2000-02-01 2001-01-09 Motorola, Inc. Method of operating a semiconductor device

Also Published As

Publication number Publication date
KR20030009082A (ko) 2003-01-29
EP1246196B1 (de) 2010-02-17
US20020131304A1 (en) 2002-09-19
US6459622B1 (en) 2002-10-01
EP1246196A3 (de) 2007-07-04
DE60235335D1 (de) 2010-04-01
JP4153222B2 (ja) 2008-09-24
EP1246196A2 (de) 2002-10-02
JP2003036683A (ja) 2003-02-07
TW548841B (en) 2003-08-21

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