ATE267447T1 - Programmierverfahren für einen nichtflüchtigen halbleiterspeicher - Google Patents

Programmierverfahren für einen nichtflüchtigen halbleiterspeicher

Info

Publication number
ATE267447T1
ATE267447T1 AT02002973T AT02002973T ATE267447T1 AT E267447 T1 ATE267447 T1 AT E267447T1 AT 02002973 T AT02002973 T AT 02002973T AT 02002973 T AT02002973 T AT 02002973T AT E267447 T1 ATE267447 T1 AT E267447T1
Authority
AT
Austria
Prior art keywords
programming
voltage
semiconductor memory
control gate
volatile semiconductor
Prior art date
Application number
AT02002973T
Other languages
English (en)
Inventor
Masahiro Kanai
Teruhiko Kamei
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Application granted granted Critical
Publication of ATE267447T1 publication Critical patent/ATE267447T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
AT02002973T 2001-05-08 2002-02-11 Programmierverfahren für einen nichtflüchtigen halbleiterspeicher ATE267447T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001137165A JP4715024B2 (ja) 2001-05-08 2001-05-08 不揮発性半導体記憶装置のプログラム方法

Publications (1)

Publication Number Publication Date
ATE267447T1 true ATE267447T1 (de) 2004-06-15

Family

ID=18984311

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02002973T ATE267447T1 (de) 2001-05-08 2002-02-11 Programmierverfahren für einen nichtflüchtigen halbleiterspeicher

Country Status (7)

Country Link
US (1) US6587381B2 (de)
EP (1) EP1256960B1 (de)
JP (1) JP4715024B2 (de)
KR (1) KR100446402B1 (de)
CN (1) CN1228786C (de)
AT (1) ATE267447T1 (de)
DE (1) DE60200498T2 (de)

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JP3659205B2 (ja) * 2001-08-30 2005-06-15 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその駆動方法
JP3843869B2 (ja) * 2002-03-15 2006-11-08 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3821032B2 (ja) * 2002-03-20 2006-09-13 セイコーエプソン株式会社 ファイルストレージ型不揮発性半導体記憶装置
JP3815381B2 (ja) * 2002-06-06 2006-08-30 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3867624B2 (ja) 2002-06-06 2007-01-10 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3871049B2 (ja) * 2002-12-10 2007-01-24 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004199738A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 不揮発性記憶装置
JP3985689B2 (ja) * 2003-02-21 2007-10-03 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004265508A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 不揮発性半導体記憶装置
JP3873908B2 (ja) 2003-02-28 2007-01-31 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
JP3786095B2 (ja) * 2003-02-28 2006-06-14 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3767588B2 (ja) * 2003-08-29 2006-04-19 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその制御方法
JP4196191B2 (ja) * 2003-09-09 2008-12-17 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその制御方法
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CN101373636B (zh) * 2007-08-20 2010-12-22 中芯国际集成电路制造(上海)有限公司 防止存储器阵列产生位线干扰的方法
US7672163B2 (en) * 2007-09-14 2010-03-02 Sandisk Corporation Control gate line architecture
JP5266085B2 (ja) * 2009-02-17 2013-08-21 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
KR101849176B1 (ko) 2012-01-06 2018-04-17 삼성전자주식회사 2-트랜지스터 플래시 메모리 및 2-트랜지스터 플래시 메모리의 프로그램 방법
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KR102083826B1 (ko) * 2013-05-13 2020-03-03 주식회사 실리콘웍스 표시 장치의 가비지 프로세싱 회로
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US9997253B1 (en) 2016-12-08 2018-06-12 Cypress Semiconductor Corporation Non-volatile memory array with memory gate line and source line scrambling
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US11309324B2 (en) * 2020-07-28 2022-04-19 Globalfoundries Singapore Pte. Ltd. Compact memory cell with a shared conductive word line and methods of making such a memory cell

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Also Published As

Publication number Publication date
DE60200498D1 (de) 2004-06-24
JP2002334587A (ja) 2002-11-22
CN1399280A (zh) 2003-02-26
EP1256960A1 (de) 2002-11-13
KR100446402B1 (ko) 2004-09-01
US6587381B2 (en) 2003-07-01
US20030002344A1 (en) 2003-01-02
KR20030009120A (ko) 2003-01-29
JP4715024B2 (ja) 2011-07-06
EP1256960B1 (de) 2004-05-19
CN1228786C (zh) 2005-11-23
DE60200498T2 (de) 2005-06-02

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