TWI404114B - 具有在基板上之窄互連部位之倒裝晶片互連 - Google Patents

具有在基板上之窄互連部位之倒裝晶片互連 Download PDF

Info

Publication number
TWI404114B
TWI404114B TW095110605A TW95110605A TWI404114B TW I404114 B TWI404114 B TW I404114B TW 095110605 A TW095110605 A TW 095110605A TW 95110605 A TW95110605 A TW 95110605A TW I404114 B TWI404114 B TW I404114B
Authority
TW
Taiwan
Prior art keywords
interconnect
width
substrate
pad
narrow
Prior art date
Application number
TW095110605A
Other languages
English (en)
Other versions
TW200723355A (en
Inventor
Rajendra D Pendse
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200723355A publication Critical patent/TW200723355A/zh
Application granted granted Critical
Publication of TWI404114B publication Critical patent/TWI404114B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H01L2224/81211—Applying energy for connecting using a reflow oven with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

具有在基板上之窄互連部位之倒裝晶片互連
本發明係關於半導體封裝，且特定而言，係關於倒裝晶片互連。
倒裝晶片封裝包括裝配於封裝基板上之半導體晶粒，該晶粒之主動側面朝該基板。該基板由介電層與至少一個金屬層組成，金屬層經圖案化以提供基板電路，其包括其他特徵中通向互連墊之跡線("引線")。該金屬層可藉由例如光罩及蝕刻製程圖案化。通常，晶粒中電路與基板中電路之互連藉由與晶粒上互連墊之陣列附接且與基板上互連墊(常稱為"抓取墊")之對應(互補)陣列接合之凸塊而獲得。抓取墊通常比引線寬，且可為例如引線之標稱寬度或設計寬度之約2至4倍寬。
積體電路上電子特徵之區域密度增長巨大，且具有更大密度電路特徵之晶片亦可具有更大密度之位點("晶粒墊")以便與封裝基板上之電路互連。
在使用封裝之設備中，封裝藉由封裝與下伏電路之間之二級互連(例如接腳、第二互連焊球)連接至下伏電路，諸如印刷電路板(例如"母板")。二級互連具有較倒裝晶片互連大的間距，因此基板上布線通常"散開"。基板上金屬層圖案化技術的重大進步使微細線路與空間之構造成為可能，但在習知排列中，相鄰墊之間的空間限制了可自陣列中較內側之抓取墊跳出之跡線的數目，且晶粒下方之抓取墊與封裝之外部接腳之間的散開布線通常形成於封裝基板內之多層金屬層上。對於複雜互連陣列，要求具有多層之基板在晶粒墊與封裝上二級互連之間完成布線。
多層基板費用昂貴，且習知倒裝晶片結構中僅基板通常就佔封裝成本的一半以上(在有些典型實例中約為60%)。多層基板之高成本已為限制倒裝晶片技術在主流產品中繁衍的因素。
習知倒裝晶片結構中跳出布線圖案通常引起額外的電寄生現象，因為布線包括訊號傳輸路徑中配線層之間之短程未屏蔽之配線與通孔。電寄生會大大限制封裝效能。
本發明之倒裝晶片互連藉由使互連凸塊直接連接在窄互連墊或窄墊上而非連接在習知抓取墊上來完成。本發明之窄墊寬度根據連接至窄墊上之互連凸塊之基底直徑選擇。特定而言，窄墊寬度比互連凸塊之基底直徑小(諸如在約20%至約80%範圍內)。本發明提供跡線在基板上更有效的布線。特定而言，訊號布線可完全形成於基板之單金屬層內。此減少了基板內層之數目，且在單層內形成訊號跡線亦容許基板必須滿足之通孔、線路及空間設計規則之某種程度之緩和。此對基板之簡化大大降低倒裝晶片封裝的總體成本。窄墊上凸塊之架構亦有助於消除來自基板設計之如通孔與"嵌柱"之該等特徵，且使微帶能控制用於訊號傳輸之電阻抗環境，藉此大大改良效能。
在一普通態樣中，本發明特別描述了具有與晶粒上之互連墊附接且與基板上之對應窄互連墊配合之焊料凸塊之倒裝晶片互連。
另一普通態樣中，本發明特別描述了包括具有與主動表面內之互連墊附接之焊料凸塊之晶粒以及具有晶粒附接表面內之窄互連墊之基板的倒裝晶片封裝，其中凸塊配合於窄墊上。
有些實施例中，窄墊上凸塊之互連根據本發明之方法而不使用在製程中之再熔化階段限制熔化焊料之阻焊層而形成。阻焊層需要之避免容許更精密之互連幾何形狀。
有些實施例中，使基板在窄互連墊上方進一步提供具有開孔的阻焊層。有些實施例中，使基板在窄互連墊上進一步提供焊錫膏。
另一普通態樣中，本發明特別描述形成倒裝晶片互連的方法，其係藉由提供具有形成於晶粒附接表面中之窄互連墊的基板以及具有附接至主動表面內之互連墊之凸塊的晶粒；支撐基板及晶粒；在基板(至少覆蓋窄互連墊)上或在晶粒之主動側(至少覆蓋凸塊)上分佈一定量之可固化黏合劑；以晶粒之主動側面向基板之晶粒附接表面來定位晶粒且對準晶粒與基板並將一者向另一者移動以便凸塊接觸基板上之對應窄互連墊；施加足以使來自凸塊與配合窄帶之間之黏合劑移位之力以將凸塊壓在配合窄墊上；至少部分固化黏合劑；熔化且接著再凝固焊料，在凸塊與窄墊之間形成金相互連。
另一普通態樣中，本發明特別描述形成倒裝晶片互連的方法，其係藉由提供具有形成於晶粒附接表面中之窄互連墊及具有在窄墊上方具有開孔之阻焊層的基板，以及具有附接至主動表面內之互連墊之凸塊的晶粒；支撐基板及晶粒；以晶粒之主動側面向基板之晶粒附接表面來定位晶粒且對準晶粒與基板並將一者向另一者移動以便凸塊接觸基板上之對應窄墊；熔化且接著再凝固以在凸塊與窄墊之間形成互連。
有些實施例中，焊料凸塊包括可軟化焊料部分，且熔化及凝固步驟熔化凸塊以在窄墊上形成互連。有些實施例中，使基板提供焊錫膏於窄墊上，且使晶粒與基板相向移動之步驟實現窄墊上凸塊與焊料之間的接觸，且熔化及凝固步驟熔化窄墊上的焊料以形成互連。
另一普通態樣中，本發明特別描述形成倒裝晶片互連的方法，其係藉由提供具有形成於晶粒附接表面中之窄互連墊及具有在窄墊上方具有開孔之阻焊層及具有窄墊上之焊錫膏的基板，以及具有附接至主動表面內之互連墊之凸塊的晶粒；支撐基板及晶粒；以晶粒之主動側面向基板之晶粒附接表面來定位晶粒且對準晶粒與基板並將一者向另一者移動以便凸塊接觸基板上之對應窄互連墊上之焊錫膏；熔化且接著再凝固焊錫膏，在凸塊與窄墊之間形成金相互連。
本發明現參考圖式進一步詳細描述，該等圖式說明本發明之替代實施例。該等圖式示意性地展示了本發明之特徵以及彼等與其他特徵及結構的關係，且不按比例繪製。在說明本發明之實施例的圖式中，為改良圖示清晰度，與其他圖式所示之元件對應之元件未全部加以特定再編號，儘管所有圖式中彼等皆易於識別。
藉由使用熔化製程以將凸塊(通常為焊料凸塊)接合在對應抓取墊之配合表面上來獲得習知倒裝晶片互連，因此，已知此為"抓取墊上凸塊"("BOC")式互連。顯然BOC設計中有兩個特徵：第一，需要較大抓取墊以與晶粒上凸塊配合；第二，需要絕緣材料(通常已知為"阻焊層")以在互連製程期間限制焊料流動。阻焊層開孔可限定抓取墊上之熔融焊料之輪廓("阻焊層限定")，或焊料輪廓可不藉由阻焊層開孔限定("非阻焊層限定")，在後者狀況中(如圖1之實例中，下文更詳細描述)，阻焊層開孔可明顯大於抓取墊。阻焊層開孔限定技術具有寬的容許範圍。因此，對於阻焊層限定凸塊構造，抓取墊必須大(通常比阻焊層開孔設計尺寸大很多)以確保阻焊層開孔位於墊之配合表面上；且對於非阻焊層限定凸塊構造，阻焊層開孔必須大於抓取墊。抓取墊寬度(或直徑(對於圓形墊))通常與焊球(或凸塊)直徑大約相同，且可差不多有跡線寬度之2至4倍寬。此導致上基板層上布線空間之大量損失。特定而言，例如，"跳出布線間距"比基板技術所能提供之最細跡線間距大不少。此意謂大量襯墊必須藉助於嵌柱與通孔(自待討論中之襯墊發散出)排列於下基板層(通常在晶粒覆蓋區以下)上。
圖1與圖2以示意性剖視圖展示習知倒裝晶片封裝之部分10、20；圖1中局部剖視圖以平行於封裝基板表面之平面、沿圖2中之直線1－1'剖視而繪製；且圖2中局部剖視圖以垂直於封裝基板表面之平面、沿圖1中之直線2－2'剖視而繪製。某些特徵經展示如同透明一般，但所展示之圖1中很多特徵至少部分地被覆蓋特徵所遮蔽。現參考圖1與圖2，封裝基板之晶粒附接表面包括形成於介電層12上的金屬層。金屬層經圖案化以形成引線13及抓取墊14。絕緣層16(通常稱為"阻焊層")覆蓋基板之晶粒附接表面；阻焊層通常由可光定義材料建構，且藉由習知光阻圖案化技術加以圖案化以遺留所曝露之抓取墊14之配合表面。附接至晶粒18之主動側上之襯墊之互連凸塊15與基板上對應抓取墊14之配合表面接合以在晶粒上之電路與基板上之引線之間形成適當電互連。使回焊之焊料冷卻而建立電連接後，在晶粒18與基板12之間的空間內導入底填材料17，機械地穩定互連且保護晶粒與基板之間的特徵。
如圖1藉由實例展示，基板之上金屬層中之訊號跳出跡線(引線13)橫穿晶粒邊緣位置(如虛線11所示)自彼等各自的抓取墊14引出且離開晶粒覆蓋區。典型實例中，訊號跡線可具有約112 μm之跳出間距PE 。如圖1所示之構造中，對於跡線本身的設計規則通常為30 μm/30 μm；意即，跡線標稱上為30 μm寬，且彼等緊密集攏起來之間距可為30 μm。抓取墊通常比跡線寬度大2倍，因此，該實例中抓取墊在標稱上具有90 μm寬度(或直徑，因為該實例中彼等大約為圓形)。且該實例中，阻焊層中具有135 μm標稱寬度(直徑)之開孔比襯墊大。
圖1與圖2展示非阻焊層限定之焊料輪廓。當晶粒上凸塊之可熔材料熔化時，熔融焊料傾向於"濕潤"引線與抓取墊之金屬，且焊料傾向於越過未遮蔽之任何鄰近金屬表面"流出"。焊料傾向於沿鄰近引線13流動，且此處焊料流動受阻焊層限制，例如在圖1中19處。襯墊處非阻焊層限定之焊料輪廓在圖2中很明顯，其中凸塊15之材料展示為越過抓取墊14之側面流動29且向下流至基板12之介電層之表面。此稱為非阻焊層限定輪廓，因為焊料流過表面且越過抓取墊之側面流下不受阻焊層限制，且(除非襯墊處存在大體過量的焊料)焊料流動受到基板之介電表面通常可不被熔融焊料濕潤之實情所限制。如圖1中，抓取墊習知排列密度之下限由對於用以形成可靠窄阻焊結構之阻焊形成技術能力之限制以及在阻焊層鄰近開孔之間提供阻焊結構之需要且結合其他因素來判定。跳線密度之下限另外由跳出線路自更靠中心定位之抓取墊而布線至更靠外圍定位之抓取墊之間之需要且結合其他因素判定。
圖3以與圖2中相似之剖視圖展示習知阻焊層限定焊料輪廓30。經展示，晶粒38藉由凸塊35黏著在藉由對基板32之介電層之晶粒附接側上之金屬層圖案化而與跡線(引線33)一起所形成之抓取墊34之配合表面上。使回焊之焊料冷卻而建立電連接後，將底填材料37導入晶粒38與基板32之間的空間內，機械地穩定互連且保護晶粒與基板之間的特徵。此處，抓取墊34比圖1與圖2之實例更寬，且阻焊層開孔比抓取墊更小，以便阻焊層材料覆蓋每個抓取墊之配合表面之側面與局部(如39處所示)以及引線33。當使凸塊35與各自抓取墊34之配合表面接觸且接著熔化時，阻焊層材料36限制熔融焊料之流動，因此焊料輪廓之形狀由抓取墊34上之阻焊層開孔之形狀與尺寸限定。習知阻焊層限定之抓取墊上凸塊式互連之典型實例中，抓取墊具有約140 μm之直徑，且阻焊層開孔具有約90 μm之直徑，且布線跡線為約25－30 μm寬。該實例中，凸塊附接至晶粒墊(圖2或圖3中未示)之配合表面之直徑，意即凸塊與晶粒墊之間介面之位置，由阻焊層開孔限定為具有約90 μm之直徑。
圖4與圖6分別沿圖5與圖7中直線4－4'與6－6'以平行於基板表面之平面所取得之局部剖視示意圖分別展示本發明之一實施例之窄墊上凸塊式("BONP")倒裝晶片互連之部分40。某些特徵經展示如同透明一般。本發明之互連藉由使凸塊配合在基板上各自的窄互連墊上而達成，因此本文中此稱為"窄墊上凸塊"("BONP")式互連。阻焊層材料在該等細密幾何形狀下通常無法融化，且根據本發明之該等實施例，不使用阻焊層。實情為，在裝配製程之過程中(如下所述)，無阻焊層而完成限制熔融焊料流動之功能。圖5沿圖4中直線5－5'以垂直於封裝基板表面平面之平面展示如圖4中之封裝之局部剖視圖；且圖7沿圖6中直線7－7'以垂直於封裝基板表面平面之平面展示如圖6中之封裝之局部剖視圖。
用於本發明之窄墊上凸塊式("BONP")基板之跳出布線圖案藉由圖4與圖6之實例展示：圖4中，一晶粒上之互連球之晶粒附接墊排成一列而接近晶粒周界，為該晶粒所配置之凸塊45配合至跳出跡線43上之靠近晶粒覆蓋區之邊緣(如虛線41所示)之一列對應窄互連墊上；圖6中，一晶粒上之晶粒附接墊處於靠近晶粒周界之平行列之陣列中，為該晶粒所配置之凸塊65配合至跳出跡線63上之靠近晶粒覆蓋區之邊緣(如虛線61所示)之一互補陣列之對應窄互連墊上。
如圖4與圖6說明，使用本發明之窄墊上凸塊式互連可達到之布線密度可等於藉由基板技術所提供之最細跡線間距。所說明之特定狀況中，此形成比在習知抓取墊上凸塊式配置中所達到之布線密度大約高90%的布線密度。在BONP之周界列實施例(例如圖4)中，凸塊以微細間距放置，其可等於基板之最細跡線間距。此配置為裝配製程提出了挑戰，因為凸塊間距與接合間距必須非常微細。BONP之周界陣列型式(例如圖6)中，凸塊以區域陣列排列，為較大凸塊間距與接合間距提供更大空間，且緩解了對裝配製程之技術挑戰。即使在陣列實施例中，基板上布線跡線的有效間距與周界列排列中相同，且如圖6中之排列減輕了細間距凸塊與接合之負擔而保持跳出布線細間距的優勢。
現特別參考圖4與圖5，引線43與窄互連墊46由對基板介電層42之晶粒附接表面上之金屬層圖案化而形成。窄墊46作為互連部位處跡線43之加寬而形成。互連墊之"寬度"(圖5中為Wp )為橫越互連部位處跡線之加寬部分之標稱或設計尺寸。根據本發明，基板上窄互連墊之寬度根據連接至基板之晶粒上凸塊之凸塊基底寬度("基底直徑")確定。"凸塊基底寬度"(圖5中Wb )為凸塊45與晶粒墊49之間之大體圓(近似圓形)接觸介面之標稱或設計直徑。(如所能瞭解，例如，以平行於凸塊-墊介面之平面所取得之凸塊直徑可能大於凸塊基底寬度，如圖2、3、5及7中示意說明)。特別根據本發明，互連墊之寬度Wp 小於凸塊基底寬度Wb ，且窄互連墊寬度可小達凸塊基底寬度之20%。很多實施例中，窄墊寬度在凸塊基底寬度約20%至約80%之範圍內。有些實施例中，窄互連墊寬度小於凸塊基底寬度且大於約凸塊基底寬度之25%。有些實施例中，窄墊寬度小於約凸塊基底寬度之60%。
根據本發明，藉由使晶粒上之凸塊45接合在引線43上之窄互連墊46上，而形成晶粒48之電互連。根據本發明，習知較寬抓取墊為不必要的，且在如圖4與圖5之實施例中，不需要阻焊層；以下詳細描述該方法。
習知抓取墊的寬度(直徑)通常與凸塊大約相同，且通常為跡線或引線寬度之兩倍至四倍寬。如將瞭解，引線寬度中預期有些變化。如本文中所使用，窄互連墊具有標稱或跡線設計規則寬度之至少約120%之標稱或設計寬度，且本發明之窄引線上凸塊式互連包括連接至大於標稱或跡線設計規則寬度之約120%且小於凸塊基底直徑之跡線之加 寬部分的凸塊。具有小於約120%之寬度之互連部位不構成窄互連墊，且由使凸塊連接在小於標稱或跡線設計規則寬度之約120%之引線之部分上所形成之互連稱為"引線上凸塊"式互連。
類似地，參考圖6與圖7，引線63及窄互連墊66藉由圖案化基板介電層62之晶粒附接表面上之金屬層而形成。訊號跳出跡線橫越晶粒邊緣位置(虛線61所示)引出，且離開晶粒覆蓋區。窄墊66作為互連部位處跡線63之加寬而形成。互連墊之"寬度"(圖7中Wp )為橫越互連部位處跡線之加寬部分之標稱或設計尺寸。該實例中，如圖4與圖5所示之實例中，根據本發明，基板上窄互連墊之寬度根據連接至基板之晶粒上凸塊之凸塊基底寬度確定。"凸塊基底寬度"(圖7中Wb )為凸塊65與晶粒墊69之間大體圓(近似圓形)接觸介面之標稱或設計直徑。特別根據本發明，互連墊寬度Wp 小於凸塊基底寬度Wb ，且窄互連墊寬度可小達凸塊基底寬度之20%。很多實施例中窄墊寬度在凸塊基底寬度約20%至約80%之範圍內。有些實施例中，窄互連墊寬度小於凸塊基底寬度且大於凸塊基底寬度之約25%。有些實施例中，窄墊寬度小於凸塊基底寬度之約60%。
根據本發明，晶粒68之電互連藉由使晶粒窄互連墊66上之凸塊65接合在引線63上而形成。自接近晶粒覆蓋區之內部的成排互連部位處橫越晶粒邊緣位置引出之某些跳出跡線(例如66)，在互連部位之靠外圍各排上之凸塊65之間通過。根據本發明不需要抓取墊，且在如圖6與圖7中之實施例中，不需要阻焊層；以下詳述該方法。
根據本發明，隨著形成跡線之技術改良，可以可靠地形成具有小於約25 μm之標稱或設計規則寬度的跡線。減小之跡線寬度可為增大布線密度創造條件。然而，小於約25 μm之引線上之"引線上凸塊式"倒裝晶片互連的機械可靠性可能不令人滿意，因為凸塊與引線之間之介面之尺寸較小，且不可提供足以提供良好電互連之接合強度。本發明藉由加寬引線至尺寸上與凸塊基底寬度相關且受限小於凸塊基底寬度的程度而形成窄互連墊，從而提供可靠機械連接(及良好電互連)。
本發明之窄互連墊可以各種方式中任一種成形。有些該等形狀可更易於製造，且有些可提供其他製程優點。舉例而言，窄墊可為大體矩形，方形141或拉長形143，如圖14A與圖14B中實例所示；或者，其為大體圓形，圓形146或橢圓形147，如圖14C與圖14D中實例所示。其他形狀可使用，一特別有用的形狀149藉由圖14E中實例展示，其半圓形部分藉由一方形或矩形部分而沿引線或跡線142之長度方向分開。又，窄墊可形成為引線或跡線152加寬之對稱形151或非對稱形153，如圖15A與15B所示(展示如實例之大體矩形墊)。又，窄墊不必位於或靠近引線或跡線之末端，但可形成於互連指定處的任意點，如圖15C所說明(展示如實例之大體矩形墊155)。形成長大於寬之墊增加了窄墊之可濕潤配合表面(平坦表面加上側面之曝露部分)，且可改良互連之機械強度。又，若墊長大於寬，則阻焊層開孔(或凸塊)之未對準之容限增加，特別是墊在跡線末端之處，拉長墊可降低阻焊層開孔(或凸塊)脫離墊之末端之可能性。
藉由圖4、6、8及9中之實例所示之阻焊層開孔為大體圓形(圓形或橢圓形)，但根據本發明，阻焊層開孔可以各種方式中任一種成形。有用的為例如提供大體矩形之阻焊層開孔，方形161或拉長形163，如圖16A、16B所示(展示如實例之大體矩形墊164)。給定寬度之方形或矩形之面積大於具有相同寬度(直徑，短軸)之圓或橢圓之面積。鑒於此原因，方形或矩形阻焊層開孔具有固持大量焊錫膏(或其他可熔材料)之容量，從而此可提供諸如焊錫膏之可熔材料在與凸塊配合之前塗佈至窄墊上之配合表面(下文詳述)。又，將可熔材料印入方形或矩形阻焊層開孔較印入圓形或橢圓形阻焊層開孔更容易，因為在印花製程中存在較大的未對準容限。又，若規定阻焊層開孔之寬度限度，則方形或矩形阻焊層開孔為互連製程期間將大凸塊安裝在襯墊上提供更大的開放區域。
藉由與阻焊層176中圓形阻焊層開孔174相關之實例，本發明之實施例之各種窄墊構造展示於圖17中。各實例中阻焊層開孔具有可為例如約90 μm之寬度(直徑)Wm。173處展示引線上凸塊式構造。引線或跡線172具有可為例如約30 μm之標稱(設計)寬度WL 。175處展示具有矩形之窄墊。該實例中在形成窄墊處之引線或跡線具有可為例如約30 μm之標稱(設計)寬度WL '。矩形窄墊具有可為例如約45 μm之寬度WP '。177處展示在更寬引線或跡線所形成之具有卵形、具有可為例如約50 μm之標稱(設計)寬度WL "之窄墊。179處展示具有矩形之窄墊，該矩形經膨脹具有一卵形。該實例中，形成窄墊處之更窄引線或跡線具有可為例如約30 μm之標稱(設計)寬度WL '''。窄墊179之矩形部分具有可為例如約45 μm之寬度WP "；且該卵形膨脹部分具有可為約50 μm之寬度WP E 。
圖18中，藉由與引線(或跡線)或窄墊182相關之實例展示本發明之實施例之各種阻焊層186開孔構造。該等實例中，互連部位處之引線或窄墊具有可為例如約40 μm之寬度WL 。一第一實例中，具有可為例如約90 μm之寬度(直徑)Wm之圓形阻焊層開孔185暴露互連部位部分183。一第二實例中，具有可為例如約80 μm之寬度(橫越引線或窄墊)Wm'以及可為例如約120 μm之長度Lm'之矩形阻焊層開孔187，暴露互連部位部分183'。一第三實例中，具有可為例如約80 μm之寬度(橫越引線或窄墊)Wm"以及可為例如約120 μm之長度Lm"之橢圓形阻焊層開孔189，暴露互連部位部分183"。與圓形阻焊層開孔185相比，在183"、183"部位處之矩形開孔187與卵形開孔189暴露引線或襯墊之更大長度(從而更大面積)，即使該實例中圓形開孔具有更大的直徑亦如此。此為互連製程期間焊料回焊提供了更大的範圍且可導致更強勁的互連。矩形開孔187所暴露的面積稍大於具有相同寬度與長度之橢圓形開孔189所提供的面積；且此外，若橢圓形開孔稍未對準，則面積減小，但矩形開孔稍未對準則不會。然而，實務上，由於在阻焊層電介質中圖案化開孔之過程中之解析度限制，因此設計矩形開孔會具有或多或少的圓角。
本發明之有些說明性實例中，待安裝之晶粒上之凸塊基底直徑可為約90 μm，且在基板上形成寬度在約25 μm(此處跡線寬度小於約25 μm)至約50 μm之範圍內之窄互連墊。與具有更大直徑之習知抓取墊(通常可為跡線寬度之2倍至4倍寬)之基板相比，此提供布線密度之大幅改良。
如圖4與圖6所示，本發明之窄墊上凸塊式互連可提供顯著更高的訊號跡線跳出布線密度。又，如圖4與圖6所示，本發明之此態樣之BONP互連無需使用阻焊層以限定互連部位處之焊料輪廓。
無需阻焊層，諸如藉由圖4、5、6及7中實例所展示之實施例之BONP互連結構可根據本發明藉由幾種方法中任一種方法製造。大體而言，使互連凸塊(通常為焊料凸塊)黏附在晶粒之主動側之互連墊上。基板之晶粒附接表面(稱為"上"表面)具有經圖案化之上金屬層，以在互連部位處提供跡線與窄墊以便與特定晶粒上排列之凸塊互連。本發明之一較佳方法中，使用包封樹脂黏合劑47、67以在互連製程之熔化狀態期間限制焊料流動。
圖8與圖9以平行於基板表面之平面所取得之示意性剖視圖展示本發明之其他實施例之窄墊上凸塊式倒裝晶片互連之一部分的兩個實例。某些特徵經展示如同透明一般。根據本發明之此態樣，提供可具有在約80 μm至90 μm範圍內之標稱阻焊層開孔直徑之阻焊層。阻焊層材料可在該等間距處熔解，且特定而言，可相對低費用地製得基板，其所具有之阻焊層具有90 μm開孔及具有±25 μm之對準容限。有些實施例中，使用根據標準設計規則製得的層疊基板(諸如4層金屬層疊物)。圖8與圖9之實施例中，例如，跡線間距可為~90 μm且窄墊可在270 μm區域陣列中，提供了~90 μm橫越晶粒覆蓋區之邊緣(如虛線81、91所示)的有效跳出間距。
如圖8與圖9之實施例中，無需非流動性底填；可使用習知毛細管底填。
如圖8之實施例中，藉由使凸塊直接配合在窄引線或跡線83上之窄互連墊84上達成互連，引線或跡線圖案化於基板82之晶粒附接表面上之介電層上；阻焊層86用於將焊料流動限制在阻焊層開孔88之範圍內，防止焊料沿可經焊料濕潤之引線流出互連部位。此外，阻焊層可將熔融焊料之流動限制在引線之間，或此可在裝配製程過程中完成。
如圖9之實施例中、如同圖8，跡線93上窄墊圖案化於基板92之晶粒附接表面上之介電層上。焊錫膏提供於引線93上之互連部位處(窄墊)94，以提供用於互連之可熔媒質。阻焊層96中之開孔98用於限定焊錫膏。焊錫膏藉由例如標準印刷過程分佈，接著回焊，且接著(若需要)可鑄成型以提供均勻表面以接觸焊球。使用如以上參考圖8所述之基板，可在裝配過程中塗施焊錫膏；或者，可向基板提供經適當圖案化的焊錫膏再裝配。本發明之窄墊上焊料式實施例中，可使用選擇性塗施焊料至互連部位處的其他方法，包括無電極電鍍及電鍍技術。窄墊上焊料式構造為互連提供了額外的焊料容量，且因此可提供更高的產品產量，且亦可提供更高的晶粒間隙。
因此，有些實施例中，使用本發明之窄墊上焊料式構造用於將具有高熔融溫度焊料凸塊(諸如高鉛[高Pb]焊料，通常用於與陶瓷基板之互連)之晶粒互連至有機基板上。可選擇具有足夠低之熔融溫度的焊錫膏，以便在回焊期間不損傷有機基板。為形成該等實施例中的互連，使高熔融互連凸塊與窄墊上焊料部位接觸，且再熔化使窄墊上焊料熔合至凸塊。若使用非可軟化凸塊以及窄墊上焊料製程，則無需預先塗佈的黏合劑，因為焊料移位或流動受到在每一互連處僅存在少量焊料之實情之限制，且非可軟化凸塊防止裝配之瓦解。
其他實施例中，本發明之窄墊上焊料式構造用於具有共熔焊料凸塊之晶粒之互連。
圖10A－10C中示意性展示用於製造窄墊上凸塊式互連之一較佳方法之一實施例。
參考圖式，提供具有至少一個介電層且在晶粒附接表面113上具有金屬層之基板112，金屬層經圖案化以在晶粒附接表面上提供電路，尤其跡線或引線136上之窄互連墊114。基板112支撐於例如載台或平臺116上，與晶粒附接表面113反向之基板表面111面向支撐台。一定量之包封樹脂122分佈在基板之晶粒附接表面113上，至少覆蓋引線上之窄互連墊114。提供具有與主動側103上之晶粒墊(圖中未示)附接之凸塊104之晶粒102。凸塊包括接觸窄墊之配合表面之可熔材料。包括卡盤106之拾放工具108藉由使卡盤106與晶粒之背側101接觸而拾起晶粒。使用拾放工具，以晶粒之主動側朝向基板之晶粒附接表面使晶粒面向基板定位，如圖10A所示；且將晶粒與基板對準並使一者向另一者移動(箭頭M)以便凸塊104接觸基板上之跡線(引線)上之對應窄互連墊114。接著施加一力(箭頭F)以將凸塊105壓在引線上窄墊115之配合表面134上，如圖10B所示。該力必須至少足以使黏合劑122自凸塊與窄互連墊115之配合表面134之間移位。該力可使凸塊變形，破壞凸塊之接觸表面上及/或窄墊之配合表面上的氧化物膜。凸塊之變形可導致凸塊之可熔材料被壓在窄墊之頂部及邊緣上。如132處所示，如(例如)藉由加熱至一選定溫度使黏合劑至少部分固化。在此階段，黏合劑僅需部分固化，意即僅固化至足以隨後防止熔融焊料沿黏合劑與導電跡線之間之介面流動之程度。接著，使凸塊105之可熔材料熔融並接著再凝固，在凸塊105與窄墊115之間形成金相互連，且完成黏合劑固化，以完成晶粒安裝並緊固配合表面(現為互連介面)144處之電互連，如圖10C中在140處大體所展示。在圖10C所示剖視圖之平面中，互連在某些凸塊l45與某些引線上之對應窄互連墊155之間形成，如(例如)圖6之構造中之實例。其他引線156在其他位置之窄互連墊上互連，此在其他剖視圖中為明顯的。所展示為比較高的跡線密度。黏合劑之固化可在熔融焊料之前或同時或之後完成。通常，黏合劑為可熱固化黏合劑，且藉由調節溫度控制該方法中任意階段之固化程度。該等組件例如可藉由提高拾放工具上卡盤之溫度或藉由提高基板支撐台之溫度加熱且固化。
圖11A－11D進一步詳細展示了該方法。圖11A中，在基板212之晶粒附接表面上供有導電(金屬)跡線，且跡線上之互連部位處窄互連墊214覆蓋有黏合劑222。晶粒202相對於基板212而定位，使得晶粒之主動側面向基板之晶粒附接側，且對準晶粒(箭頭A)使得晶粒上之凸塊204與窄墊214上之對應配合表面對齊。使晶粒與基板彼此相向移動以便凸塊與窄墊上各自的配合表面接觸。接著，如圖11B所示，施加力以使凸塊205與窄墊215彼此相抵移動，如圖11B中232處所示使黏合劑移位，且使窄墊之配合表面234上及邊緣上之凸塊變形。窄墊上之凸塊變形破壞了凸塊之接觸表面及窄墊之配合表面上之氧化物膜，建立良好的電連接，且窄墊邊緣上之凸塊變形有助於建立良好的暫時性機械連接。如圖10A－10C之實例中，某些跡線216之窄互連墊不在圖11B之平面範圍內。加熱以部分固化黏合劑，如圖11C中236處所示。接著加熱以將凸塊之溫度升高至足以引起凸塊之可熔材料熔融，如圖11D所示。此大體(儘管不必完全)完成黏合劑246之固化且完成窄互連墊215之配合表面244上之凸塊245之金相互連。經固化之黏合劑穩定了晶粒安裝。
較佳方法之一替代性實施例中，除基板外，黏合劑可預先塗施至晶粒表面，或至少塗施至晶粒表面上之凸塊。黏合劑可例如彙集於儲槽，且晶粒之主動側可浸漬於儲槽並移除，以便凸塊上攜帶一定量的黏合劑；接著，使用拾放工具，以晶粒之主動側朝向基板之晶粒附接表面使晶粒面向經支撐之基板而定位，且使晶粒與基板對準並使一者移向另一者以便凸塊接觸基板上之對應跡線(引線)。該方法描述於美國專利第6,780,682號(2004年8月24日)中，該專利以引用方式併入本文中。接著如以上所述，執行施力、固化並熔融。
藉由圖12中之實例示意性展示用於本發明之方法之力與溫度的時間表。此圖中，時間在水平軸上自左向右延續；力分佈310展示為厚實線，且溫度分佈320展示為點化線。溫度分佈起始於約80℃－90℃範圍內之一溫度。力分佈起始於大體為零之力。自起始時間ti 開始，力自Fi 快速(幾乎瞬間)上升312至移位/變形力Fd 且在彼力保持314達一定時間，如以下所論述。Fd 為大至足以將黏合劑自凸塊與窄互連墊之配合表面之間移離之力；且較佳地，Fd 足以使配合表面上之凸塊之可熔(窄墊接觸)部分變形，破壞氧化物膜並形成良好的金屬至金屬(金相)接觸，且有些實施例中，在窄墊之邊緣上破壞氧化物膜並形成良好的金屬至金屬(金相)接觸以建立凸塊與窄墊之機械互鎖("潛變"變形)。所需要力之總量視凸塊材料及尺寸以及視凸塊數目而定，且可經適當實驗而判定。當力上升時，溫度亦自起始溫度Ti 快速上升322至凝膠溫度Tg 。凝膠溫度Tg 為足以部分固化黏合劑(至"凝膠")的溫度。較佳地，設定力與溫度斜坡應使得繼達到Fd 之瞬間之後且在達到Tg 之前存在一短滯後時間td e f ，該時間至少足夠長以容許升高的力在黏合劑之部分固化開始前移位黏合劑並使凸塊變形。在移位/變形壓力Fd 及在凝膠溫度Tg 下將總成保持314、324足以實現黏合劑之部分固化的溫度t凝 膠 。黏合劑應足夠牢固以便其在焊料再熔階段期間能維持良好凸塊外形，意即足夠牢固以防止凸塊之熔融可熔材料之非所需的移位，或防止熔融可溶材料沿窄墊及引線流動。一旦黏合劑部分固化至足夠程度，壓力會快速斜坡下降318至力大體消失(組件之重量)。接著溫度進一步快速上升323至足以再熔凸塊之可熔部分(焊料)的溫度Tm ，且總成在再熔溫度Tm 下保持325至少足以完全形成再熔焊料於窄墊上且較佳足以大體(儘管不必完全)固化黏合劑之時間t熔 融 / 固 化 。接著，溫度斜坡下降328至起始溫度Ti ，且最後降至環境溫度。圖12所描述方法之運行過程可經歷5－10秒時間。
如圖12之實施例中之黏合劑可稱為"非流動底填"。倒裝晶片互連之有些方法中，金相互連首先形成，且接著底填材料流入晶粒與基板之間的空間內。本發明之"非流動底填"在晶粒與基板合起來之前應用，且由於凸塊移近至窄墊上以及由於晶粒與基板之表面抵靠而導致移置非流動底填。用於本發明之非流動底填黏合劑之黏合劑較佳為快速凝膠黏合劑，意即在凝膠溫度下以約1－2秒之時間充分凝膠的材料。用於非流動底填黏合劑之較佳材料包括例如所謂的非導電性焊錫膏，諸如Toshiba Chemicals及Loktite－Henkel所售之彼等物。
替代性凸塊結構可用於本發明之窄墊上凸塊式互連中。特定而言，例如，可使用所謂的複合焊料凸塊。複合焊料凸塊具有至少兩個由不同凸塊材料形成的凸塊部分，包括一在再熔條件下可軟化之部分，及一在再熔條件下大體非可軟化之部分。非軟化部分附接至晶粒上之互連部位；用於非可軟化部分之典型習知材料包括具有例如高鉛(Pb)含量之各種焊料，以及例如金(Au)。可軟化部分接合至非可軟化部分，且形成與本發明之窄互連墊之連接者為可軟化部分。用於複合凸塊之可軟化部分之典型習知材料包括共熔焊料(例如)。
圖13以示意性剖視圖展示使用複合凸塊之窄墊上凸塊式互連之實例。現參考圖13，在晶粒302之主動側中之晶粒墊上提供包括非可軟化部分345與可軟化部分347之複合凸塊。可軟化部分可為例如共熔焊料或相對低溫熔融焊料。可軟化部分接觸窄墊355之配合表面344，且若需要窄墊上凸塊之可熔部分之變形，則凸塊之可軟化部分在所用力之條件下可變形。非可軟化部分可為例如具有高鉛(Pb)含量之焊料。處理期間當晶粒受壓移動抵靠基板時非可軟化部分不變形，且可軟化部分在該方法之再熔階段期間不熔融。因此，可形成非可軟化部分所需尺寸以提供晶粒之主動表面與基板之晶粒附接表面之間的間隙距離。
如可瞭解，如(例如)圖4、5、6及7所示實施例中之凸塊不必為完全可軟化凸塊。可替代性使用複合凸塊或使用窄墊上焊料式方法中非可軟化凸塊(高Pb或Au)製造該等圖中所展示之結構，如以上所述。
此外，如自上文可瞭解，如(例如)圖13出現之互連可藉由使非複合式非可軟化凸塊(高Pb，Au)與在配合表面上提供有可熔材料(諸如可作為焊錫膏提供的共熔焊料或相對低溫熔融焊料)之窄互連墊接觸而形成。或者，窄互連墊可具有配合表面上之可熔材料且凸塊可為複合凸塊，其亦具有可軟化(可熔)部分。若窄互連墊具有配合表面上之可熔材料，則該製程中使用阻焊層、繼之使用毛細管底填可為較佳。
其他實施例涵蓋於以下申請專利範圍中。
10．．．習知倒裝晶片封裝之部分
11．．．虛線
12．．．介電層
13．．．引線
14．．．抓取墊
15．．．互連凸塊
16．．．絕緣層/阻焊層
17．．．底填材料
18．．．晶粒
19．．．焊料流動受阻焊層限制之處
20．．．習知倒裝晶片封裝之部分
29．．．流動
30．．．習知阻焊層限定焊料輪廓
32．．．基板
33．．．引線
34．．．抓取墊
35．．．凸塊
36．．．阻焊層材料
37．．．底填材料
38．．．晶粒
39．．．阻焊層材料覆蓋每個抓取墊之配合表面之側面與局部
40．．．窄墊上凸塊式倒裝晶片互連之部分
41．．．虛線
42．．．介電層
43．．．跡線
45．．．凸塊
46．．．窄互連墊
47．．．包封樹脂黏合劑
48．．．晶粒
49．．．晶粒墊
61．．．虛線
62．．．窄墊
63．．．跡線
65．．．凸塊
66．．．窄墊
67．．．包封樹脂黏合劑
68．．．晶粒
69．．．晶粒墊
81．．．虛線
82．．．基板
83．．．窄引線或跡線
84．．．窄互連墊
86．．．阻焊層
88．．．阻焊層開孔
91．．．虛線
92．．．基板
93．．．引線
94．．．互連部位處(窄墊)
96．．．阻焊層
98．．．開孔
101．．．晶粒之背側
102．．．晶粒
103．．．主動側
104．．．凸塊
105．．．凸塊
106．．．卡盤
108．．．拾放工具
111．．．基板表面
112．．．基板
113．．．晶粒附接表面
114．．．窄互連墊
115．．．窄墊
116．．．載台或平臺
132．．．黏合劑至少部分固化之處
134．．．配合表面
136．．．跡線或引線
141．．．方形
142．．．引線或跡線
143．．．拉長形
144．．．配合表面(互連介面)
145．．．凸塊
146．．．圓形
147．．．橢圓形
149．．．特別有用的形狀
151．．．對稱形
152．．．引線或跡線
153．．．非對稱形
155．．．對應窄互連墊
156．．．引線
161．．．方形
163．．．拉長形
164．．．大體矩形墊
202．．．晶粒
204．．．凸塊
205．．．凸塊
212．．．基板
214．．．窄墊
215．．．窄墊
216．．．跡線
222．．．黏合劑
232．．．使黏合劑移位之處
234．．．窄墊之配合表面
236．．．加熱以部分固化黏合劑之處
244．．．窄互連墊之配合表面
245．．．凸塊
246．．．黏合劑
302．．．晶粒
310．．．力分佈
312．．．快速上升
314．．．保持
318．．．快速下降
320．．．溫度分佈
323．．．快速上升
324．．．保持
325．．．保持
328．．．溫度斜坡下降
344．．．窄墊之配合表面
345．．．非可軟化部分
347．．．可軟化部分
355．．．窄墊
圖1為以平行於封裝基板表面平面之剖視(如圖2中箭頭1－1'所示)展示習知抓取墊上凸塊式倒裝晶片互連之一部分之示意圖；圖2為以垂直於封裝基板表面平面之剖視(如圖1中箭頭2－2'所示)展示習知抓取墊上凸塊式倒裝晶片互連之一部分之示意圖；圖3為以垂直於封裝基板表面平面之剖視展示另一習知抓取墊上凸塊式倒裝晶片互連之一部分之示意圖；圖4為以平行於封裝基板表面平面之剖視展示本發明之一實施例之窄墊上凸塊式倒裝晶片互連之一實施例之一部分之示意圖；圖5為以垂直於封裝基板表面平面之剖視(如圖4中箭頭5－5'所示)展示如圖4中本發明之一實施例之窄墊上凸塊式倒裝晶片互連之一實施例之一部分之示意圖；圖6為以平行於封裝基板表面平面之剖視展示本發明之一實施例之窄墊上凸塊式倒裝晶片互連之另一實施例之一部分之示意圖；圖7為以垂直於封裝基板表面平面之剖視(如圖6中箭頭7－7'所示)展示如圖6中本發明之一實施例之窄墊上凸塊式倒裝晶片互連之一實施例之一部分之示意圖；圖8與圖9為以平行於封裝基板表面平面之剖視分別展示本發明之一實施例之窄墊上凸塊式倒裝晶片互連之另一實施例之一部分之示意圖；圖10A至圖10C為以剖視說明本發明之一實施例之倒裝晶片互連之製造方法中之步驟之示意圖；圖11A至圖11D為以剖視說明本發明之一實施例之倒裝晶片互連之製造方法中之步驟之示意圖；圖12為展示用於本發明之一實施例之倒裝晶片互連之製造方法之力與溫度之時間表之示意圖；圖13為剖視展示本發明之一實施例之窄墊上凸塊式倒裝晶片互連之示意圖；圖14A至圖14E為說明本發明之實施例之各種互連墊形狀之平面示意圖；圖15A至圖15C為說明本發明之實施例之各種互連墊構造之平面示意圖；圖16A與圖16B為說明本發明之實施例之阻焊層開孔之平面示意圖；圖17為詳細說明本發明之實施例之與阻焊層開孔相關之各種互連墊構造之平面示意圖；及圖18為詳細說明本發明之實施例之與互連墊相關之各種阻焊層構造之平面示意圖。
81．．．虛線
82．．．基板
83．．．窄引線或跡線
84．．．窄互連墊
86．．．阻焊層
88．．．阻焊層開孔

Claims (15)

  1. 一種製造一半導體元件之方法，其包含：於一半導體晶粒之一表面上形成複數個接觸墊；於一基板之一表面上形成複數個導電跡線，該等導電跡線包含一互連部位；及於該等接觸墊與該等互連部位之間形成一包含可熔及不可熔部分之複合互連結構，其中該等導電跡線包含一由置放於該基板上之相鄰導電跡線間之最小間隔決定之間距，該等導電跡線包含一大於該接觸墊之一寬度之長度，且該互連部位之一寬度提供一等同於該等導電跡線之該間距之布線密度。
  2. 如請求項1之方法，其中該互連部位之該寬度介於該互連結構與該接觸墊間之一接觸介面之一寬度之20%與80%之間。
  3. 如請求項1之方法，其中該互連部位之該寬度係實質上等同於該等導電跡線之一寬度。
  4. 如請求項1之方法，其中該互連部位之該寬度為該等導電跡線之一寬度之120%。
  5. 如請求項1之方法，其中該等互連部位包含大致上矩形、拉長形或圓形。
  6. 一種製造一半導體元件之方法，其包含：於一半導體晶粒之一表面上形成複數個接觸墊；於一基板之一表面上形成複數個導電跡線，該等導電跡線包含一互連部位且包含一大於該接觸墊之一寬度之 一長度；及於該等接觸墊與該等互連部位之間形成一互連結構，其中該互連部位之一寬度係實質上等同於該等導電跡線之一寬度。
  7. 如請求項6之方法，其中該互連部位之該寬度為該等導電跡線之該寬度之120%。
  8. 如請求項6之方法，其中該等導電跡線包含一由置放於該基板上之相鄰導電跡線間之最小間隔決定之間距，且該互連部位之該寬度提供一等同於該等導電跡線之該間距之布線密度。
  9. 如請求項6之方法，其中該互連部位之該寬度介於該互連結構與該接觸墊間之一接觸介面之一寬度之20%與80%之間。
  10. 如請求項6之方法，其中該等互連部位包含大體上矩形、拉長形或圓形。
  11. 一種半導體元件，其包含：一半導體晶粒，其包含形成於該半導體晶粒之一表面上之複數個接觸墊；一基板，其包含形成於該基板之一表面上之複數個導電跡線，該等導電跡線包含一互連部位且包含一大於該接觸墊之一寬度之一長度；及一於該等接觸墊與該等互連部位之間所形成之互連結構，其中該互連部位之一寬度係實質上等同於該等導電跡線之一寬度。
  12. 如請求項11之方法，其中該互連部位之該寬度為該等導電跡線之該寬度之120%。
  13. 如請求項12之方法，其中該等導電跡線包含一由置放於該基板上之相鄰導電跡線間之最小間隔決定之間距，且該互連部位之該寬度提供一等同於該等導電跡線之該間距之布線密度。
  14. 如請求項12之方法，其中該互連結構包含一相鄰於該接觸墊之不可熔部分及一相鄰於該互連部位之可熔部分之。
  15. 如請求項11之方法，其中該互連部位包含大體上矩形、拉長形或圓形。
TW095110605A 2005-03-25 2006-03-27 具有在基板上之窄互連部位之倒裝晶片互連 TWI404114B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66520805P 2005-03-25 2005-03-25
US11/388,755 US20060216860A1 (en) 2005-03-25 2006-03-24 Flip chip interconnection having narrow interconnection sites on the substrate

Publications (2)

Publication Number Publication Date
TW200723355A TW200723355A (en) 2007-06-16
TWI404114B true TWI404114B (zh) 2013-08-01

Family

ID=37053986

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095110605A TWI404114B (zh) 2005-03-25 2006-03-27 具有在基板上之窄互連部位之倒裝晶片互連

Country Status (5)

Country Link
US (3) US20060216860A1 (zh)
JP (2) JP2008535225A (zh)
KR (1) KR20070107154A (zh)
TW (1) TWI404114B (zh)
WO (1) WO2006105015A2 (zh)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
US8026128B2 (en) * 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8674500B2 (en) * 2003-12-31 2014-03-18 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
KR101249555B1 (ko) 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
TWI232072B (en) * 2004-04-05 2005-05-01 Wistron Corp Method and structure for printed circuit board assembly and jig for assembling structure
WO2006098187A1 (ja) * 2005-03-15 2006-09-21 Matsushita Electric Industrial Co., Ltd. フリップチップ実装方法およびバンプ形成方法
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
TWI307950B (en) * 2006-08-15 2009-03-21 Advanced Semiconductor Eng Substrate structure having n-smd ball pads
US20080123335A1 (en) * 2006-11-08 2008-05-29 Jong Kun Yoo Printed circuit board assembly and display having the same
US7750250B1 (en) 2006-12-22 2010-07-06 Amkor Technology, Inc. Blind via capture pad structure
US8592989B2 (en) * 2007-02-09 2013-11-26 Stats Chippac Ltd. Integrated circuit package system with bump over via
JP4618260B2 (ja) * 2007-02-21 2011-01-26 日本テキサス・インスツルメンツ株式会社 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置
US20080246147A1 (en) * 2007-04-09 2008-10-09 Chao-Yuan Su Novel substrate design for semiconductor device
US8323771B1 (en) * 2007-08-15 2012-12-04 Amkor Technology, Inc. Straight conductor blind via capture pad structure and fabrication method
US7749887B2 (en) * 2007-12-18 2010-07-06 Micron Technology, Inc. Methods of fluxless micro-piercing of solder balls, and resulting devices
US7759137B2 (en) 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US20090250814A1 (en) * 2008-04-03 2009-10-08 Stats Chippac, Ltd. Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
EP2120262A1 (en) * 2008-05-16 2009-11-18 Phoenix Precision Technology Corporation Structure of packaging substrate and method for making the same
DK2200347T3 (da) 2008-12-22 2013-04-15 Oticon As Fremgangsmåde til drift af et høreinstrument baseret på en estimering af den aktuelle kognitive belastning af en bruger og et høreapparatsystem og tilsvarende anordning
US8659172B2 (en) 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
TWI455263B (zh) * 2009-02-16 2014-10-01 Ind Tech Res Inst 晶片封裝結構及晶片封裝方法
US8536458B1 (en) * 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
US8294276B1 (en) * 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) * 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US20120098120A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
US8970033B2 (en) * 2011-02-25 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Extending metal traces in bump-on-trace structures
US20120267779A1 (en) * 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
US8441127B2 (en) * 2011-06-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace structures with wide and narrow portions
US8643196B2 (en) * 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
KR101281341B1 (ko) * 2011-08-08 2013-07-02 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
CN102458046A (zh) * 2011-09-28 2012-05-16 柏承科技(昆山)股份有限公司 改善焊盘外形限制锡膏扩散的结构和方法
US9786622B2 (en) * 2011-10-20 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US20130099371A1 (en) * 2011-10-21 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having solder jointed region with controlled ag content
US8952529B2 (en) * 2011-11-22 2015-02-10 Stats Chippac, Ltd. Semiconductor device with conductive layer over substrate with vents to channel bump material and reduce interconnect voids
US9257385B2 (en) * 2011-12-07 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Landing areas of bonding structures
US8633588B2 (en) * 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
US9659893B2 (en) 2011-12-21 2017-05-23 Mediatek Inc. Semiconductor package
US8497579B1 (en) * 2012-02-16 2013-07-30 Chipbond Technology Corporation Semiconductor packaging method and structure thereof
US9064757B2 (en) * 2012-02-29 2015-06-23 Mediatek Inc. Enhanced flip chip structure using copper column interconnect
US9437534B2 (en) * 2012-02-29 2016-09-06 Mediatek Inc. Enhanced flip chip structure using copper column interconnect
US9935038B2 (en) * 2012-04-11 2018-04-03 Taiwan Semiconductor Manufacturing Company Semiconductor device packages and methods
CN104221480B (zh) * 2012-04-19 2017-09-08 松下知识产权经营株式会社 电子零件安装方法及电子零件安装线
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
JP2014072371A (ja) * 2012-09-28 2014-04-21 Ibiden Co Ltd プリント配線板及びプリント配線板の製造方法
JP2014072370A (ja) * 2012-09-28 2014-04-21 Ibiden Co Ltd プリント配線板及びプリント配線板の製造方法
TWI491347B (zh) * 2012-10-24 2015-07-01 Hon Hai Prec Ind Co Ltd 散熱板及封裝殼體
JP5913063B2 (ja) * 2012-11-27 2016-04-27 日本特殊陶業株式会社 配線基板
US8877558B2 (en) * 2013-02-07 2014-11-04 Harris Corporation Method for making electronic device with liquid crystal polymer and related devices
TW201436665A (zh) * 2013-03-07 2014-09-16 Delta Electronics Inc 電路板設置緩衝墊的自動化製程及結構
US9536850B2 (en) * 2013-03-08 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
US9418928B2 (en) * 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9508637B2 (en) 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9275967B2 (en) 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9305890B2 (en) 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
US9806046B2 (en) * 2014-03-13 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and manufacturing method
CN106463427B (zh) * 2014-06-27 2020-03-13 索尼公司 半导体装置及其制造方法
US9589924B2 (en) * 2014-08-28 2017-03-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
TWI562255B (en) * 2015-05-04 2016-12-11 Chipmos Technologies Inc Chip package structure and manufacturing method thereof
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
CN107591385A (zh) * 2016-07-08 2018-01-16 欣兴电子股份有限公司 封装基板及其制造方法
US10109570B2 (en) 2016-09-21 2018-10-23 Intel Corporation Radial solder ball pattern for attaching semiconductor and micromechanical chips
CN106777718A (zh) * 2016-12-23 2017-05-31 上海斐讯数据通信技术有限公司 一种pcb光绘文件处理方法及处理系统
US11393771B2 (en) 2018-09-27 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures in semiconductor packaged device and method of forming same
DE102019117917B4 (de) 2018-09-27 2023-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Bondingstrukturen in halbleiter-packages und verfahren zu ihrer herstellung
KR20210138223A (ko) 2020-05-12 2021-11-19 삼성전자주식회사 반도체 패키지
US11404390B2 (en) * 2020-06-30 2022-08-02 Micron Technology, Inc. Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
KR20220055112A (ko) 2020-10-26 2022-05-03 삼성전자주식회사 반도체 칩들을 갖는 반도체 패키지
KR20220089365A (ko) * 2020-12-21 2022-06-28 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
KR20220155741A (ko) 2021-05-17 2022-11-24 삼성전자주식회사 반도체 패키지
KR20230111542A (ko) * 2022-01-18 2023-07-25 엘지이노텍 주식회사 반도체 패키지

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229209B1 (en) * 1995-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Chip carrier
US6462425B1 (en) * 1999-04-19 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20030067084A1 (en) * 2000-06-28 2003-04-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20040108135A1 (en) * 2002-10-11 2004-06-10 Takeshi Ashida Circuit board, mounting structure of ball grid array, electro-optic device and electronic device
US6809262B1 (en) * 2003-06-03 2004-10-26 Via Technologies, Inc. Flip chip package carrier
US20050040524A1 (en) * 2003-08-18 2005-02-24 Siliconware Precision Industries Co., Ltd. Chip carrier for semiconductor chip

Family Cites Families (203)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719737B2 (ja) 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JPH04355933A (ja) * 1991-02-07 1992-12-09 Nitto Denko Corp フリツプチツプの実装構造
JPH0528037A (ja) 1991-07-23 1993-02-05 Nec Corp バツフア管理方式
US5186383A (en) 1991-10-02 1993-02-16 Motorola, Inc. Method for forming solder bump interconnections to a solder-plated circuit trace
US5383916A (en) 1991-11-12 1995-01-24 Puretan International, Inc. Support member for a tanning bed or comparable device
JP2678958B2 (ja) * 1992-03-02 1997-11-19 カシオ計算機株式会社 フィルム配線基板およびその製造方法
US5314651A (en) * 1992-05-29 1994-05-24 Texas Instruments Incorporated Fine-grain pyroelectric detector material and method
JP3152796B2 (ja) 1993-05-28 2001-04-03 株式会社東芝 半導体装置およびその製造方法
US5386624A (en) * 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5519580A (en) * 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
JP3353508B2 (ja) * 1994-12-20 2002-12-03 ソニー株式会社 プリント配線板とこれを用いた電子装置
US5650595A (en) 1995-05-25 1997-07-22 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
EP0747954A3 (en) * 1995-06-07 1997-05-07 Ibm Solder ball comprising a metal cover with low melting point
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
KR0182073B1 (ko) * 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JPH09260552A (ja) * 1996-03-22 1997-10-03 Nec Corp 半導体チップの実装構造
JP2751912B2 (ja) 1996-03-28 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
KR100216839B1 (ko) * 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US5854514A (en) 1996-08-05 1998-12-29 International Buisness Machines Corporation Lead-free interconnection for electronic devices
US5775569A (en) 1996-10-31 1998-07-07 Ibm Corporation Method for building interconnect structures by injection molded solder and structures built
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5729896A (en) 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
KR100467897B1 (ko) 1996-12-24 2005-01-24 닛토덴코 가부시키가이샤 반도체 장치 및 이의 제조방법
US6002172A (en) * 1997-03-12 1999-12-14 International Business Machines Corporation Substrate structure and method for improving attachment reliability of semiconductor chips and modules
JP3500032B2 (ja) * 1997-03-13 2004-02-23 日本特殊陶業株式会社 配線基板及びその製造方法
JPH10270496A (ja) * 1997-03-27 1998-10-09 Hitachi Ltd 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法
JP3346263B2 (ja) * 1997-04-11 2002-11-18 イビデン株式会社 プリント配線板及びその製造方法
WO1999000842A1 (en) * 1997-06-26 1999-01-07 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
JPH1126919A (ja) * 1997-06-30 1999-01-29 Fuji Photo Film Co Ltd プリント配線板
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5985456A (en) * 1997-07-21 1999-11-16 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
US6335222B1 (en) 1997-09-18 2002-01-01 Tessera, Inc. Microelectronic packages with solder interconnections
US6448665B1 (en) * 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
JPH11145176A (ja) 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
JP3819576B2 (ja) * 1997-12-25 2006-09-13 沖電気工業株式会社 半導体装置及びその製造方法
US6303408B1 (en) 1998-02-03 2001-10-16 Tessera, Inc. Microelectronic assemblies with composite conductive elements
JPH11233571A (ja) 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びアンダーフィル材並びに熱硬化性フィルム材
US6324754B1 (en) * 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
US6329605B1 (en) * 1998-03-26 2001-12-11 Tessera, Inc. Components with conductive solder mask layers
JPH11330162A (ja) * 1998-05-19 1999-11-30 Sony Corp 半導体チップの実装方法
JP2000031204A (ja) * 1998-07-07 2000-01-28 Ricoh Co Ltd 半導体パッケージの製造方法
EP1099247B1 (en) 1998-07-15 2004-03-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method for transferring solder to a device and/or testing the device
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
DE19839760A1 (de) 1998-09-01 2000-03-02 Bosch Gmbh Robert Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung
WO2000019517A1 (fr) * 1998-09-30 2000-04-06 Ibiden Co., Ltd. Microplaquette semi-conductrice et procede de fabrication
JP2000133667A (ja) * 1998-10-22 2000-05-12 Citizen Watch Co Ltd 突起電極の形成方法
JP2000133672A (ja) * 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6383916B1 (en) 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
JP3346320B2 (ja) * 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
JP4024958B2 (ja) 1999-03-15 2007-12-19 株式会社ルネサステクノロジ 半導体装置および半導体実装構造体
US6556268B1 (en) 1999-03-31 2003-04-29 Industrial Technology Research Institute Method for forming compact LCD packages and devices formed in which first bonding PCB to LCD panel and second bonding driver chip to PCB
US6225206B1 (en) 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
JP2000349194A (ja) 1999-06-08 2000-12-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
US6458622B1 (en) 1999-07-06 2002-10-01 Motorola, Inc. Stress compensation composition and semiconductor component formed using the stress compensation composition
US6122171A (en) 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
JP2001068836A (ja) * 1999-08-27 2001-03-16 Mitsubishi Electric Corp プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法
US6303400B1 (en) * 1999-09-23 2001-10-16 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
TW429492B (en) * 1999-10-21 2001-04-11 Siliconware Precision Industries Co Ltd Ball grid array package and its fabricating method
US6774474B1 (en) 1999-11-10 2004-08-10 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
JP2001156203A (ja) 1999-11-24 2001-06-08 Matsushita Electric Works Ltd 半導体チップ実装用プリント配線板
JP3865989B2 (ja) 2000-01-13 2007-01-10 新光電気工業株式会社 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置
JP2001230339A (ja) * 2000-02-18 2001-08-24 Nec Corp 半導体装置
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
JP2001313314A (ja) * 2000-04-28 2001-11-09 Sony Corp バンプを用いた半導体装置、その製造方法、および、バンプの形成方法
US6661084B1 (en) 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
JP2001332583A (ja) * 2000-05-22 2001-11-30 Fujitsu Ltd 半導体チップの実装方法
US6573610B1 (en) * 2000-06-02 2003-06-03 Siliconware Precision Industries Co., Ltd. Substrate of semiconductor package for flip chip package
US6787918B1 (en) * 2000-06-02 2004-09-07 Siliconware Precision Industries Co., Ltd. Substrate structure of flip chip package
JP2001351945A (ja) * 2000-06-05 2001-12-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6201305B1 (en) * 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
JP3554533B2 (ja) * 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
CA2426330A1 (en) 2000-11-01 2002-05-10 3M Innovative Properties Company Electrical sensing and/or signal application device
JP2002151532A (ja) 2000-11-08 2002-05-24 Sharp Corp 電子部品、半導体装置の実装方法および半導体装置の実装構造
JP2002151551A (ja) 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US6552436B2 (en) 2000-12-08 2003-04-22 Motorola, Inc. Semiconductor device having a ball grid array and method therefor
DE10163799B4 (de) * 2000-12-28 2006-11-23 Matsushita Electric Works, Ltd., Kadoma Halbleiterchip-Aufbausubstrat und Verfahren zum Herstellen eines solchen Aufbausubstrates
US6518678B2 (en) 2000-12-29 2003-02-11 Micron Technology, Inc. Apparatus and method for reducing interposer compression during molding process
US6780682B2 (en) 2001-02-27 2004-08-24 Chippac, Inc. Process for precise encapsulation of flip chip interconnects
US7242099B2 (en) * 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP2002270732A (ja) 2001-03-13 2002-09-20 Sharp Corp アンダーフィル材付き電子部品
ATE458249T1 (de) 2001-03-15 2010-03-15 Halo Inc Doppelbit monos speicherzellgebrauch für breite programbandbreite
US7331502B2 (en) 2001-03-19 2008-02-19 Sumitomo Bakelite Company, Ltd. Method of manufacturing electronic part and electronic part obtained by the method
US6495397B2 (en) 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection
TW498506B (en) 2001-04-20 2002-08-11 Advanced Semiconductor Eng Flip-chip joint structure and the processing thereof
US6664483B2 (en) * 2001-05-15 2003-12-16 Intel Corporation Electronic package with high density interconnect and associated methods
US6510976B2 (en) 2001-05-18 2003-01-28 Advanpack Solutions Pte. Ltd. Method for forming a flip chip semiconductor package
US7294457B2 (en) 2001-08-07 2007-11-13 Boehringer Ingelheim (Canada) Ltd. Direct binding assay for identifying inhibitors of HCV polymerase
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US6660560B2 (en) 2001-09-10 2003-12-09 Delphi Technologies, Inc. No-flow underfill material and underfill method for flip chip devices
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
TW507341B (en) * 2001-11-01 2002-10-21 Siliconware Precision Industries Co Ltd Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate
US7202556B2 (en) 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
WO2003071842A1 (en) 2001-12-26 2003-08-28 Motorola, Inc. Method of mounting a semiconductor die on a substrate without using a solder mask
JP3891838B2 (ja) 2001-12-26 2007-03-14 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6870276B1 (en) * 2001-12-26 2005-03-22 Micron Technology, Inc. Apparatus for supporting microelectronic substrates
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
TWI268581B (en) * 2002-01-25 2006-12-11 Advanced Semiconductor Eng Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material
TWI239578B (en) * 2002-02-21 2005-09-11 Advanced Semiconductor Eng Manufacturing process of bump
JP2003264256A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
JP2003273145A (ja) * 2002-03-12 2003-09-26 Sharp Corp 半導体装置
US6767411B2 (en) 2002-03-15 2004-07-27 Delphi Technologies, Inc. Lead-free solder alloy and solder reflow process
TW550800B (en) 2002-05-27 2003-09-01 Via Tech Inc Integrated circuit package without solder mask and method for the same
US6780673B2 (en) * 2002-06-12 2004-08-24 Texas Instruments Incorporated Method of forming a semiconductor device package using a plate layer surrounding contact pads
TW558809B (en) * 2002-06-19 2003-10-21 Univ Nat Central Flip chip package and process of making the same
US6659512B1 (en) 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
US6974330B2 (en) 2002-08-08 2005-12-13 Micron Technology, Inc. Electronic devices incorporating electrical interconnections with improved reliability and methods of fabricating same
US6696644B1 (en) 2002-08-08 2004-02-24 Texas Instruments Incorporated Polymer-embedded solder bumps for reliable plastic package attachment
US6811892B2 (en) 2002-08-22 2004-11-02 Delphi Technologies, Inc. Lead-based solder alloys containing copper
JP2004095923A (ja) * 2002-09-02 2004-03-25 Murata Mfg Co Ltd 実装基板およびこの実装基板を用いた電子デバイス
US7294928B2 (en) * 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
TW561602B (en) 2002-09-09 2003-11-11 Via Tech Inc High density integrated circuit packages and method for the same
JP2004111676A (ja) * 2002-09-19 2004-04-08 Toshiba Corp 半導体装置、半導体パッケージ用部材、半導体装置の製造方法
JP2004165283A (ja) 2002-11-11 2004-06-10 Fujitsu Ltd 半導体装置
US7173342B2 (en) 2002-12-17 2007-02-06 Intel Corporation Method and apparatus for reducing electrical interconnection fatigue
JP4114483B2 (ja) * 2003-01-10 2008-07-09 セイコーエプソン株式会社 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器
US6821878B2 (en) 2003-02-27 2004-11-23 Freescale Semiconductor, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US6943058B2 (en) 2003-03-18 2005-09-13 Delphi Technologies, Inc. No-flow underfill process and material therefor
US6774497B1 (en) * 2003-03-28 2004-08-10 Freescale Semiconductor, Inc. Flip-chip assembly with thin underfill and thick solder mask
US20040232560A1 (en) 2003-05-22 2004-11-25 Chao-Yuan Su Flip chip assembly process and substrate used therewith
US20040232562A1 (en) * 2003-05-23 2004-11-25 Texas Instruments Incorporated System and method for increasing bump pad height
US6849944B2 (en) * 2003-05-30 2005-02-01 Texas Instruments Incorporated Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad
US6888255B2 (en) * 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
TWI227556B (en) * 2003-07-15 2005-02-01 Advanced Semiconductor Eng Chip structure
TWI241702B (en) * 2003-07-28 2005-10-11 Siliconware Precision Industries Co Ltd Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
KR100523330B1 (ko) * 2003-07-29 2005-10-24 삼성전자주식회사 Ｓｍｄ 및 ｎｓｍｄ 복합형 솔더볼 랜드 구조를 가지는ｂｇａ 반도체 패키지
TWI234258B (en) * 2003-08-01 2005-06-11 Advanced Semiconductor Eng Substrate with reinforced structure of contact pad
KR100541394B1 (ko) * 2003-08-23 2006-01-10 삼성전자주식회사 비한정형 볼 그리드 어레이 패키지용 배선기판 및 그의제조 방법
TWI221336B (en) * 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US7271484B2 (en) * 2003-09-25 2007-09-18 Infineon Technologies Ag Substrate for producing a soldering connection
US20050095835A1 (en) 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7112524B2 (en) * 2003-09-29 2006-09-26 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
JP3877717B2 (ja) 2003-09-30 2007-02-07 三洋電機株式会社 半導体装置およびその製造方法
JP2005109187A (ja) * 2003-09-30 2005-04-21 Tdk Corp フリップチップ実装回路基板およびその製造方法ならびに集積回路装置
TWI245389B (en) * 2003-10-02 2005-12-11 Siliconware Precision Industries Co Ltd Conductive trace structure and semiconductor package having the conductive trace structure
US7462942B2 (en) 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
KR101249555B1 (ko) 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US8076232B2 (en) * 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US7736950B2 (en) 2003-11-10 2010-06-15 Stats Chippac, Ltd. Flip chip interconnection
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US7294451B2 (en) 2003-11-18 2007-11-13 Texas Instruments Incorporated Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
JP3863161B2 (ja) 2004-01-20 2006-12-27 松下電器産業株式会社 半導体装置
WO2005093817A1 (ja) 2004-03-29 2005-10-06 Nec Corporation 半導体装置及びその製造方法
JP4024773B2 (ja) 2004-03-30 2007-12-19 シャープ株式会社 配線基板、半導体装置およびその製造方法並びに半導体モジュール装置
KR100597993B1 (ko) * 2004-04-08 2006-07-10 주식회사 네패스 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법
TWI240389B (en) * 2004-05-06 2005-09-21 Advanced Semiconductor Eng High-density layout substrate for flip-chip package
US7224073B2 (en) * 2004-05-18 2007-05-29 Ultratera Corporation Substrate for solder joint
US7183493B2 (en) 2004-06-30 2007-02-27 Intel Corporation Electronic assembly having multi-material interconnects
US7057284B2 (en) * 2004-08-12 2006-06-06 Texas Instruments Incorporated Fine pitch low-cost flip chip substrate
JP2006108313A (ja) 2004-10-04 2006-04-20 Rohm Co Ltd 実装基板および半導体装置
DE102004050178B3 (de) 2004-10-14 2006-05-04 Infineon Technologies Ag Flip-Chip-Bauelement
US7488896B2 (en) 2004-11-04 2009-02-10 Ngk Spark Plug Co., Ltd. Wiring board with semiconductor component
US8067823B2 (en) 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
US20060131758A1 (en) * 2004-12-22 2006-06-22 Stmicroelectronics, Inc. Anchored non-solder mask defined ball pad
TWI261329B (en) * 2005-03-09 2006-09-01 Phoenix Prec Technology Corp Conductive bump structure of circuit board and method for fabricating the same
US7361990B2 (en) 2005-03-17 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
JP2008535225A (ja) * 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US20060255473A1 (en) 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP4190525B2 (ja) 2005-08-22 2008-12-03 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4971769B2 (ja) 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
TWI286830B (en) 2006-01-16 2007-09-11 Siliconware Precision Industries Co Ltd Electronic carrier board
TWI294682B (en) 2006-02-03 2008-03-11 Siliconware Precision Industries Co Ltd Semiconductor package substrate
US20070200234A1 (en) 2006-02-28 2007-08-30 Texas Instruments Incorporated Flip-Chip Device Having Underfill in Controlled Gap
US7317245B1 (en) 2006-04-07 2008-01-08 Amkor Technology, Inc. Method for manufacturing a semiconductor device substrate
US7541681B2 (en) 2006-05-04 2009-06-02 Infineon Technologies Ag Interconnection structure, electronic component and method of manufacturing the same
JP2007305881A (ja) 2006-05-12 2007-11-22 Sharp Corp テープキャリアおよび半導体装置並びに半導体モジュール装置
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
KR100764055B1 (ko) 2006-09-07 2007-10-08 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법
TWI378540B (en) 2006-10-14 2012-12-01 Advanpack Solutions Pte Ltd Chip and manufacturing method thereof
US20080093749A1 (en) 2006-10-20 2008-04-24 Texas Instruments Incorporated Partial Solder Mask Defined Pad Design
TWI331388B (en) 2007-01-25 2010-10-01 Advanced Semiconductor Eng Package substrate, method of fabricating the same and chip package
JP4618260B2 (ja) 2007-02-21 2011-01-26 日本テキサス・インスツルメンツ株式会社 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置
US7521284B2 (en) 2007-03-05 2009-04-21 Texas Instruments Incorporated System and method for increased stand-off height in stud bumping process
TWI361482B (en) 2007-05-10 2012-04-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package structure and package substrate applicable thereto
US8178392B2 (en) 2007-05-18 2012-05-15 Stats Chippac Ltd. Electronic system with expansion feature
US20090057378A1 (en) 2007-08-27 2009-03-05 Chi-Won Hwang In-situ chip attachment using self-organizing solder
EP2206145A4 (en) 2007-09-28 2012-03-28 Tessera Inc FLIP-CHIP CONNECTION WITH DOUBLE POSTS
TWI357137B (en) 2007-10-19 2012-01-21 Advanced Semiconductor Eng Flip chip package structure and carrier thereof
TWI358113B (en) 2007-10-31 2012-02-11 Advanced Semiconductor Eng Substrate structure and semiconductor package usin
TW200921868A (en) 2007-11-07 2009-05-16 Advanced Semiconductor Eng Substrate structure
US7847399B2 (en) 2007-12-07 2010-12-07 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
JP5107012B2 (ja) 2007-12-12 2012-12-26 新光電気工業株式会社 配線基板及び電子部品の実装構造の製造方法
TWI340615B (en) 2008-01-30 2011-04-11 Advanced Semiconductor Eng Surface treatment process for circuit board
US7670939B2 (en) 2008-05-12 2010-03-02 Ati Technologies Ulc Semiconductor chip bump connection apparatus and method
US7851928B2 (en) 2008-06-10 2010-12-14 Texas Instruments Incorporated Semiconductor device having substrate with differentially plated copper and selective solder
TWI425896B (zh) 2008-06-11 2014-02-01 Advanced Semiconductor Eng 具有內埋式導電線路之電路板及其製造方法
KR100979497B1 (ko) 2008-06-17 2010-09-01 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
US7790509B2 (en) 2008-06-27 2010-09-07 Texas Instruments Incorporated Method for fine-pitch, low stress flip-chip interconnect
TWI384600B (zh) 2008-12-09 2013-02-01 Advanced Semiconductor Eng 內埋線路基板及其製造方法
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US20110049703A1 (en) 2009-08-25 2011-03-03 Jun-Chung Hsu Flip-Chip Package Structure
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229209B1 (en) * 1995-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Chip carrier
US6462425B1 (en) * 1999-04-19 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20030067084A1 (en) * 2000-06-28 2003-04-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20040108135A1 (en) * 2002-10-11 2004-06-10 Takeshi Ashida Circuit board, mounting structure of ball grid array, electro-optic device and electronic device
US6809262B1 (en) * 2003-06-03 2004-10-26 Via Technologies, Inc. Flip chip package carrier
US20050040524A1 (en) * 2003-08-18 2005-02-24 Siliconware Precision Industries Co., Ltd. Chip carrier for semiconductor chip

Also Published As

Publication number Publication date
US20130026628A1 (en) 2013-01-31
WO2006105015A2 (en) 2006-10-05
US8318537B2 (en) 2012-11-27
US20060216860A1 (en) 2006-09-28
WO2006105015A3 (en) 2007-11-22
JP2012064980A (ja) 2012-03-29
US9159665B2 (en) 2015-10-13
US20120211880A9 (en) 2012-08-23
US20100193947A1 (en) 2010-08-05
JP5565875B2 (ja) 2014-08-06
KR20070107154A (ko) 2007-11-06
TW200723355A (en) 2007-06-16
JP2008535225A (ja) 2008-08-28

Similar Documents

Publication Publication Date Title
TWI404114B (zh) 具有在基板上之窄互連部位之倒裝晶片互連
JP4928945B2 (ja) バンプ−オン−リードフリップチップ相互接続
US9545014B2 (en) Flip chip interconnect solder mask
US7901983B2 (en) Bump-on-lead flip chip interconnection
JP2005005358A (ja) 半導体モジュールの積層基板間接続構造