CN109671693A - 电路引脚结构 - Google Patents

电路引脚结构 Download PDF

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Publication number
CN109671693A
CN109671693A CN201811203795.0A CN201811203795A CN109671693A CN 109671693 A CN109671693 A CN 109671693A CN 201811203795 A CN201811203795 A CN 201811203795A CN 109671693 A CN109671693 A CN 109671693A
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CN
China
Prior art keywords
pin
convex block
width
interconnecting piece
lead
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Pending
Application number
CN201811203795.0A
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English (en)
Inventor
曾国玮
陈柏琦
郑瑞轩
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Sitronix Technology Corp
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Sitronix Technology Corp
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Publication of CN109671693A publication Critical patent/CN109671693A/zh
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Abstract

本发明揭示一种电路引脚结构，其包含一第一引脚与一第二引脚。该第一引脚具有一第一凸块连接部与一第一引线段，该第一引线段连接于该第一凸块连接部，该第一引线段的宽度小于该第一凸块连接部的宽度。该第二引脚相邻于该第一引脚，并与该第一引脚之间具有一引脚间隙，且具有一第二凸块连接部与一第一引线段，该第二引脚的该第一引线段连接于该第二凸块连接部，该第二凸块连接部与该第一凸块连接部呈错位排列，该第二凸块连接部相邻该第一引脚的该第一引线段。

Description

电路引脚结构
技术领域
本发明是有关于一种电路引脚结构，尤其是一种增加相邻引脚间的间隙(Gap)，而提高被生产的稳定度且符合细间距(Fine pitch)的电路引脚结构。
背景技术
由于近年来电子装置的功能性需求不断提升，电子装置内的芯片(IntegratedCircuit，IC)所需的接脚数量随的增加，导致相邻接脚间的间隙越来越狭小。所以在芯片封装制程中，为了在有限的空间中制作更多的引脚，以满足芯片高接脚数量的发展趋势，在封装上的引脚结构需以细间距(Fine Pitch)为目标，而缩小相邻引脚间的间隙。但是，由于相邻引脚间的间隙狭小，容易导致蚀刻液难以进入相邻引脚间，如此即造成不易蚀刻甚至无法蚀刻出引脚结构的问题。在封装技术的相关文献中，例如美国专利公告号US6,222,738B1与中华人民共和国专利公告号CN1099135C2，皆未提出引脚结构以细间距为目标的技术内容，而且也未针对蚀刻问题提出解决方案。因此，目前的芯片封装制程中，引脚结构的间隙限制已经局限了芯片设计，举例而言，一般封装厂会限制引脚结构的间距的最小值(例如20μm)，以确保相邻的引脚结构具有足够大的间隙，此即造成有限的电路空间中可容纳的引脚结构数量受限。
鉴于上述习知技术的不足，本发明提供一种电路引脚结构，可在无需修改制程参数、无需提升机台能力及不增加制造成本下稳定被形成，且形成的电路引脚结构能稳定符合细间距(Fine Pitch)的目标，如此即提升生产良率。
发明内容
本发明的目的，在于提供一种电路引脚结构，其运用颈缩设计增加相邻引脚间的间隙，而让生产制程稳定形成符合细间距目标的引脚结构，以提升制造良率。
本发明揭示一种电路引脚结构，其包含一第一引脚与一第二引脚。该第一引脚具有一第一凸块连接部与一第一引线段，该第一引线段连接于该第一凸块连接部，该第一引线段的宽度小于该第一凸块连接部的宽度。该第二引脚相邻于该第一引脚，并与该第一引脚的间具有一引脚间隙，且具有一第二凸块连接部与一第一引线段，该第二引脚的该第一引线段连接于该第二凸块连接部，该第二凸块连接部与该第一凸块连接部呈错位排列，该第二凸块连接部相邻该第一引脚的该第一引线段。
附图说明
图1：其为本发明的薄膜覆晶封装的一实施例的侧视图；
图2：其为本发明的电路引脚结构应用于薄膜覆晶封装的一第一实施例的俯视图；
图3：其为本发明的电路引脚结构应用于薄膜覆晶封装的一第二实施例的俯视图；
图4：其为本发明的电路引脚结构的一第二实施例的示意图；
图5：其为本发明的电路引脚结构的一第三实施例的示意图；
图6：其为本发明的电路引脚结构的一第四实施例的示意图；
图7：其为本发明的电路引脚结构的一第五实施例的示意图；
图8：其为本发明的电路引脚结构的一第六实施例的示意图；
图9：其为本发明的电路引脚结构的一第七实施例的示意图；
图10：其为本发明的电路引脚结构的一第八实施例的示意图；及
图11：其为本发明的电路引脚结构的一第九实施例的示意图。
【图号对照说明】
10 封装结构
20 基板
30 金属层
31 金属层
32 引脚
322 凸块连接部
324 引线段
326 引线段
33 第一引脚
332 第一凸块连接部
334 第一引线段
336 第二引线段
337 转折部
35 第二引脚
352 第二凸块连接部
354 第一引线段
356 第二引线段
358 凸块连接部
36 第三引脚
362 第三凸块连接部
364 第一引线段
366 第二引线段
367 转折部
37 引脚
38 引脚
39 引脚
40 防焊层
42 防焊层
50 涂胶层
60 芯片
62 凸块
A1 间距
A2 间距
B 间距
C0 间隙
C1 间隙
C2 间隙
C3 间隙
C4 间隙
C5 间隙
C6 间隙
D 间隙
E 间隙
F 间隙
G 间隙
具体实施方式
在说明书及后续的申请专利范围当中使用了某些词汇指称特定的组件。所属本发明技术领域中具有通常知识者应可理解，制造商可能会用不同的名词称呼同一个组件。本说明书及后续的申请专利范围并不以名称的差异作为区分组件的方式，而是以组件在整体技术上的差异作为区分的准则。在通篇说明书及后续的申请专利范围当中所提及的「包含」为一开放式用语，故应解释成「包含但不限定于」。此外，「耦接」一词在此包含任何直接及间接的电气连接手段。因此，若文中描述一第一装置耦接一第二装置，则代表该第一装置可直接电气连接该第二装置，或可透过其他装置或其他连接手段间接地电气连接至该第二装置。
为对本发明的特征及所达成的功效有更进一步的了解与认识，谨佐以实施例及配合详细的说明，说明如后：
驱动芯片的封装型态包含卷带式封装(Tape Carrier Package，TCP)、薄膜覆晶封装(Chip on Film，COF)及玻璃覆晶封装(Chip on Glass，COG)等，而以下说明选择以薄膜覆晶封装为实施例说明本发明的电路引脚结构。然而本发明的电路引脚结构也可应用于其他封装型态，其实施方式不再重复说明。
请参阅图1，其为本发明的薄膜覆晶封装的一实施例的侧视图。如图所示，封装结构10包含一基板20、位于基板20的左右两侧的金属层30、31、复数防焊层40、42及一涂胶层50，而用于封装一芯片60，复数凸块62形成于芯片60的底部的焊垫(图未视)。其中，该基板20较佳为一可挠性基板，故该基板20的材料较佳为可弯折材料，例如该基板20的材料可以包含聚酰亚胺(Polyimide，PI)，且其厚度可制作较薄以利弯折；该些金属层30、31的材料可以是为传递讯号效果佳的金属，例如铜(Cu)、金(Au)、银(Ag)、铁(Fe)、锡(Sn)等等；该些凸块62的材料可以是金(Au)或者锡铅(Sn/Pb)，而位于基板20的左右两侧的金属层30、31为经由蚀刻后所形成的电路引脚结构，而用于传递讯号。该些凸块62分别连接于金属层30、31，即该些凸块62是连接芯片60与金属层30、31的桥梁，该些防焊层40、42分别覆盖该些金属层30、31的部分区域，即覆盖电路引脚结构的部份结构，例如覆盖电路引脚结构中非用于焊接的引线段，以保护电路引脚结构，例如避免被氧化或者避免焊锡沾到电路引脚结构，而造成短路。涂胶层50涂布于该些防焊层40、42间，而覆盖位于该些防焊层40、42间的基板20、该些金属层30、31与该些凸块62，涂胶层50更覆盖部分防焊层40、42与芯片60的底部与侧面。涂胶层50于烘烤制程后即会硬化，而保护涂胶层50所覆盖的该些金属层(引脚结构)30、31、该些凸块62与芯片60。位于该些防焊层40、42间的引脚结构的引线段可称为内引脚，非位于该些防焊层40、42间的引脚结构的引线段可称为外引脚，以用于连接外部电路。
请参阅图2，其为本发明的电路引脚结构应用于薄膜覆晶封装的一第一实施例的俯视图。为了清楚表示本发明的电路引脚结构与习知电路引脚结构的差异，绘示于图2的薄膜覆晶封装10同时包含本发明的电路引脚结构与习知电路引脚结构。如图所示，左侧金属层30为经由蚀刻后所形成的本发明的电路引脚结构，其包括复数引脚33、35、36，该些引脚33、35、36彼此相邻，且彼此间皆具有一引脚间隙(Gap)而互相不接触，如第二引脚35相邻于第一引脚33且不接触第一引脚33。右侧金属层31为经由蚀刻后所形成的习知电路引脚结构，其包括复数引脚37、38、39，该些引脚37、38、39彼此相邻，且彼此间皆具有引脚间隙而互相不接触。每一引脚37、38、39呈长条状。该些引脚37、38、39的一端相对于芯片60的底部，而分别连接位于芯片60的底部的该些凸块62，因此该些引脚37、38、39的宽度大于凸块62的宽度。该些引脚37、38、39的另一端未被防焊层42覆盖，以连接外部电路(图未示)。
复参阅图2，本发明的第一引脚33具有一第一凸块连接部332、一第一引线段334与一第二引线段336，第一引线段334连接于第一凸块连接部332与第二引线段336之间。第二引脚35具有一第二凸块连接部352、一第一引线段354与一第二引线段356，第一引线段354连接于第二凸块连接部352与第二引线段356之间。第三引脚36具有一第三凸块连接部362、一第一引线段364与一第二引线段366，第一引线段364连接于第三凸块连接部362与第二引线段366之间，于本实施例中，第三引脚36同于第一引脚33，但并非限制第三引脚36必须相同于第一引脚33。上述该些引脚33、35、36的该些凸块连接部332、352、362分别连接位于芯片60的底部的该些凸块62，而该些引脚33、35、36的该些第二引线段336、356、366的一端未被防焊层40覆盖，以连接外部电路。
于图2实施例中，第一引脚33的第一引线段334的宽度与第二引线段336的宽度小于第一凸块连接部332的宽度，第二引脚35的第一引线段354的宽度与第二引线段356的宽度小于第二凸块连接部352的宽度，第三引脚36的第一引线段364的宽度与第二引线段366的宽度小于第三凸块连接部362的宽度。由于，本发明的电路引脚结构运用颈缩设计，如此增加第一引脚33与第二引脚35间的引脚间隙，例如第一引脚33的第一引线段334的宽度与第二引线段336的宽度小于第一凸块连接部332的宽度，如此增加第一引脚33的第一引线段334与第二引脚35的第一引线段354间的间隙C1以及第一引脚33的第二引线段336与第二引脚35的第二引线段356间的间隙C2。此外，第二凸块连接部352可以位于第一引线段334的一侧，而相邻第一引线段334，即第一凸块连接部332可以与第二凸块连接部352呈错位排列(于图面上的水平方向)，而更进一步增加了第一引脚33与第二引脚35间的引脚间隙，例如第二引脚35的第二凸块连接部352与第一引脚33的第一引线段334间的间隙C3。上述错位排列是指第一凸块连接部332位于第二凸块连接部352的前方(于图面上的水平方向)，而第二凸块连接部352可以相邻或不相邻第一凸块连接部332。同样地，第二凸块连接部352也相邻第三引脚36的第一引线段364，第三凸块连接部362也与第二凸块连接部352呈错位排列(于图面上的水平方向)，以增加第二引脚35与第三引脚36间的引脚间隙。
复参阅图2，虽然在本实施例中，第一引脚33的第二引线段336的宽度大于第一引线段334的宽度，但并非限制每个引脚的第二引线段的宽度必须大于第一引线段的宽度，例如第二引脚35的第二引线段356的宽度就可设计与其第一引线段354的宽度相同。于本发明另一实施例中，第一引脚33的第二引线段336的宽度并非必须小于第一凸块连接部332的宽度；第二引脚35的第一引线段354的宽度与第二引线段356的宽度并非必须小于第二凸块连接部352的宽度；第三引脚36的第二引线段366的宽度并非必须小于第三凸块连接部362的宽度。
为了明显比较本发明的电路引脚结构与习知电路引脚结构的差异，图2所示的本发明的电路引脚结构的间距与习知电路引脚结构的间距为相同，例如间距A1、B皆为了符合细间距(Fine pitch)设计目标而为18μm，间距一般定义为两相邻引脚结构中的间隙与其中一引脚结构的宽度的总和，因此间距A1可为本发明的第二引线段336的宽度与间隙C2的总和，间距B为习知的引脚37的宽度与间隙C0的总和。从图2可知，习知电路引脚结构的引脚37与引脚38间的间隙C0明显小于本发明的电路引脚结构的第一引脚33与第二引脚35间的间隙C1、C2、C3，如此进行蚀刻制程形成习知的引脚37与引脚38时，蚀刻液不易进入引脚37与引脚38间，如此可能造成蚀刻不完全的现象，其表示无法稳定形成电路引脚结构而造成制造良率低的问题。相对而言，由于本发明的第一引脚33与第二引脚35间的间隙C1、C2、C3较大，所以蚀刻液可以充分进入第一引脚33与第二引脚35间，如此可稳定形成第一引脚33与第二引脚35，而可以提高制造良率。再者，采用本发明的电路引脚结构可节省引脚材料的使用而降低成本。换言之，相同的芯片接脚数下，本发明的电路引脚结构的间距A1缩小后(例如小于18μm)，位于芯片60的该些焊垫间的间隙也可以进一步缩小，如此即可以进一步缩小芯片60的面积，使晶圆可以形成更多芯片而提升单片晶圆的价值。此外，藉由让相邻的引脚的凸块连接部呈错位排列，如此可以增加相邻的引脚的凸块连接部间的间隙，而可以减少凸块连接部间的原子迁移(Migration)机率。又，在本实施例中该基板20为可挠性基板，藉由增加各引脚间的间隙可大幅降低基板20形变时相邻引脚短路或损坏的机率，使得各引脚线路制作完成后，得以承受多次弯折却不至于毁损断线。
请参阅图3，其为本发明的电路引脚结构应用于薄膜覆晶封装的一第二实施例的俯视图。从图2实施例可以得知，由于本发明电路引脚结构采用颈缩设计，所以在相同引脚间距下，本发明电路引脚结构的间隙明显大于习知电路引脚结构的间隙，如此可藉由缩小间隙，而可进一步缩小引脚间距，而提高面积使用效率。图3实施例中，位于基板20的左侧的本发明电路引脚结构的间距A2小于图2实施例中的间距A1，例如间距A2为14μm，而位于基板20的右侧的习知电路引脚结构的间距B同于图2所示的间距B。如此，在相同于习用三条引脚37、38、39所占用的面积下，可以形成本发明的四条引脚32、33、35、36。
此外，在第一引线段334采用颈缩设计下，第二凸块连接部352可以位于第一引线段334的颈缩部位，即相邻于第一引线段334，如此第一凸块连接部332可以与第二凸块连接部352呈错位排列，错位排列是指第二凸块连接部352未相邻第一凸块连接部332。再者，运用颈缩设计的第一引线段334未超出涂胶层50的范围，所以，第一引线段334不容易遭到外在应力而被破坏。此外，引线段334、336、354、356、364、366、324、326的宽幅缩小后，其所占用的面积随着缩小，而可以降低电容平板效应。再者，一般于蚀刻制程中，若相邻的两引脚间的间隙太过狭小，则会有蚀刻不完全或者无法蚀刻的现象，导致相邻的两引脚呈现短路状态，由于习知电路引脚结构的相邻的两引脚间的间隙有限，再缩小的空间不大，所以不易形成符合较严苛细间距要求的习知电路引脚结构，例如细间距为14μm。然而，相较于习知电路引脚结构，本发明的电路引脚结构运用颈缩设计可以增加相邻的两引脚间的间隙，如此本发明的电路引脚结构可稳定被形成且符合严苛细间距要求。实际上，由于习知电路引脚结构的引脚37与引脚38的宽度必须大于凸块62的宽度，若欲使引脚37与引脚38的间距小至14μm，则引脚37与引脚38的间隙C0需小至6μm，间隙如此狭小的引脚结构会大幅提升上述蚀刻不完全的发生机率。一般而言，蚀刻形成间距B为14μm的习知电路引脚结构的良率不超过10％，根本无法量产化，而蚀刻形成间距A2为14μm的本发明电路引脚结构的良率可大幅提升，达到使产品可量产化之目的，所以运用本发明之电路引脚结构，对于符合间距为14μm的要求而言，良率可以大幅提升。而且，因引线段的宽幅缩小，使相邻之两引线段间的间隙加大，而可减少大电流凸波的发生率及可减少封装期间金属物散落所造成的短路问题，并可提升抗静电能力。
复参阅图3，第一引线段334相邻第一引线段354，两者间具有一间隙C4，此实施例中所述的间距是指引线段的宽度与间隙的总和，例如间距是第一引线段334的宽度与间隙C4的总和，其可为14μm～18μm且小于18μm。第一引线段354的宽度与间隙C4的总和同样也可为14μm～18μm且小于18μm。再者，第二凸块连接部352相邻第一引线段334，第二凸块连接部352与第一引线段334之间具有一间隙C5，第一引线段334的宽度与间隙C5的总和同样可为14μm～18μm且小于18μm。此外，第二引线段336与第二引线段356之间具有一间隙C6，第二引线段336的宽度与间隙C6的总和同样可为14μm～18μm且小于18μm。
请参阅图4，其为本发明的电路引脚结构的第二实施例的示意图。如图所示，第一引线段334与第二引线段336的宽度小于第一凸块连接部332的宽度，第一引线段354与第二引线段356的宽度小于第二凸块连接部352的宽度。而且，第一引线段334的宽度等于第二引线段336的宽度，第一引线段354的宽度等于第二引线段356的宽度。第一引线段334的侧边为平面状，第二凸块连接部352的侧边平行于第一引线段334的侧边而为平面状。再者，图4实施例的引脚结构可以包含转折部，例如第一引脚33的结构包含转折部337，第一引线段334连接于转折部337的底部，一转折部337的顶部连接第二引线段336。第三引脚36的结构包含一转折部367，第一引线段364连接于转折部367的顶部，转折部367的底部连接第二引线段366。所以，第二引脚35的第二凸块连接部352位于颈缩设计的两个第一引线段334、364的间。然，凸块连接部也可以位于颈缩设计的两个第二引线段的间。
请参阅图5，其为本发明的电路引脚结构的第三实施例的示意图。如图所示，第一凸块连接部332的宽度等于第二引线段336的宽度，第二凸块连接部352的宽度等于第二引线段356的宽度。而且，第一引线段334的宽度小于第二引线段336的宽度，第一引线段354的宽度小于第二引线段356的宽度。如此，由图4与图5的实施例可知，第一引脚33的第二引线段336的宽度可以大于第一引线段334的宽度，且小于等于第一凸块连接部332的宽度。
请参阅图6，其为本发明的电路引脚结构的第四实施例的示意图。如图所示，第二凸块连接部352相邻第一引线段334，第二凸块连接部352与第一引线段334之间具有一第一间隙D，第一引线段354相邻第二引线段336，第一引线段354与第二引线段336之间具有一第二间隙E，第一间隙D相同于第二间隙E。
请参阅图7，其为本发明的电路引脚结构的第五实施例的示意图。如图所示，第一引线段334的宽度小于第一凸块连接部332的宽度，第二引线段336的宽度等于第一凸块连接部332的宽度，第一引线段354与第二引线段356的宽度小于第二凸块连接部352的宽度。而且第一引线段354的宽度等于第二引线段356的宽度。
请参阅图8，其为本发明的电路引脚结构的第六实施例的示意图。如图所示，第一引线段334的宽度小于第一凸块连接部332的宽度，第二引线段336的宽度等于第一凸块连接部332的宽度，第一引线段354的宽度小于第二凸块连接部352的宽度，而第一引线段354的宽度等于第二引线段356的宽度。
除了图4至图8的实施例，为了有利于涂胶制程的排胶可以将引脚的外型修改为圆滑外型。请参阅图9，其为本发明的电路引脚结构的一第七实施例的示意图。如图所示，第二凸块连接部352改为圆滑外型以利涂胶制程的排胶。而且，第一引线段334的侧边为一曲状，第二凸块连接部352的侧边对应第一引线段334的侧边而为曲状。
请参阅图10，其为本发明的电路引脚结构的一第八实施例的示意图。如图所示，第一凸块连接部332与第二凸块连接部352皆改为圆滑外型以利涂胶制程的排胶。再者，第二凸块连接部352相邻第一引线段334，第二凸块连接部352与第一引线段334之间具有一间隙F，第一引线段354相邻第二引线段336，第一引线段354与第二引线段336之间具有一间隙G，间隙F不同于间隙G。此外，图10实施例的第二引脚35的结构因位于颈缩设计的第一引脚33与第三引脚36之间，所以第二引脚35的第一引线段354的宽度可以改为与第二凸块连接部352的宽度相同。或者，第二引脚35的第一引线段354与第二引线段356的宽度可以皆改为与第二凸块连接部352的宽度相同。如此，间隙F由不同于间隙G改为相同于间隙G。
请参阅图11，其为本发明的电路引脚结构的一第九实施例的示意图。如图所示，图11实施例的引脚结构中的第二凸块连接部352可以为不同形状，例如改为凸块连接部358的形状。再者，上述各种实施方式的电路引脚结构，因引线段的宽幅缩小，促使引线段与相邻的引线段或凸块间距加大，而有助于组件的散热。此外，实施方式所列举各种电路引脚结构的不同态样皆可选择性交互应用，例如图10所示圆滑外型的凸块连接部可以应用于图4，将图4的凸块连接部由矩形改为圆滑外型。或者，将图5所示第一引线段334的宽度小于第二引线段336的宽度应用于图4，而将图4所示第一引线段334与第二引线段336的宽度从相等改为不相等。
综上所述，本发明揭示一种电路引脚结构，其包含一第一引脚与一第二引脚。该第一引脚具有一第一凸块连接部与一第一引线段，该第一引线段连接于该第一凸块连接部，该第一引线段的宽度小于该第一凸块连接部的宽度。该第二引脚相邻于该第一引脚，并与该第一引脚之间具有一引脚间隙，且具有一第二凸块连接部与一第一引线段，该第一引线段连接于该第二凸块连接部，该第二凸块连接部与该第一凸块连接部呈错位排列，该第二凸块连接部相邻该第一引脚的该第一引线段。
本发明的电路引脚结构的技术可以普及至各贴合Tape厂，且在无需额外采买机台及无需耗费用下可提升形成符合细间距的电路引脚结构的稳定度及制造良率。
上文仅为本发明的较佳实施例而已，并非用来限定本发明实施的范围，凡依本发明权利要求范围所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的权利要求范围内。

Claims (18)

1.一种电路引脚结构，其特征在于，其包含：
一第一引脚，具有一第一凸块连接部与一第一引线段，该第一引线段连接于该第一凸块连接部，该第一引线段的宽度小于该第一凸块连接部的宽度；及
一第二引脚，相邻于该第一引脚，并与该第一引脚之间具有一引脚间隙，且具有一第二凸块连接部与一第一引线段，该第二引脚的该第一引线段连接于该第二凸块连接部，该第一凸块连接部与该第二凸块连接部呈错位排列，该第二凸块连接部相邻该第一引脚的该第一引线段。
2.如权利要求1所述的电路引脚结构，其特征在于，其中，该第二引脚的该第一引线段的宽度小于该第二凸块连接部的宽度。
3.如权利要求1所述的电路引脚结构，其特征在于，其中，该第一引脚的该第一引线段相邻该第二引脚的该第一引线段，该第一引脚的该第一引线段与该第二引脚的该第一引线段之间具有一间隙，该第一引脚的该第一引线段的宽度与该间隙的总和为14μm~18μm且小于18μm，该第二引脚的该第一引线段的宽度与该间隙的总和为14μm~18μm且小于18μm。
4.如权利要求1所述的电路引脚结构，其特征在于，其中，该第二凸块连接部相邻该第一引脚的该第一引线段，该第二凸块连接部与该第一引脚的该第一引线段之间具有一间隙，该第一引脚的该第一引线段的宽度与该间隙的总和为14μm~18μm且小于18μm。
5.如权利要求1所述的电路引脚结构，其特征在于，其中，该第一引脚更具有一第二引线段，该第一引脚的该第一引线段连接于该第一凸块连接部与该第二引线段之间。
6.如权利要求5所述的电路引脚结构，其特征在于，其中，该第一引脚的该第一引线段的宽度与该第二引线段的宽度小于该第一凸块连接部的宽度。
7.如权利要求5所述的电路引脚结构，其特征在于，其中，该第二引线段的宽度等于该第一凸块连接部的宽度。
8.如权利要求5所述的电路引脚结构，其特征在于，其中，该第二引线段的宽度等于该第一引脚的该第一引线段的宽度。
9.如权利要求5所述的电路引脚结构，其特征在于，其中，该第二引线段的宽度大于该第一引脚的该第一引线段的宽度，且小于等于该第一凸块连接部的宽度。
10.如权利要求5所述的电路引脚结构，其特征在于，其中，该第二凸块连接部相邻该第一引脚的该第一引线段，该第二凸块连接部与该第一引脚的该第一引线段之间具有一第一间隙，该第二引脚的该第一引线段相邻该第一引脚的该第二引线段，该第二引脚的该第一引线段与该第一引脚的该第二引线段之间具有一第二间隙，该第一间隙相同或不同于该第二间隙。
11.如权利要求1所述的电路引脚结构，其特征在于，其中，该第二引脚更具有一第二引线段，该第二引脚的该第一引线段连接于该第二凸块连接部与该第二引线段之间。
12.如权利要求11所述的电路引脚结构，其特征在于，其中，该第二引脚的该第一引线段的宽度与该第二引线段的宽度小于该第二凸块连接部的宽度。
13.如权利要求11所述的电路引脚结构，其特征在于，其中，该第二引线段的宽度等于该第二凸块连接部的宽度。
14.如权利要求11所述的电路引脚结构，其特征在于，其中，该第二引线段的宽度等于该第二引脚的该第一引线段的宽度。
15.如权利要求11所述的电路引脚结构，其特征在于，其中，该第二引线段的宽度大于该第二引脚的该第一引线段的宽度，且小于等于该第二凸块连接部的宽度。
16.如权利要求1所述的电路引脚结构，其特征在于，更包含一第三引脚，其相邻于该第二引脚，并与该第二引脚之间具有一引脚间隙，且具有一第三凸块连接部与一第一引线段，该第三引脚的该第一引线段连接于该第三凸块连接部，该第三引脚的该第一引线段的宽度小于该第三凸块连接部的宽度，该第三凸块连接部与该第二凸块连接部呈错位排列，该第二凸块连接部相邻该第一引脚的该第一引线段与该第三引脚的该第一引线段。
17.如权利要求1所述的电路引脚结构，其特征在于，其中，该第一引脚的该第一引线段的侧边为曲状，该第二凸块连接部的侧边对应该第一引脚的该第一引线段的侧边而为曲状。
18.如权利要求1所述的电路引脚结构，其特征在于，其中，该第一引脚的该第一引线段的侧边为平面状，该第二凸块连接部的侧边平行于该第一引脚的该第一引线段的侧边而为平面状。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111490024A (zh) * 2020-04-16 2020-08-04 常州欣盛半导体技术股份有限公司 一种提高cof-ic封装过程中引脚剥离强度的线路结构
CN113133181A (zh) * 2019-12-31 2021-07-16 颀邦科技股份有限公司 电路板
CN113376907A (zh) * 2021-06-11 2021-09-10 四川京龙光电科技有限公司 集成功能的lcd模组

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI773257B (zh) * 2021-04-20 2022-08-01 南茂科技股份有限公司 可撓性線路基板及薄膜覆晶封裝結構

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI226111B (en) * 2003-11-06 2005-01-01 Himax Tech Inc Semiconductor packaging structure
US20050082647A1 (en) * 2003-10-04 2005-04-21 Samsung Electronics Co., Ltd. Tape circuit substrate and semiconductor chip package using the same
JP2006229018A (ja) * 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd テープキャリア基板およびその製造方法および半導体装置
US20070035036A1 (en) * 2005-08-12 2007-02-15 Sharp Kabushiki Kaisha Semiconductor device, laminated semiconductor device, and wiring substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199228A (en) * 1981-06-02 1982-12-07 Toshiba Corp Wire bonding pad device
JPS6111148Y2 (zh) 1981-06-11 1986-04-09
JPS63276235A (ja) * 1987-05-08 1988-11-14 Nec Corp 半導体集積回路装置
US6194667B1 (en) * 1998-08-19 2001-02-27 International Business Machines Corporation Receptor pad structure for chip carriers
JP4075642B2 (ja) * 2003-02-25 2008-04-16 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
KR101237172B1 (ko) * 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP4224086B2 (ja) * 2006-07-06 2009-02-12 三井金属鉱業株式会社 耐折性に優れた配線基板および半導体装置
KR100881183B1 (ko) * 2006-11-21 2009-02-05 삼성전자주식회사 높이가 다른 범프를 갖는 반도체 칩 및 이를 포함하는반도체 패키지
JP2009272571A (ja) * 2008-05-09 2009-11-19 Mitsui Mining & Smelting Co Ltd プリント配線基板及びその製造方法
WO2009153835A1 (ja) * 2008-06-18 2009-12-23 富士通株式会社 回路基板、半導体装置およびそれらの製造方法
JP4864126B2 (ja) * 2009-08-26 2012-02-01 ルネサスエレクトロニクス株式会社 Ｔｃｐ型半導体装置
JP5296116B2 (ja) 2011-02-16 2013-09-25 シャープ株式会社 半導体装置
KR102178791B1 (ko) * 2014-01-02 2020-11-13 삼성전자주식회사 반도체 패키지 기판 및 이를 포함하는 반도체 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050082647A1 (en) * 2003-10-04 2005-04-21 Samsung Electronics Co., Ltd. Tape circuit substrate and semiconductor chip package using the same
TWI226111B (en) * 2003-11-06 2005-01-01 Himax Tech Inc Semiconductor packaging structure
JP2006229018A (ja) * 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd テープキャリア基板およびその製造方法および半導体装置
US20070035036A1 (en) * 2005-08-12 2007-02-15 Sharp Kabushiki Kaisha Semiconductor device, laminated semiconductor device, and wiring substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113133181A (zh) * 2019-12-31 2021-07-16 颀邦科技股份有限公司 电路板
CN113133181B (zh) * 2019-12-31 2022-02-11 颀邦科技股份有限公司 电路板
CN111490024A (zh) * 2020-04-16 2020-08-04 常州欣盛半导体技术股份有限公司 一种提高cof-ic封装过程中引脚剥离强度的线路结构
CN113376907A (zh) * 2021-06-11 2021-09-10 四川京龙光电科技有限公司 集成功能的lcd模组

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