CN103081091A - 具有阈值电压设置凹槽的晶体管及其制造方法 - Google Patents

具有阈值电压设置凹槽的晶体管及其制造方法 Download PDF

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CN103081091A
CN103081091A CN2011800404851A CN201180040485A CN103081091A CN 103081091 A CN103081091 A CN 103081091A CN 2011800404851 A CN2011800404851 A CN 2011800404851A CN 201180040485 A CN201180040485 A CN 201180040485A CN 103081091 A CN103081091 A CN 103081091A
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layer
transistor
dopant
ddc
threshold voltage
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CN103081091B (zh
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R·阿尔加瓦尼
L·希弗伦
P·拉纳德
S·E·汤普森
C·德维尔纳夫
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Triple Fujitsu Semiconductor Co., Ltd.
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Suvolta Inc
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Abstract

结构和制造其的方法涉及深耗尽沟道（DDC）设计，允许基于CMOS的器件具有比传统体CMOS减小的σVT，并可以允许精确得多地设置沟道区中具有掺杂剂的FET的阈值电压VT。表示独特的凹槽的创新掺杂剂剖面实现了在精确范围内的VT设定的调整。通过适当选择金属可以扩展这个VT设置范围，以便在管芯上适应极宽范围的VT设置。DDC设计相比于传统体CMOS晶体管还可以具有强体效应，这可以允许DDC晶体管中有意义的功耗的动态控制。结果是能够独立控制VT（以低σVT）和VDD，以使得可以独立于给定器件的VT来调节体偏置。

Description

具有阈值电压设置凹槽的晶体管及其制造方法
技术领域
本申请总体上涉及半导体器件和与其相关的制造工艺，更具体地，涉及一种具有阈值电压设置凹槽（notch）的晶体管及其制造方法。
背景技术
一段时间以来，半导体产业使用体CMOS晶片技术来制造集成电路。将晶片切割成通常称为管芯或芯片的单个部分，其中将每一个芯片封装到电子器件中。已经证明体CMOS技术是尤其“可扩缩的”，这意味着：在优化和重复利用现有制造工艺和设备的同时，可以使得体CMOS晶体管越来越小，以便维持可接受的生产成本。在历史上，随着体CMOS晶体管的尺寸减小，其功耗也减小，这有助于业界提供增大的晶体管密度和更低的操作功率。因此，半导体行业已经能够借助体CMOS晶体管的尺寸来调整其功耗的大小，减小运行晶体管及其所在的系统的成本。
然而近年来，在减小体CMOS晶体管尺寸的同时减小其功耗已经变得越来越困难。晶体管功耗直接影响芯片功耗，其又影响运行系统的成本，且在一些情况下，影响系统的应用。例如，如果在相同芯片面积中的晶体管的数量加倍，同时每个晶体管的功耗保持相同或增大，芯片的功耗就将大于两倍。这部分是由于冷却所得到的芯片的需要，其同样需要更多的能量。结果，这会使得对运行芯片的终端用户收取的能耗费用增加一倍以上。这种增加的功耗还会相当大地减小消费电子设备的有用性，例如由于减小了移动设备的电池寿命。它还具有其它效果，例如，增大产热和对散热的需要，有可能减小系统的可靠性，以及对环境的不利影响。
在半导体工程师中已经普遍地觉察到不断地减小体CMOS的功耗是不切实际的，部分是由于认为晶体管的运行电压VDD不再能够随着晶体管尺寸减小而减小。CMOS晶体管或者导通或者截止。CMOS晶体管的状态由施加到晶体管的栅极的相对于晶体管的阈值电压VT的电压值来确定。在晶体管导通时，其消耗动态功率，这可以由以下等式来表示：
P动态=CVDD 2f
其中，VDD是提供给晶体管的运行电压，C是在晶体管导通时其负载电容，f时晶体管运行的频率。在晶体管截止时，其消耗静态功率，这可以由以下等式来表示：
P静态=IOFF VDD
其中，IOFF是晶体管截止时的泄漏电流。在历史上，业界已经主要通过减小运行电压VDD而减小了晶体管功耗，这同时减小了动态和静态功率二者。
减小运行电压VDD的能力部分取决于能够精确地设置阈值电压VT，但这随着晶体管尺寸减小而变得越来越困难。对于使用体CMOS工艺制造的晶体管，设置阈值电压VT的主要参数之一是沟道中掺杂剂的量。影响VT的其它因素是晕圈（halo）注入、源漏低掺杂扩散和沟道厚度。理论上，可以精确地完成匹配晶体管VT，以使得相同芯片上的相同晶体管具有相同的VT，但实际上掺杂剂浓度和设置中的工艺和统计学变化意味着阈值电压可以相当大地变化。这种不匹配的晶体管将不会响应于相同的栅极电压而同时全部导通，在极端情况下，一些晶体管会从不导通。更令人关心的是，不匹配的晶体管导致增大的泄漏损耗，这即使在晶体管没有有效开启的情况下也浪费功率。
对于具有100nm或更短的沟道长度的晶体管，在额定掺杂剂浓度水平，在沟道中可以设置少至30到50个掺杂剂原子。这与位于具有大于约100纳米沟道长度的前一代晶体管的沟道中的成千上万个原子形成对照。对于纳米级晶体管，如此少的掺杂剂原子的数量和设置中的内在统计学变化导致称为随机掺杂剂波动（RDF）的可检测的变化。连同工艺和材料变化一起，对于具有掺杂沟道的纳米级体CMOS晶体管，RDF是VT中变化（通常称为σVT）的主要决定因素，由RDF引起的σVT的量仅随着沟道长度减小而增大。
业界在寻找用于具有极大减小的σVT的创新晶体管的工艺和设计。然而，诸如未掺杂沟道FINFET之类的许多提出的解决方案将需要晶体管工艺制造和布局中的相当大的变化。这减缓了采用，因为业界宁愿避免重新设计，这要求传统的且广泛使用的集成电路制造工艺和晶体管布局中相当大的变化。对于片上系统（SoC）或其它高度集成的器件而言尤其是这样，所述片上系统（SoC）或其它高度集成的器件包括各种电路类型，诸如模拟输入输出电路（I/O）、数字电路及其它类型的电路。此外，考虑到在如此高度集成的系统上的不同类型的电路，如果可以改进一类或多类电路，并且任何必要的传统（legacy）电路保持相同，则仍要一起生产整体SoC，以避免制造工艺中额外的步骤。例如，如果可以实现对数字电路的改进，而所述改进不适用于模拟电路，就会希望一起同时制造电路，而不增加更多的处理步骤。可以重新设计整个集成电路，以适应在减小的电压源下的操作。本文提及的术语“重新设计”可以包括在电路制造前对晶体管栅极尺寸的适当调整。然而，在进行重新设计尝试时遇到了困难。额外的工艺和掩蔽步骤可能是复杂的、昂贵的且在技术上是困难的。
考虑到与过渡到新技术相关的实际成本与风险，半导体和电子系统的制造商长久以来在寻找扩展体CMOS的使用的方式。至少部分由于在VDD实质上减小到低于1伏时不能易于控制晶体管组中的σVT变化，就半导体产业看来，不断减小体CMOS中的功耗已经日益成为不可克服的问题。
发明内容
获得即使在低功率晶体管代替标准晶体管时也允许管芯上模拟I/O晶体管保持不变的低功率数字晶体管工艺和结构具有相当大的优点。因此，希望获得改变了一些但其他是未变化的传统电路的电路混合体，但制造它们的工艺没有实质的改变。为了减小成本并增大产量，最好是在生产总体集成电路中不实质增加制造步骤的数量。
因此，本领域中需要用于互补金属氧化物半导体（CMOS）晶体管和集成电路的改进的结构和方法，以及适合于在单一集成电路管芯上制造传统和创新的数字和模拟晶体管二者的晶体管制造工艺。会发现，本文所述的多个实施例提供了这种结构和工艺，用以以极佳的方式克服现有技术中的缺点。
提供了一套创新和多样化的结构和方法来减小一大批电子器件和系统中的功耗。这些创新和多样化的结构可以与包括传统器件的其他器件一起实现在公共硅衬底上。这些结构和方法中的一些很大程度上可以通过重新使用现有体CMOS工艺流程和制造技术来实现，这允许半导体行业以及更广泛的电子行业免于代价高且有风险地转换到替换技术。一些结构和方法涉及深耗尽沟道（DDC）设计，允许基于CMOS的器件具有比常规体CMOS减小的σVT，并可以允许精确得多地设置沟道区中具有掺杂剂的FET的阈值电压VT。存在许多方式来配置DDC以获得不同的益处，本文提出的额外的结构和方法可以单独或结合DDC一起使用，以产生额外的益处。
本公开内容介绍了相对于常规半导体制造工艺的多个技术优点。一个技术优点是提供表示独特的凹槽的掺杂剂剖面（profile），以便实现对在精确范围内的VT设定的调整。另一个技术优点是通过适当选择金属可以扩展VT设置范围，以便在管芯上适用极宽范围的VT设置。再另一个技术优点包括使用体偏置以提供对DDC晶体管中的功耗的显著动态控制。结果是能够独立控制VT（以低σVT）和VDD，以使得可以独立于给定器件的VT来调节体偏置。
本发明的某些实施例可以具有一些、全部这些优点，或者不具有这些优点。依据以下的附图、说明和权利要求，其他技术优点对于本领域技术人员而言也可以是显而易见的。
附图说明
为了更完整地理解本公开内容，结合附图参考以下的说明，在附图中，相似的参考标记代表相似的部分，其中：
图1示出了代表性的SoC以及示例性的剖面，所述代表性的SoC具有画出轮廓的DDC数字晶体管、数字传统晶体管、DDC模拟晶体管、模拟传统晶体管、高VT器件、低VT器件及其他器件的分组。
图2A是示出根据不同实施例的涉及处理不同模拟和数字器件的不同工艺步骤的总体流程图。
图2B是示出能够根据多个实施例配置的掺杂剂剖面的图示。
图2C和2D是示出能够根据多个实施例配置的多个掺杂剂剖面的图示。
图3是示出根据不同实施例的工艺步骤的晶体管工艺结构的实例。
图3A包括根据不同实施例的器件特征的两个表。
图4A-4L是示出集成电路工艺流程的一个实施例的流程图。
图5A-5J是示出集成电路工艺流程的另一个实施例的流程图。
图6A-6M是示出集成电路工艺流程的另一个实施例的流程图。
图7A-7J是示出集成电路工艺流程的另一个实施例的流程图。
具体实施方式
提供了创新的结构和方法，所述结构和方法被配置为减小大批电子器件和系统的功耗，它们可以与各种不同部件一起生产，包括数字和模拟器件，也可以与传统的器件在同一电路中一起生产。提供了对工艺友好的技术，用于在同一管芯上以精确和宽范围的VT控制和改进的σVT构造各种晶体管。此外，提供了可以在单个SoC上构造的结构，其能够分别设置体偏置系数和VT。消除这两个设置的相互影响为设计者提供了在单个SoC上混合并匹配极为不同的晶体管器件类型的能力。
可以使用DDC结构（以低σVT）精确设置VT的值，表示独特的凹槽的创新的掺杂剂剖面实现了在精确范围内的VT设置的调节，在一个实例中调节至约+/-0.2V。可以通过适当选择金属来扩展这个VT设置范围，以便在管芯上适用VT设置的极宽范围。并且有可能不必需要用于每一个晶体管的多个分离的掩蔽步骤。借助增加静态和/或动态偏置的精确设定，可以在基本上精确的范围内以宽量程VT构造不同类型的晶体管。例如，实际上可以构造具有-0.9到+0.9伏之间的VT（对于1.0VDD晶体管）的任何类型的晶体管，并构造在同一管芯上。
在功能上，这意味着本文所述的实施例提供了广泛适用的晶体管工艺步骤，其允许了复杂的高和低VT或混合信号电路的成本节约的制造。由这种工艺形成的晶体管很好地匹配和/或能够运行在传统模式中或按要求运行在各种低功率模式中。
这些创新结构和方法中的一些可以主要通过重新使用现有体CMOS工艺流程和当前的基础设施制造技术来实现，这允许半导体行业以及更广泛的电子行业免于代价高且有风险地转换到替换技术，其需要制造工艺和设备的昂贵改变。包括模拟和数字晶体管，及传统和创新结构的混合体的不同晶体管设计可以包含在单个集成电路或片上系统（SoC）中，用于改善的功率节省和性能益处。按所希望的，可以实现不同功率模式，包括传统模式或低功率模式。此外，这些新结构可以连同传统晶体管和布局结构一起包含在工艺流程中，通过避免额外的工艺步骤减小了制造商在集成电路的工艺流程中并入新结构的风险。结果，很少地或者没有增大包含创新的功率节省晶体管结构的诸如SoC的集成电路的生产费用。
还提供了用于在诸如电子产品的系统中结合并使用本文所述的本发明的方法和结构，以提供优于常规器件的低功率运行带来的实质益处。这种益处包括系统级的较低功耗、改进的系统性能、改进的系统成本、改进的系统可制造性和/或改进的系统可靠性，这是可以根据本文所述和所示实施例设计并制造的冷却器低功率系统的结果。如将要说明的，本发明可以有利地用于各种电子系统中，包括消费设备，诸如个人计算机、移动电话、电视、数字音乐播放器、机顶盒、膝上型和掌上型计算设备、电子书阅读器、数码相机、GPS系统、平板显示器、便携式数据存储设备和平板电脑，以及各种其他电子设备。在一些实施方式中，晶体管和集成电路可以实质上增强电子系统整体上的操作，以及相应的商业适用性。在一些实施例中，如本文所述的创新的晶体管、及包含它们的集成电路和系统也可以实现比替换方案对环境更为友好的实施方式。
这些及其他益处提供了数字电路中的进步，其满足了设计者、生产者和消费者的许多需要。这些益处可以提供由创新的结构组成的系统，其实现了集成电路的不断的更进一步的进步，从而得到了具有改进性能的器件和系统。本文将参考晶体管、集成电路、电子系统和相关方法来说明实施例和实例，并将在制造工艺和商业链的多个层面突出创新的结构和方法提供的（包括向电子产品的终端用户的）特征和益处。这些实例中固有的概念在生产集成电路和电子系统的结构和方法中的应用将证明是可扩展的。因此，将会理解，本发明的精神和范围不局限于这些实施例和实例，而仅由本文所附权利要求来限定，并且还限定在相关的及共同指定的应用中。
在一个实施例中，提供了创新的纳米级场效应晶体管（FET）结构，相比于具有相同沟道长度的传统掺杂沟道器件，其具有精确控制的阈值电压。在这个背景下，精确控制的阈值电压包括设置及可能的调整VT值的能力，该能力提供了σVT的显著改进或减小。该结构及其制造方法可以允许相比于传统器件的具有低运行电压的FET晶体管。一个实施例包括纳米级FET结构，其可操作以具有耗尽带或区（即，深耗尽沟道，DDC），该耗尽带或区从栅极延伸到设置在低于栅极的深度的高掺杂屏蔽层（screening layer）。在一个实施例中，与位于低于栅极至少1/2栅极长度距离的高浓度屏蔽区相比，接近栅极的沟道区基本上是未掺杂的。这提供了与高掺杂屏蔽区或层成对的基本上未掺杂的沟道区或层（小于5×1017个原子/cm3的浓度，通常形成为外延生长的硅层）。在操作中，这些结构共同起作用以限定深耗尽带或区，其终止了在近似等于或大于阈值电压的电压施加到栅极时的源自栅极的电场。
在某些实施例中，定位屏蔽层以避免与源极和漏极直接接触。在某些其他实施例中，其可以形成为在多个源极/漏极/沟道/屏蔽区下延伸的薄片。屏蔽区的厚度范围通常可以为5到50纳米。屏蔽区相对于沟道、阈值电压调节区（如果提供的话）和P阱是高掺杂的。实际上，将屏蔽区掺杂为具有在1×1018到1×1020个原子/cm3的浓度。在某些实施例中，可以在屏蔽区上涂覆碳、锗等的抗掺杂剂迁移层，以防止掺杂剂朝向未掺杂沟道和栅极迁移。
尽管主要由栅极功函数、体偏置、沟道厚度和屏蔽层的深度和掺杂剂浓度的组合设定阈值电压，但借助相邻于屏蔽区任选地提供分离的外延生长的硅层，可以对阈值电压进行小的调整。这种阈值电压调节区具有小于屏蔽区的掺杂剂浓度的掺杂剂浓度。对于通常的应用，将阈值电压调节区掺杂为具有从5×1017到2×1019个原子/cm3范围的平均浓度。当存在时，阈值调节区厚度通常可以在2到50纳米的厚度范围。在某些实施例中，碳、锗等的抗掺杂剂迁移层可以涂覆在阈值电压调节区上和/或下，以防止掺杂剂迁移到沟道区中，或者可替换地，从屏蔽区迁移到阈值电压调节区中。
如同会理解的，对于低于100nm的逻辑器件，DDC深度（Xd）可以由栅极下的屏蔽层的深度来确立，通常是栅极长度的一半（即1/2LG），有可能等于栅极长度（即LG）或者附近的中间分数（例如，3/4LG）。在一个实例中，DDC深度可以设置为大于或约等于沟道长度的一半，这在工作中允许阈值电压的精确设置设定，即使在低于1伏的低运行电压情况下。根据特定应用的需要，不同深度可以提供不同的有益结果。考虑到本公开内容，会理解不同DDC深度在不同应用、不同器件几何形状和特定设计的多个参数中是可能的。根据特定应用的参数，形成DDC晶体管中所用的不同区厚度、掺杂剂浓度和运行条件可以提供不同的有益结果。
如同将论述的，一些结构和方法与DDC设计有关，其可以在相同晶片和管芯上布置的单片电路中与传统晶体管器件一起生产。DDC可以允许CMOS器件具有相比于具有高掺杂沟道的传统体CMOS的减小的σVT，允许增大的VT的可变性。相比于传统体CMOS晶体管，DDC设计还可以具有强的体效应，这可以允许改进的体偏置辅助的对晶体管电压阈值设定的控制。存在许多方式来配置DDC，以实现不同的益处，本文提出的另外的结构和方法可以单独或结合DDC来使用，以产生额外的益处。
这些结构和制造这些结构的方法允许FET晶体管相比于传统纳米级器件具有低运行电压和低阈值电压。此外，DDC晶体管可以被配置为允许在电压体偏置生成器的帮助下静态地设置阈值电压。在一些实施例中，甚至可以动态地控制阈值电压，允许极大地减小晶体管泄漏电流（通过设定电压偏置以针对低泄漏、低速工作上调VT），或者增大晶体管泄漏电流（通过针对高泄漏、高速工作下调VT）。最终，这些结构和制造这些结构的方法用于设计具有可以在电路工作的同时进行动态调整的FET器件的集成电路。因此，可以用名义上相同的结构来设计集成电路中的晶体管，并可以控制、调节或编程，以响应于不同偏置电压在不同运行电压下工作，或者响应于不同偏置电压和运行电压在不同运行模式下工作。另外，可以在制造后配置这些以用于电路内的不同应用。
本文参考晶体管说明了某些实施例和实例，并突出了提供晶体管的创新结构和方法的特征和益处。然而，这些实例中固有的概念在生产集成电路的结构和方法中的适用性是可扩展的，并且不局限于晶体管或体CMOS。因此，在本领域中将会理解，本发明的精神和范围不局限于这些实施例和实例或本文所附权利要求，以及相关的及共同指定的应用，但可以有利地应用于其它数字电路环境中。
在以下说明中，给出了可以在其中实施本发明的一些优选方式的多个具体细节。显然，可以在无需这些具体细节的情况下实现本发明。在其它实例中，没有详细示出公知的电路、部件、算法和工艺，或者以示意性的或方框图形式示出，以便不在不必要的细节方面使得本发明难以理解。另外对于大多数部分，省略了有关于材料、工具、工艺时序、电路布局和管芯设计的细节，因为此类细节对于完整理解本发明是不必要的，认为它们在相关领域普通技术人员的理解能力内。在以下说明和权利要求中通篇使用了某些术语以指代特定系统部件。类似地，会理解，可以以不同名称来指代部件，本文的说明并非旨在区分名称上而非功能上不同的部件。在以下论述和权利要求中，以开放的方式使用词语“包括”和“包含”，因此例如应解释为意思是“包括，但不限于”。
本文说明了上述的方法和结构的多个实施例和实例。会认识到，该详细说明仅是说明性的，任何情况下都并非旨在是限制性的。本领域技术人员得益于本公开内容易于想到其它实施例。将对附图中所示的实施例加以具体介绍。相同的附图标记在附图和以下具体说明中通篇用于指代相同或相似的部分。
为了清楚，没有示出和说明本文所述的实施方式和实施例的全部常规特征。当然，会理解，在本公开内容的任何此类实际实施方式的开发中，通常会做出多个实施方式特定的决策，以便实现开发者的特定目标。此外，会理解，该开发工作有可能是复杂且耗时的，但对于得益于本公开内容的本领域技术人员来说仍然是常规的工程任务。
此外，将按照物理和功能区或层来说明注入的或者以其它方式存在于半导体的衬底或晶体层中用以改进半导体的物理和电气特性的原子的浓度。本领域技术人员可以将这些理解为具有特定浓度平均值的材料的三维体。或者，可以将它们理解为具有不同或空间上变化的浓度的子区或子层。它们也可以作为掺杂剂原子的小组、基本上类似地掺杂剂原子的区域等，或者其它物理实施例而存在。对基于这些特性的区域的说明并非旨在限制形状、实际位置或取向。它们也并非旨在将这些区域或层局限于所用的工艺步骤的任何特定类型或数量、层的类型或数量（例如，合成的或单一的）、半导体沉积、蚀刻技术、或者生长技术。这些工艺可以包括外延形成的区或原子层沉积、掺杂剂注入方法或包括线性的、单调增大的、退化或其它适合的空间变化的掺杂剂浓度的特定竖直或横向掺杂剂剖面。本文包括的实施例和实例可以示出所用的特定处理技术或材料，诸如以下说明并在以下附图中示出的外延及其它工艺。这些实例仅旨在作为说明性实例，不应将它们解释为限制性的。掺杂剂剖面可以具有掺杂剂浓度不同的一个或多个区或层，定义了浓度中的变化和如何定义区或层，不管工艺如何，是否可以借助包括红外光谱法、卢瑟福背散射法（RBS）、二次离子质谱法（SIMS）或使用不同定性或定量掺杂剂浓度确定方法的其它掺杂剂分析工具的技术来加以检测。
在一个实施例中，可以用低功率晶体管来配置用于低功率电路的构造块，例如，本文提供的低功率场效应晶体管，其可以在1.0伏或更低的电压VDD工作。在一个实例中，晶体管可以包括多晶硅栅极，具有小于100纳米的栅极长度，其中，栅极包括多晶硅层和介电层。器件进一步包括低掺杂外延沟道，其接触多晶硅栅极的介电层。可以以在低掺杂外延沟道下且在晶体管体上延伸的方式设置高掺杂屏蔽层。可以处理屏蔽层以减小掺杂剂在低掺杂外延沟道中的扩散，如以下更详细论述的。器件包括源极和漏极，以及在源极与漏极之间延伸的低掺杂外延沟道。
在某些实施例中，还可以包括体分接头，以允许将体偏置电压施加到晶体管体。体偏置依赖于体效应现象，以调节MOSFET的VT，且通常量化为体效应系数。如会理解的，相对于源极前向体偏置（FBB）所述体减小了VT，这增大了晶体管速度。然而，因为泄漏对VT的指数相关性，其还导致功率使用的大量增加。类似地，反向体偏置（RBB）减小了泄漏，但以减小速度和增大延迟为代价。在某些实施例中，例如体偏置的施加允许将阈值电压VT增大到大于0.3伏的值。
体分接头（tap）示意性地示出为在体偏置生成器与晶体管体之间的连接，根据应用，其可以应用于单个器件、器件的组、或者给定集成电路上的整个电路或子电路。根据这些实施例，改进的σVT允许更强的体偏置系数，后者又允许VT中改进的变化。在现有技术的系统中，体偏置系数通过高掺杂沟道来改进，这导致σVT的较宽且不希望出现的范围。因此，需要将高阈值电压用于此类器件，从而以体偏置间接（mediated）控制来工作。根据本文所述的实施例，可以用低σVT和VT的高可调值来构造器件。此外，在给与设计者在单个SoC上混合和匹配各种部件的独特能力的情况下，可以分离地且独立地设置和/或调节体偏置和VT。
同样，创新的结构和方法被配置为减小大批电子器件和系统中的功耗，它们可以与各种不同部件一起生产，包括数字和模拟器件，也可以与传统的器件在同一电路中一起生产。根据本文所述的实施例，提供了器件、系统和方法，它们允许极大地改进（降低）σVT，还提供了改进的和强体偏置系数。因此，具有强体偏置的各种可调VT是可能的，得到了以较低功率工作的更好性能的器件和系统。为了实现它，提供了对工艺友好的技术，用于在同一管芯上以精确和宽范围的VT控制和改进的σVT构造各种晶体管。此外，提供了可以在单个SoC上构造的结构，能够分别设置体偏置系数和VT。消除这两个设置的相互影响为设计者提供了在单个SoC上混合并匹配极为不同的晶体管器件的能力。
图1示出了示例性SoC100，以几个不同的数字和模拟晶体管结构配置在硅片115上，其可以包含在使用本文所述方法的器件中。根据本文所述的方法和工艺，可以使用体CMOS在硅上生产具有创新和传统晶体管器件和结构的各种组合的系统。在不同实施例中，可以将芯片分割为一个或多个区域，其中动态偏置结构10、静态偏置结构12或无偏置结构14分别或以某些组合方式存在。例如，在动态偏置区10中，动态可调器件16可以连同高和低VT器件18、20以及可能的DDC逻辑器件21一起存在。例如，在静态偏置区12中，DDC逻辑器件102可以连同传统逻辑器件104以及高和低VT器件22、24一起存在。在无偏置的区14中，DDC模拟器件106、传统模拟器件108和具有I/O通信信道112的传统I/O模拟系统110可以共同存在。
在该示例性系统中，各种不同器件可以存在于单个SoC100上，其可以分成不同的区，这可以取决于希望用于每一区的偏置的类型。因此，SoC100可以包括DDC数字逻辑器件102、传统数字逻辑器件104、DDC模拟器件106、传统模拟器件108及传统输入和输出（I/O）模拟电路和系统110、高和低VT器件18、20、22、24，及可能的其它器件，它们可以经由公共总线114、线路迹线（未示出）或其它互连在电路内彼此相互连接。作为公共衬底115上的体CMOS形成或者以其它方式处理器件，公共衬底115通常是硅或其它类似的衬底。
SoC100包括具有DDC横截面剖面的至少一个或多个器件106，其一个实例在此示出为各种模拟和数字晶体管120、130、140、150，它们全部可以共同形成于衬底115上。第一器件120是数字晶体管，具有栅极堆叠体122和间隔部、源极和漏极124/126、深耗尽沟道128下的浅阱127（或者晶体管的体）和屏蔽层129，屏蔽层129在浅沟槽隔离（STI）结构117之间延伸。该剖面的意义是由这个及其它器件借助深耗尽沟道和屏蔽层可能获得的低功率特性。另一个数字器件130具有栅极堆叠体132和间隔部、源极和漏极134/136、和深耗尽沟道138下的浅阱137。与器件120不同，这个数字器件130具有屏蔽层139，其连同DDC138一起在源极与漏极134/136之间延伸。类似于器件120，这个剖面的意义是由这个及其它器件借助深耗尽沟道和屏蔽层可能获得的低功率特性。
左侧第三和第四器件是模拟器件，它们分享在其沟道区中的数字器件的一些物理特性，为这些及其它类似的模拟器件提供了功率节省特征。模拟器件140是数字晶体管，具有栅极堆叠体142和间隔部、源极和漏极144/146、在深耗尽沟道148下的浅阱147，和屏蔽层149，其在STI结构117之间延伸。类似于上述的数字器件，这个模拟器件剖面的意义是由这个及其它模拟器件借助深耗尽沟道和屏蔽层可能获得的低功率特性。另一个模拟器件150具有栅极堆叠体152和间隔部、源极和漏极154/156、和在深耗尽沟道158下的浅阱157。与器件140不同，这个数字器件150具有屏蔽层159，其连同DDC158一起在源极与漏极154/156之间延伸。类似于器件140，这个剖面的意义是由这个及其它器件借助深耗尽沟道和屏蔽层可能获得的低功率特性。以下将更进一步示出并说明这些及其它器件。
在以下应用中，希望将偏置电压施加到晶体管的体127，诸如图1中所示的偏置电压源160。根据一个实施例，可以通过将偏置电压施加到体来动态设置给定器件或多个器件的VT。因此，同样，根据应用，示意性地示出为在偏置电压源160与晶体管之间的连接的体分接头可以应用于单个器件、器件的组、或者给定集成电路上的整个电路或子电路。
根据这些实施例，改进的σVT允许更强的允许VT中改进的变化的体偏置系数。这些器件可以具有高或低的VT，并可以以不同参数来构造。此外，这些器件可以构造在单个SoC上，具有分别设置体偏置系数和VT的能力。同样，消除这两个设置的相互影响为设计者提供了在单个SoC上混合并匹配极为不同的晶体管器件的能力。结果，可以调整并匹配诸如长和短沟道器件的不同器件的VT设置，以在不同器件间建立功率一致性。实际上，相比于任意器件的总VT，VT的调整相对较小，例如0.2V。可以用其它工艺得到VT中较大的变化，所述其它工艺例如为金属栅极的构造、栅极功函数、选择性EPI沉积、离子注入、退火及提供VT中更广泛变化的其它工艺。
参考图2，示出了用于生产用于模拟和数字器件的不同类型DDC结构的简要工艺流程图200。在此所示的工艺在其说明中旨在是概括和和宽泛的，以便不使得发明概念难以理解，以下阐明更详细的实施例和实例。这些连同其它工艺步骤一起允许对包括DDC结构器件以及传统器件的集成电路进行处理和制造，从而允许设计覆盖具有改进性能和较低功率的模拟和数字器件的全部范围。
此外，借助调整VT的能力，可以匹配不同晶体管，允许在同一硅晶片上生产极为不同的器件。可以使用公知的处理技术和设计规则连同传统器件一起形成创新的结构。这可以借助将体偏置系数的设置与VT的设置分离来获得。
在步骤202中，过程以阱形成开始，其可以是根据不同实施例和实例的许多不同工艺中的一个。如在203中所示的，阱形成可以在STI（浅沟槽隔离）形成204之前或之后，这取决于应用和希望的结果。硼（B）、铟（I）或其它P型材料可以用于P型注入，砷（As）或磷（P）及其它N型材料可以用于N型注入。对于PMOS阱注入，可以在10到80keV范围内以1×1013到8×1013/cm2的浓度注入P+注入。可以在5到60keV范围内以1×1013到8×1013/cm2的浓度注入As+。对于NMOS阱注入，硼注入B+注入可以在0.5到5keV范围内，并在1×1013到8×1013/cm2的浓度范围内。可以在10到60keV范围内以1×1014到5×1014/cm2的浓度执行锗注入Ge+。可以在0.5到5keV范围以1×1013到8×1013/cm2的浓度执行碳注入C+。
晶片上的一些器件是DDC类型器件，其它的是非DDC类型器件，工艺可以包括与本文所述相同的工艺流程，其中可以在无需DDC处理的某些器件上选择性地掩蔽一些注入。
阱形成202可以包括：Ge/B(N)、As(P)的束线注入，之后是外延（EPI）预清洁处理，随后最终是非选择性的均厚EPI沉积，如202A中所示的。可替换地，可以使用B(N)、As(P)的等离子体注入，之后是EPI预清洁，随后最终是非选择性（均厚）EPI沉积来形成阱，202B。阱形成可替换地包括：B(N)、As(P)的固态－源极扩散，之后是EPI预清洁，随后最终是非选择性（均厚）EPI沉积，202C。作为再另一个可替换方案，阱形成可以简单地包括：阱注入，之后是B(N)、P(P)的原位掺杂的选择性EPI。以下将进一步说明，可以以想到的不同类型的器件来配置阱形成，包括创新的DDC结构、传统结构、高VT结构、低VT结构、改进的σVT、标准或传统σVT。本文所述的实施例允许在公共衬底上以不同阱结构且根据不同参数配置的许多器件中的任意一个。
STI形成204同样可以在阱形成202之前或之后进行，其可以包括在低于900℃温度的低温沟槽牺牲氧化物（TSOX）衬里，以下结合图6A-H更详细论述。
可以用多个不同方式由不同材料以不同功函数形成或者构造栅极堆叠体204。一个选择是多晶/SiON栅极堆叠体206A。另一个选择是先栅极工艺206B，包括SiON/金属/多晶和/或SiON/多晶，随后是高K/金属栅极。另一个选择，后栅极（gate-last）工艺206C包括高K/金属栅极堆叠体，其中，可以用“先高K－后金属栅极”流程或者“后高K－后金属栅极”流程来形成栅极堆叠体。再另一个选择，206D是金属栅极，其包括可根据器件构造调节范围的功函数，N(NMOS)/P(PMOS)/N(PMOS)/P(NMOS)/中间带隙或者在其间的任何位置。在一个实例中，N具有4.05V±200mV的功函数（WF），P具有5.01V±200mV的WF。
接下来，在步骤208中，可以注入源极/漏极尖端（tip），或者任选地可以不注入，这取决于应用。尖端的尺寸可以按需要改变，并将部分取决于是否使用栅极间隔部。在一个选择中，在208A中可以不进行尖端注入。
接下来，在可任选的步骤210和212中，可以在源极和漏极区中形成PMOS或NMOS EPI层，作为应变沟道的性能增强器。本领域技术人员会理解在应变沟道的领域中存在大量的文献。
对于后栅极的栅极堆叠体选择，在步骤214中，形成后栅极模块。这可以仅用于后栅极工艺214A。
将更详细地并借助以下的实例来说明这些及其他特征。
参考图2B，示出了曲线图203，该曲线图203示出了晶体管器件中不同沟道层的不同范围。这些范围是深度和浓度的测量值，其限定了器件的不同层，包括沟道、阈值电压设置层和屏蔽层。使用包括本文所述的那些实例的多种工艺在沟道内形成这些不同层。深度和浓度的这些范围定义了体偏置（VBB）和阈值电压（VT）的示例的可能性的范围。
·X=10-50nm，理想情况下30nm（沟道）
·Y=1-30nm，理想情况下20nm（VTA层）
·Z=10-40nm，理想情况下30m（屏蔽层）
·A≤5e17at/cm3，理想情况下≤1e17at/cm3
·5e17at/cm3≤B≤5e18at/cm3，理想情况下1e18at/cm3
·5e18at/cm3≤B≤1e20at/cm3，理想情况下1e19at/cm3
·m=1-10nm/十个，理想情况下<5nm/十个
·n1=1-15nm/十个，理想情况下<5nm/十个
·n2=1-10nm/十个，理想情况下<5nm/十个
·n3>10nm/十个，理想情况下>20nm/十个
实例：
假定B是5e18
随着B增大到1e19，VT增大（高达0.5V）
随着B减小到0，VT减小（高达-0.5V）
假定X是30nm
随着X增大到50nm，VT减小（高达-0.5V）
随着X减小10nm，VT增大（高达0.5V）
假定C是1e19
随着C增大到2e19，体系数增大40%
随着C减小到5e19，体系数减小40
Figure BDA00002846631600151
假定Y是15nm
随着Y增大到30nm，VT减小（高达-0.5V）
随着Y减小到1nm，VT增大（高达0.5V）
参考图2C和2D，示出了根据以上范围配置的多个掺杂剖面。剖面220-A、220-B和220-C分别示出了：现有技术的剖面曲线，包括可以无需EPI层而执行的SSRW或逆行注入（retrograde implant）；凸和凹剖面，其也可以无需EPI层而仅以向外扩散而形成。根据本文所述的实施例，凹槽曲线示出了不同层的剖面，其定义了提供了独特的特性的沟道区、VT设置层和屏蔽层。这些特性包括在单个晶体管中分别控制VT和VBB的能力。根据凹槽所在的位置，可以实现晶体管的不同特性。在图2C和2D中示出了不同结构220-D到220-P。实例220-D包括具有90°或更大的中间拐点的凹槽，并可以在形成器件的阱和沟道时以单个EPI层产生。反向凹槽220-E具有小于90°的中间拐点，表示在VT设置层与屏蔽层之间的掺杂剂浓度中的相对下降，并可以在形成器件的阱和沟道时以分级的（graded）单个EPI层或者以双EPI层产生。浅凹槽220-F具有大于120°的凹槽角，表示与VT设置层和屏蔽层相对较平滑的浓度对比，并可以在形成器件的阱和沟道时以分级的单个EPI层产生。低水平凹槽220-G表示VT设置层中掺杂剂的较低浓度，并可以在形成器件的阱和沟道时以单个EPI层产生。深反向凹槽220-H表示相比于浅反向凹槽，在VT设置层与屏蔽层之间的浓度中较深的中间下降，并可以在形成器件的阱和沟道时以分级的单个EPI层或者以双EPI层产生。220-J中的高水平凹槽示出了VT设置层中相对高的掺杂剂浓度以及在屏蔽层之前的趋于平缓的实例，并可以在形成器件的阱和沟道时以单个EPI层产生。高反向凹槽220-K示出了VT屏蔽层中相对高的掺杂剂水平，随后在屏蔽层之前掺杂剂水平中间下降的实例，并可以在形成器件的阱和沟道时以分级的单个EPI层或者以双EPI层产生。给定上述实施例，其他变化也是可能的，包括：多凹槽剖面220-L，可以在形成器件的阱和沟道时以双或多个EPI层产生，及多反向凹槽20-M，可以在形成器件的阱和沟道时以分级的单个或多个EPI层产生。其他变化也是可能的，诸如复合剖面220-N，复合反向剖面220-O，掩埋沟道220-P，及可以用单个或多个EPI层、一个或多个分级的EPI层、及本文所述的和本领域技术人员已知的其他工艺来产生以调整在沟道不同深度的掺杂剂水平的沟道剖面的其他变化。本领域技术人员会理解，在给定本公开内容的情况下，其他剖面也是可能的。
参考图3，示出了结构的多个选项的实例300，在图4A-4L中示出了它们的工艺流程。选项A302示出了基准（baseline）创新晶体管结构，其例如可以用于逻辑电路、SRAM器件或模拟器件，其包括具有浅阱、DDC沟道和TiN/多晶栅极堆叠体的晶体管。在一个实例中，选项A包括具有金属/多晶混合栅极堆叠体的晶体管。金属可以包括TaN、TiN、TiAlN、Mo或Ni，或者其他金属，其中可以将得到的功函数从中间带隙（midgap）调节到P+或N+多晶功函数的功函数。此外，例如ALD（原子层沉积）可以用作沉积技术。沉积的方法可任选地包括PVD（物理气相沉积）或CVD（化学气相沉积）。选项B304包括基准创新晶体管结构、浅阱、DDC沟道和TiN/多晶栅极堆叠体，并进一步包括非浅阱选项，所述非浅阱选项具有POR阱、DDC沟道和TiN/多晶栅极堆叠体以及具有POR阱、DDC沟道和TiN/多晶栅极堆叠体的模拟晶体管。选项C306包括浅阱、DDC沟道和POR栅极堆叠体以及具有POR阱、DDC沟道和TiN/多晶栅极堆叠体的可任选的非浅阱。
不同选项提供了不同器件特性，并提供了使N型功函数适应于可以用于PMOS模拟器件上的栅极的能力。参考表2，以图表说明了多个器件，以显示与NMOS和PMOS结构的兼容性，表3示出了用于浅阱、非浅阱、传统器件的三个选项的适用性，以及为每一个选项的流程增加多少掩模。掩模数随每一个晶体管组合变化，如表3所示，根据所希望的选项，所需的额外掩模可以少至一个或多达三个。
图4A-L示出了用于创新的晶体管结构的基准，其例如可以用于逻辑电路、SRAM器件或模拟器件，包括具有浅阱、DDC沟道和TiN/多晶栅极堆叠体的晶体管。过程以硅晶片开始，所述硅晶片通常用于在其上形成多个集成电路。图4A-L将借助硅晶片的一系列渐进的横截面显示几个不同电路部件的处理的一个实例。图5A-5J和6A-6M将示出可替换的实施例。随着过程进展，存在不同结构的交叉和去除，其中替换或者消除了一些结构。因此，必须去除渐进图中的标记，因此在直到最后的所有图中不会显示所有编号标记。这个实例将示出用于处理部件器件的工艺，部件器件包括PMOS DDC逻辑晶体管、NMOS DDC逻辑晶体管、PMOS DDC模拟晶体管、NMOS DDC模拟晶体管、PMOS传统逻辑晶体管、NMOS传统逻辑晶体管、PMOS传统模拟晶体管、NMOS传统逻辑晶体管、高VT器件、低VT器件、及单个SoC上的其他器件。本领域技术人员会理解，给定本文所述的实例的情况下，这些及其他器件的不同组合和排列也是可能的，以下的实例仅用于说明性目的。
在图4A中，器件400包括P型衬底402。首先对准STI，随后是P型阱（PWL）构图和注入以形成PWL410，和N型阱（NWL）构图以形成NWL412。在可替换的实施例中，可以使用与所示的相同的基础结构形成非浅阱404和模拟的输入/输出电路（I/O）406。在一个实例中，N阱=As(50-150keV，1e13-1e14)，P阱=B(10-80keV，1e13-1e14)。根据一个实施例，在STI构图前进行阱构图，这与传统的已知流程相反。此外，一些器件可以获得浅阱，其提供了额外的晶体管和电路功能。在浅阱器件的情况下，在NMOS晶体管中形成N阱，在PMOS晶体管中形成P阱。在非浅阱器件的情况下，在PMOS晶体管中形成N阱，反之亦然。
参考图4B，以在注入一个时掩蔽另一个的分离的构图注入浅阱414（浅N型阱）和416（浅P型阱）。对于非浅阱器件404以及模拟I/O器件406，这个实例没有注入浅阱。在一个实例中，SN阱=As(15-80keV，1e13-1e14)，SP阱=B(5-30keV，1e13-1e14)。在这个实例中，浅阱是可任选的，且可以使用光刻掩模来形成或阻挡，以便在同一晶片上制造两类晶体管。
在图4C中，执行N型屏蔽以在浅N阱上注入As420，并执行P型屏蔽以在浅P阱上注入Ge、B或C424。此外，执行逻辑VTP（用于P型器件的VT设置层）构图418L/S/H注入，用于设置浅N阱上的VT设置层。类似地，执行逻辑VTN（用于N型器件的VT设置层）构图422L/H/S注入，用于设置浅P阱上的VT设置层。在这个实例中以相同方式为非浅阱器件但不为模拟和I/O器件形成相同的层。在这个实例中，P型屏蔽例如可以是Ge、B和C注入中的任意一个或全部的组合（Ge（30-70keV5e13-5e14），B（0.5-2.5keV1e13-5e14），C（2-8keV5e13-5e14））。N型屏蔽例如可以是As或P中的任意一个或全部的组合（As（3k-8k2e13-2e14），P（2k-5k2e13-2e14））。NVTA可以是B和/或BF2的组合（示例性剂量，能量=B(0.1k-5k1e12-5e14)，BF2(0.5k-20keV1e12-5e14)）。PVTA可以是As和/或P的组合（示例性剂量，能量=As(1k-20k1e12-5e14)，无机磷(0.5k-12keV1e12-5e14)）。
参考图4D，针对每一类器件执行两个步骤，首先是DDC沟道EPI预清洁，随后是DDC沟道EPI沉积，以给出EPI层426。在一个实例中，可以在包括DDC和非DDC阱的整个晶片上外延沉积Si的本征层（10-80nm）。在沉积之前，可以执行表面处理的组合，以确保EPI与衬底之间的洁净分界面，从而提供最佳表面处理，以便保持EPI层中的低缺陷密度。可以仅需在希望是DDC晶体管的阱中形成屏蔽层。可以使用光刻法掩蔽其他区域。此外，可以由器件中所期望的VT来确定VTA层剂量/能量，例如以得到高VT或低VT器件，它们分别会需要多或少的剂量。
参考图4E，分别针对模拟器件的P阱和N阱形成高VT构图和注入430、432。在这个实例中，在包括DDC和非DDC阱的整个晶片上外延沉积Si的本征层（10-80nm）。在一个实例中，在沉积前，可以执行表面处理的组合，以确保EPI与衬底之间的洁净分界面。确保适当的表面处理可以是重要的，以便保持EPI层中的低缺陷密度。
参考图4F，在所有器件上执行STI构图和蚀刻及之后的STI填充/抛光和牺牲氧化以形成STI434。传统浅沟槽隔离工艺可以用于定义硅中的有效区域。实际上，需要将在STI形成期间的温度循环限制在<900℃，以便与阱堆叠体兼容。
在图4G中，执行例如诸如SiO2、高K或SiON之类的栅极电介质的形成，以便为每一个器件形成栅极介电层436。在模拟I/O器件上形成可以是高K或SiO2的厚栅极介电层436。接下来，在浅阱、非浅阱和模拟I/O器件中的每一个上执行ALD TiN沉积（在这个实例中是2－4nm）438，之后是多晶－硅沉积（这个实例中是5－10nm）440，以给出层438和440。在此，可以使用传统技术在暴露的Si区域上生长SiON的薄层，以充当栅极电介质。在一些情况下SiON可以由高K电介质代替。可以用诸如TiN的ALD中间带隙金属的薄层（2－5nm）覆盖电介质。可以用多晶-Si的薄层（5nm）覆盖金属层。在一些实施例中，可以使用简单的SiO2/多晶-Si虚设栅极堆叠体，其稍后可以由高K金属栅极在替换栅极流程中代替。
在图4H中，剥离模拟I/O器件的TiN层438。在此，随后使用光刻法暴露出诸如在其中不希望有金属栅极的诸如模拟I/O器件之类的器件。从这些区域剥离多晶-Si和TiN。借助电路上的多个器件，随后从晶片去除抗蚀剂，以便留下一些具有金属的器件和一些不具有金属的器件。
在图4I中，执行多晶-Si层沉积442，在此随后将多晶-Si沉积在整个晶片上，在一个实例中厚度是80-100nm。这之后可以是平坦化，以去除由较早的5nm多晶-Si沉积导致的任何表面形状。这之后是HM沉积，以使用传统光刻法来帮助多晶构图，给出层444。
参考图4J，对多晶进行构图以在晶片上形成栅极446A、446B（对于非浅阱器件而言是448A、448B）。在一些器件中，可以存在多晶-Si栅极。在其它器件中会存在TiN/多晶-Si堆叠体栅极。在其它器件中，会存在具有或不具有DDC阱堆叠体的浅阱，例如模拟I/O器件，栅极450A、450B。
参考图4K，为每一个器件增加尖端和间隔部（用于浅阱器件的S/D452A、452B、456A、456B和间隔部454A、454B、458A、458B；用于非浅阱器件的S/D462A、462B、466A、466B和间隔部460A、460B、464A、464B；及用于模拟I/O器件的S/D470A、470B、474A、474B和间隔部468A、468B、472A、472B）。在一个实例中，传统处理可以用于在多晶-Si上注入N和P扩展结，并形成间隔部。
参考图4L，一旦形成间隔部，就在每一个器件中使用传统技术在每一个NMOS和PMOS器件中形成深S/D结476A、476B、478A、478B。在一些情况下，可以在PMOS器件的S/D区中集成SiGe，同时可以将Si或SiCEPI集成在NMOS器件中。随后的步骤可以类似于阱建立的CMOS处理。栅极材料475和477在间隔部之间产生。根据一个实施例，通过使用这个工艺流程，可以形成在单个晶片上具有或不具有浅阱和具有多晶栅极或金属栅极堆叠体的NMOS和PMOS器件。
图5A到5J示出了具有后栅极结构的可替换实施例。在图5A中，器件500包括P型衬底502。首先对准STI，之后是P型阱（PWL）构图和注入以形成PWL504，以及N型阱（NWL）构图以形成NWL5106。类似于上面，在一个实例中，N阱=As(50-150keV,1e13-1e14)，P阱=B(10-80keV,1e13-1e14)。类似于以上讨论的，可以在STI构图前进行阱构图，这与传统已知的流程相反。
参考图5B，以分离的构图注入浅阱508（浅N型阱）和510（浅P型阱），以便在对一个进行注入时掩蔽另一个。类似于以上，在一个实例中，SN阱=As(15-80keV，1e13-1e14)，SP阱=B(5-30keV，1e13-1e14)。在这个实例中，浅阱是可任选的，可以使用光刻掩蔽来形成或阻挡，以便在同一晶片上得到两类晶体管。在浅阱器件的情况下，在NMOS晶体管中形成N阱，在PMOS晶体管中形成P阱。在非浅阱器件的情况下，在PMOS晶体管中形成N阱，反之亦然。
在图5C中，执行N型屏蔽，以在浅N阱上注入As512，执行P型屏蔽，以在浅P阱上注入Ge/B/C的组合514。此外，执行逻辑VTP（用于P型器件的VT设置层）构图516L/S/H注入，用于设置P阱上的VT设置层。类似地，执行逻辑VTN（用于N型器件的VT设置层）构图518L/H/S注入，用于设置N阱上的VT设置层。在这个实例中，P型屏蔽可以是Ge、B和C注入中的任意一个或全部的组合。对于N型屏蔽，工艺可以是As或P中的任意一个或二者的组合。仅需在希望是DDC晶体管的阱中形成屏蔽层。任选地可以使用光刻法掩蔽其他区域。此外，可以由器件中所期望的VT来确定VTA层剂量/能量，例如以便得到高VT或低VT器件，它们分别会需要较多或较少的剂量。
参考图5D，为EPI沉积执行两个步骤，首先是DDC沟道EPI预清洁，随后是DDC沟道EPI沉积，以给出EPI层520。
参考图5E，在所有器件上执行STI构图和蚀刻及之后的STI填充/抛光和牺牲氧化以形成STI522。传统的浅沟槽隔离工艺可以用于定义硅片中的工作区域。实际上，可能需要将在STI形成期间的温度循环限制在<900℃，以便与阱堆叠体兼容。
在图5F中，执行栅极电介质形成，以便为每一个相应的器件形成层524、526。可以在两个器件上形成虚设多晶硅层528，例如80nm的虚设多晶硅沉积。随后增加层530。
在图5G中，对多晶进行构图以在晶片上形成栅极532、534。这可以用HM/多晶构图和之后的多晶后蚀刻清洁处理来执行。
在图5H中，将源极/漏极结构和间隔部增加到每一个器件（S/D536、538和540、542）（间隔部542、544和546、548）。在一个实例中，传统处理可以用于在多晶-Si上注入N和P扩展结并形成间隔部。可以以用于浅N阱上的源极和漏极的第一NTP构图和注入，和用于形成浅P阱上的源极和漏极的PTP构图和注入来形成尖端。间隔部可以由预清洁和沉积以及之后的间隔部蚀刻和清洁处理来形成。
接下来，如图5I中所示，可以在掩蔽NMOS器件的情况下通过PSD构图和注入形成PMOS器件上的源极和漏极。可以在掩蔽PMOS器件的情况下通过NSD构图和注入形成NMOS器件上的源极和漏极。随后用退火工艺激活两个器件的每一个源极和漏极，为每一个器件给出源极和漏极。
同样，这个可替换的工艺称为后栅极工艺，其没有以传统工艺进行。在最后的步骤中，如图5J所示，使用几个步骤来执行栅极形成。首先是ILD沉积和抛光，之后是间隔564中的虚设栅极的去除，之后是使用掩模构图在每一个相应的器件中进行高K/金属栅极沉积和NMOS金属沉积558和PMOS金属沉积562。最后形成填充金属，之后是金属抛光。
图6A-6M示出了另一个可替换的实施例，其中使用了选择性原位EPI工艺。在图6A中，器件600中包括P型衬底602。首先对准STI，之后是P型阱（PWL）构图和注入以形成PWL604，和N型阱（NWL）构图以形成NWL606。如上所述，在可替换的实施例中，可以使用与所示相同的基本结构来形成非浅阱604和模拟输入/输出电路（I/O）。在一个实例中，N阱=As(50-150keV,1e13-1e14)，P阱=B(10-80keV,1e13-1e14)。根据一个实施例，在STI构图前进行阱构图，这与传统已知的流程相反。
参考图6B，以分离的构图注入浅阱608（浅N型阱）和610（浅P型阱），以便在注入一个时掩蔽另一个。在一个实例中，SN阱=As(15-80keV，1e13-1e14)，SP阱=B(5-30keV，1e13-1e14)。在这个实例中，浅阱是可任选的，可以使用光刻掩蔽来形成或阻挡，以便在同一晶片上得到两类晶体管。
参考图6C，执行SPWL上的氧化物层612的氧化物沉积，以暴露出SNWL608。接下来，参考图6D，沉积原位As分步掺杂EPI膜。图中所示的是两层614、616，也可以有可任选的第三层。在一个工艺中，以分步掺杂沉积单一EPI膜，其中初始层是10-30nm As=1e19，中间层是2nm到10nm As=5e18，顶层是5nm到20nm As小于或等于5e17。在另一个实例中，仅沉积两层，以使用分步掺杂形成单一EPI膜，其中首先以10-30nmAs=5e19沉积初始层，之后是顶层5nm到20nm As小于或等于5e17。在一个实例中，在STI宽度内包含小平面，即，宽度小平面<0.5×宽度STI，对于每10nm的膜厚度，小平面宽度约为7nm。
参考图6E，剥离氧化物612，在图6F中，在SNWL608上的新结构上沉积氧化物层618。
在图6G中，在与图6E的结构614、616相同或相似的构件中形成新层620、622，但代替砷，以硼对其进行掺杂。在一个工艺中，以分步掺杂沉积单一EPI膜，其中初始层是10-30nm B=1e19，中间层是2nm到10nm B=5e18，顶层是5nm到20nm B小于或等于5e17。在另一个实例中，仅沉积两层，以使用分步掺杂形成单一EPI膜，其中首先以10-30nm B=5e19沉积初始层，之后是顶层5nm到20nm B小于或等于5e17。在图6H中剥离氧化物618，在SNWL608和SPWL610上分别留下两个匹配的结构。
在图6I中，STI垫层（pad）氧化物（Lo-T热的）和氮化物沉积（Lo-TCVD）给出了新的垫层氧化物层624。实际上，可以对不同小平面进行掺杂，从而使其具有不同的氧化速率。
在图6J中，在相应的N和P阱上沉积STI光刻层626、628，掩蔽各个晶体管，从而为STI处理做准备。实际上，最小STI宽度是优选的，例如大于最大小平面宽度的两倍的STI宽度。在图6K中，蚀刻并清洁STI空间，以给出STI空间630。在图6L中，去除并清洁抗蚀剂层626、628，可以执行STI沟槽牺牲氧化物和HDP、CVD或SOD填充，以形成STI632，之后是氧化物CMP，以便在氮化物上停止。在图6M中，例如由热过氧化物湿法蚀刻去除氮化物，之后是分步高度调整（例如通过HF湿法蚀刻），以给出阱形成634。
根据一个实施例，提供了低热预算浅沟槽隔离（STI）工艺，以控制沟道和阱中掺杂剂到在先前部分中所述的器件规格的热扩散。在处理中，特定流的热预算是时间和温度的函数，如果可以相对于一个减小另一个，就可以为工艺提供直接的经济和器件益处。作为更进一步的背景，现代IC技术使用STI作为单个晶体管彼此隔离电气相互作用的手段。本文为先进的CMOS工艺提供了创新的低热预算隔离工艺。这个工艺流程消除了用于通常集成电路制造中的传统高热预算步骤。堆叠体生长/沉积的PAD氧化物代替传统高热预算（>900℃/>15min）热氧化物。新的低热预算堆叠工艺可以以超薄生长的缓冲氧化物开始。缓冲氧化物的目的是保持硅的原子地（atomically）光滑和纯净的表面，其之后是较低膜质量的低热预算沉积的氧化物。生长的缓冲氧化物的热预算可以是<600℃和<120秒。通过将原子地纯净的缓冲氧化物的厚度减小到小于2nm，来将其总热预算保持为低。缓冲氧化物可以是氯化氧化物，作为从引入的晶片的表面去除金属杂质的手段。为了完成PAD氧化物的最终堆叠体以达到其约11nm的最终厚度，利用了低热预算沉积的氧化物。可以在<500℃沉积PECVD（等离子体增强化学气相沉积）或LPCVD（低压化学气相沉积）沉积的氧化物，以达到垫层氧化物的最终厚度。初始生长的缓冲氧化物也可以消耗一些引入的硅表面、缺陷和杂质。在工艺中稍后这个氧化物的随后的湿法蚀刻去除可以提供原子地光滑的硅表面，以用于栅极电介质形成的目的。这个硅的顶表面还充当用于NMOS和PMOS器件二者的CMOS器件的沟道。可以以垂直扩散炉中的快速蒸汽氧化来使用可替换的低热预算垫层氧化。
同样，根据一个实施例，为低热预算处理提供了一工艺。隔离氮化物在垫层氧化物处理之后。隔离氮化物可以用作CMP停止层。这个氮化物的密度和厚度确定了间隙填充后的沟槽剖面、凹陷和垂悬物（over-hang）。通常在垂直扩散炉中以高温实现典型的隔离氮化物。通常形成这种氮化物族以具有200MPa到1GPa范围中的拉伸应力。可以沉积具有3GPa拉伸应力到-3GPa压应力性质的可调应力的PECVD氮化物层。可以调整诸如折射率、应力、密度和抛光速率之类的基础氮化物膜特性，以匹配给定产品所需的特定工艺条件。
所述工艺之后是STI光刻和构图。典型的45nm节点STI使用约200/200nm的间距和深度。在32nm节点，间距和深度可以减小到约150/200nm。氮化物蚀刻及之后的氧化物蚀刻暴露出硅表面，用于最终的隔离硅蚀刻。基于氯的化学反应随后可以用于蚀刻具有预期沟槽剖面的硅。硅蚀刻后，可以用湿法蚀刻化学反应来清洁硅表面的蚀刻残留物。两步骤低热预算氧化可以用于硅角落和侧面的不对称氧化，产生圆角，其可以减小得到的晶体管中的泄漏。随后由诸如高密度等离子体、旋涂式介电材料或次大气压化学气相沉积之类的氧化物间隙填充工艺来填充沟槽。可以在小于500℃（处理温度显著减小）执行沉积工艺。
需要这个沉积的间隙填充氧化物的高热预算致密化以减小蚀刻速率并硬化氧化物，用于随后的化学机械抛光步骤。这个高热预算致密化步骤由快速热处理（RTP）技术或诸如暴露于激光脉冲的其它快速热退火技术来代替。可以优化激光的频率和脉冲范围，以便或者使得间隙填充氧化物的热吸收最大，或者使得周围的硅的吸收最大。周围的硅随后将热传递到沟槽中的相邻的间隙填充氧化物。这个过程之后是化学机械抛光，利用氮化物作为蚀刻停止层，之后是氧化物的干法或受控湿法蚀刻，以减小蚀刻速率。为了控制沉积的间隙填充氧化物的湿法蚀刻速率，选择化学反应以使得蚀刻速率最小，其中首先通过在诸如NH3的氮化剂气体或诸如N2O的双氮化/氧化气体助剂中使氧化物氮化。氮化的间隙填充氧化物的蚀刻速率显著减小，从而允许显著减小致密化步骤的热预算。
图7A-7H示出了这个可替换方案的一个实例，示出了一工艺流程，该工艺流程被配置为减小制造过程中的热预算，节省制造成本。图7A中形成器件700的过程以P+衬底702开始，之后是P衬底EPI层704，随后是缓冲氧化物层705，随后是垫层氧化物层706，最后是隔离氮化物层708。在一个实施例中，可以用P+衬底上的P-型EPI产生引入的晶片。垫层氧化物可以是约10nm的热氧化物，在约900℃、在VDF工艺中产生。垫层氧化物是缓冲氧化物，并可以是PECVD氧化物沉积的。隔离氮化物可以是约100nm的CVD氮化物，在约500℃、在VDF工艺中产生。隔离氮化物可以是PECVD隔离氮化物。
在图7B中，抗蚀剂层710沉积在隔离氮化物上。这允许层712的去除，包括隔离氮化物、垫层氧化物、P-衬底和部分P+衬底。这可以通过首先执行氮化物干法蚀刻，之后是垫层氧化物干法蚀刻，之后是硅蚀刻到特定深度来执行。根据这个实施例，层的去除导致了低于P-衬底的STI沟槽和进入部分P+衬底的沟槽，允许对与多个不同器件一起形成的DDC结构的阱结构的适当隔离。
在图7C中，结果显示准备好形成STI结构的浅沟槽714。在图7D中，侧壁制备716由高温氧化及之后的高温氮化形成，实际上一起留下了具有垫层氧化物层706的扩展的垫层氧化物层和侧壁制备层716。这个侧壁制备层的一个益处在于其在某种程度上保护了P-衬底，并且当如图7E执行浅沟槽隔离（STI）填充时，圆整了P-衬底719周围的角。这个圆角减小了得到的晶体管器件中的泄漏。在一个实例中，图7E的STI填充可以在高达32nm节点设计中由HDP压缩氧化物来执行。SACVD（亚原子化学气相沉积）拉伸氧化物后处理可以用于32nm节点设计。SOD（旋涂介电材料）可以用于32nm节点，并可以需要高温退火。在图7F中，可以执行化学机械抛光（CMP），其中由化学机械抛光减小隔离氮化物层708上的顶层720。在借助当前处理设备的应用中，如没有隔离氮化物层，层就自动停止。在图7G中，用HF垫层氧化物蚀刻工艺蚀刻掉垫层氧化物层，用磷蚀刻工艺蚀刻掉隔离氮化物。结果是P+衬底，具有P-衬底EPI并具有高质量浅沟槽隔离填充722。图7H示出了得到的结构，可以生产它以用于多个器件，诸如所示的两个局部器件，一个可能具有用于P型晶体管的P-衬底726，另一个728可以是P-衬底上的N+衬底上的P-衬底，或者是其他配置的器件并与具有STI724的另一个器件分离。
图7I和7J示出了可替换的实施例，其中STI槽隔离填充722向下到达P-衬底中，但没有向下进入P+衬底中。在诸如非DDC配置的器件的器件中，会希望获得这个结构，因为在一些器件中无需STI的较深隔离。
根据本文所述的多个实施例，可以在特定范围内获得不同的掺杂剂剖面。示出的这些范围和阐述的参数旨在作为实例，本领域技术人员会理解，本文所述和所示实施例的益处在这些范围内或附近总体上是可实现的。
实际上，设计者和制造商从数学模型和来自实际电路的样品测量中收集统计数据，以确定电路设计的阈值电压的变化。晶体管之间的电压差不匹配不管是得自于制造变化还是RDF，都确定为σVT。为了电路整体上的运行，必须考虑σVT来选择运行电压VDD。通常变化越大，σVT越高，这使得必须将运行电压VDD设置得较高，以便晶体管适当地工作。在电路中实现了多个器件的情况下，会需要将VDD设置为最高总值，以便电路适当地工作。
提供了减小了σVT的结构及其生产的方法，减小了集成电路中晶体管的阈值电压的变化范围。借助减小的σVT，可以更精确地设置VT的静态值，并且甚至可以响应于改变的偏置电压而改变VT的静态值。借助减小的σVT可以更精确地设置用于电路中标称相同的器件的阈值电压，从而允许器件使用较低运行电压VDD工作，并因此消耗较少的功率。此外，借助更大的改变给定晶体管或晶体管组的VT的动态余量（headroom），器件可以响应于用于特定模式的不同偏置电压而在不同模式下工作。这可以为许多器件和系统增加功能，并且在器件功率模式的精密控制有用的情况下可以尤其有益于器件。
在本文所述的多个工艺中，尽管在外延生长过程中可以注入或共沉积掺杂剂，但进一步的高温处理可以促使掺杂剂通过硅晶格扩散。形成晶体管结构所需的高温处理步骤可以导致掺杂剂原子从屏蔽层移动到先前未掺杂的沟道中，或者甚至迁移到栅极氧化物中。有本文提供的几个方法来在不同工艺流程中进行对掺杂剂扩散的预防，例如当在工艺中执行热退火过程时。
在一个方法中，可以借助注入或碳化硅（SiC）外延层的生长将碳引入到屏蔽层中。例如在退火过程中，置换碳捕获（借助逐出（kick-out）机制）诸如硼或磷的任何移动载流子。增加碳有助于防止多晶硅栅极晶体管通常会经受的高热循环期间的扩散。
已知铟与不移动的硼形成团簇。然而，这也导致硼的低掺杂剂活性。因此，用以实现高活性和低扩散的方法包括铟与硼的共注入。本文包括了几个实例，在考虑本公开内容的情况下，其他的也是可能的，包括在不同组合中共同使用的这些实例及其他工艺。在一个示例性工艺中，可以执行铟和硼的共注入，以使得他们的最高点对齐。在铟与硼的最高点之间的不同比率，连同诸如闪光和激光的退火选项一起会导致高浓度和锐剖面。在另一个实例中，可以执行铟与硼的共注入，以使得铟的最高点接近于表面，随后是硼。硼到表面的扩散将被铟减慢，同时屏蔽和VT层将实现高活性。在另一个实例中，可以执行铟与硼的共注入，以使得铟的最高点接近于衬底，随后是硼。这将防止铟扩散到衬底中，允许屏蔽层中存在高浓度。在另一个实例中，可以使用硼与碳的分子形式。
尽管碳在防止硼或其他掺杂剂的迁移中是有用的，但碳自身可以迁移到未掺杂的沟道中，增大了散射（scattering）并减小了沟道迁移率。为了防止碳扩散，以下过程可以是有用的。如果将碳和硼共注入到非晶硅中，低温退火可以用于再生长硅层。在这个低温退火过程中，碳置换地再生。这是因为当从硅上晶体开始过程时，需要使其成为非晶的或者使其非晶化，用于处理以使其不再处于结晶状态。于是在退火后必须将其设置回结晶状态或者使其再结晶。于是可以实现硅上晶体从非结晶状态的再生。借助位于晶格中的间隙位置的碳，碳将置换晶格中的硅原子。因此，碳置换地再生。
该再生导致硅间隙原子（interstitial）的大量集中。利用随后的退火，这些间隙原子迅速向表面扩散，并将硼从屏蔽区拉到沟道区。另外，借助延迟了硼扩散的逐出机制，置换的碳变为间隙原子。该间隙原子碳也向表面扩散，通常会导致沟道迁移率降低，并产生不期望的表面状态。
然而，在这个工艺实施例中，随着硼、过量的间隙原子和碳移向表面，高温退火及之后的氧化或高温氧化用以消耗移向表面的硼、碳和间隙原子浓度。氧化工艺将产生额外的间隙原子，所以该氧化层需要是较薄的（约2nm）。随后剥离氧化物，并在无污染的表面上外延生长未掺杂的硅沟道。未掺杂的EPI减少暴露于移动碳和硼，其借助氧化物生长和剥离已经从系统去除了。另外，在EPI生长后栅极氧化前可以使用类似的氧化。这个另外的氧化可以作为第一次氧化的补充或者代替第一次氧化。
在注入过程中，在硅中引入了相当大的损害。得到的间隙原子帮助硼快速地扩散。根据一个实施例，通过去除注入损害，可以消除间隙原子，允许较少的扩散和更为突变的结。实现其的两个方法是等离子体注入和掺杂旋涂玻璃。在旋涂玻璃工艺中，将高剂量的氧化硅放置在硅的表面上。对于等离子体注入，在表面上沉积高剂量的高掺杂等离子体。在此，衬底中没有渗透或沉积，没有发生注入。当退火时，在所述固溶度下引入掺杂剂，其中较高的温度导致较高的固溶度。于是可以由热退火影响掺杂剂，以便在不损害硅结构的情况下引入更多的掺杂剂。结果是以突变结实现的较高掺杂，并且极大地减小了对硅的损害。
在一个实施例中，SiGe可以用于减慢硼从屏蔽层扩散到沟道中。可以将SiGe沉积在衬底顶上。掺杂剂可以注入到衬底中，或者在SiGe层的外延生长过程中直接共沉积。Si层仍沉积为沟道。SiGe防止了从这些掺杂层到Si沟道中的扩散。
在屏蔽层与EPI层之间的分界面处可以使用C/N/Ge/Cl/F的单原子层掺杂（delta doping）。这个层用于防止掺杂剂扩散通过层。这个层还使得系统中可以扩散到器件的沟道中或析出进入栅极中的掺杂剂的量最小化。
源极/漏极和源极/漏极延伸可以引发来自DDC沟道区的形成的损害。由于多晶硅需要深注入和高温退火来防止多晶栅耗尽效应（poly depletion），经由横向分散引入到沟道区中的损害和掺杂剂可以产生从DDC沟道堆叠体到沟道中的较大扩散（借助间隙原子或共扩散效应）。由于不能牺牲多晶栅耗尽效应，就没有方法来降低注入能量/剂量或者退火标准。阻止沟道掺杂进入DDC沟道堆叠体的两个方法是使用RSD和第二间隔部。
第二个间隔部可以用于增大与SD注入和DDC沟道剂量的横向距离，以防止注入掺杂剂时对硅的损害。在SD注入后、自对准硅化（salicidation）前可以去除或不去除这个间隔部。借助在Si与DDC沟道之间增大的横向Si，横向分散效应减小。
尽管在附图中说明并示出了某些示例性实施例，但会理解，这种实施例仅是说明宽泛的发明的，而非对其进行限制，本发明不局限于所示和所述的特定构造和布置，因为本领域普通技术人员可以想到多种其他改进。因此，应在说明性意义而非限制性意义上看待说明书和附图。

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1.一种用于制造包含多个器件类型的集成电路管芯的方法。包括：
形成多个掺杂阱；
对所述多个掺杂阱中的至少一些进行二次掺杂，以形成高掺杂的屏蔽层；
在所述屏蔽层上外延生长均厚层；
对至少一些部分的所述外延生长均厚层进行掺杂，以在所述均厚层中形成阈值电压设置层；
使用浅沟槽隔离来将所述多个掺杂阱中的至少一些彼此隔离；以及
在所述均厚层上形成多个栅极堆叠体，至少一些栅极堆叠体具有第一成分并可操作以具有在所述栅极堆叠体与所述高掺杂屏蔽层之间延伸的耗尽区，其它栅极堆叠体具有第二成分，以允许多个器件类型。
2.根据权利要求1所述的方法，其中，在外延生长所述均厚层后进行：使用浅沟槽隔离来使所述多个掺杂阱中的至少一些彼此分离。
3.根据权利要求1所述的方法，其中，所述均厚层进一步包括在所述阈值电压设置层上的沟道层。
4.根据权利要求1和3所述的方法，其中，将至少一部分所述均厚层保留在所述多个栅极堆叠体下，作为实质上未掺杂的浓度小于5×1017个原子/cm3的沟道层。
5.根据权利要求1所述的方法，其中，在形成所述阈值电压设置层的处理期间所述屏蔽层中的掺杂剂向外扩散到所述均厚层内。
6.根据权利要求1所述的方法，其中，通过在掺杂剂注入期间掩蔽至少一些所述均厚层并且保持被掩蔽的均厚层实质上未掺杂来形成不同的器件类型。
7.根据权利要求1或3所述的方法，其中，通过对至少一些所述均厚层和/或沟道层进行掺杂来形成不同的器件类型。
8.根据权利要求1所述的方法，其中，对所述外延生长阈值电压设置层进行掺杂以形成阈值电压设置凹槽。
9.根据权利要求1所述的方法，其中，使用后栅极工艺形成所述多个栅极堆叠体中的至少一些。
10.根据权利要求1所述的方法，其中，通过用PAD氧化物替换热氧化物来保持低热预算。
11.一种包含多个器件类型的集成电路管芯，包括：
多个掺杂阱，至少一些掺杂阱被二次掺杂，以形成用于第一器件类型的屏蔽层，至少一些掺杂阱支持第二器件类型；
均厚层，包括位于所述第一器件类型的屏蔽层上的不同掺杂的第一沟道层和阈值电压设置层；
所述第二器件类型的掺杂阱上的第二沟道层；以及
所述第一和第二沟道层上的多个栅极堆叠体，至少一些栅极堆叠体具有第一成分，其它栅极堆叠体具有第二成分。
12.根据权利要求11所述的集成电路管芯，其中，所述第一和第二沟道层都实质上未掺杂，以在相应的多个栅极堆叠体下具有小于5×1017个原子/cm3的浓度。
13.根据权利要求11所述的集成电路管芯，其中，通过对至少一些所述均厚层和/或沟道层进行掺杂来形成不同的多个器件类型。
14.根据权利要求11所述的集成电路管芯，其中，所述阈值电压设置层与所述屏蔽层接触。
15.根据权利要求11所述的集成电路管芯，其中，选择多个器件类型以包括DDC数字逻辑器件、传统数字逻辑器件、DDC模拟器件、传统模拟器件、传统输入输出（I/O）模拟电路和系统、高VT器件和低VT器件中的至少一个。
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