TWI608594B - 具有臨界電壓設定凹口之電晶體及其製造方法 - Google Patents

具有臨界電壓設定凹口之電晶體及其製造方法 Download PDF

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TWI608594B
TWI608594B TW100121618A TW100121618A TWI608594B TW I608594 B TWI608594 B TW I608594B TW 100121618 A TW100121618 A TW 100121618A TW 100121618 A TW100121618 A TW 100121618A TW I608594 B TWI608594 B TW I608594B
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layer
undoped
channel
threshold voltage
devices
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TW100121618A
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TW201205783A (en
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露西安 席弗倫
普西卡 蘭納德
雷薩 阿加法尼
史考特Ｅ 湯普森
凱瑟琳 德維爾納夫
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三重富士通半導體股份有限公司
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Description

具有臨界電壓設定凹口之電晶體及其製造方法 相關申請案之交叉引用
本申請案主張2010年6月22日申請之美國臨時申請案第61/357,492號之權益。
發明領域
本申請案大體而言係關於半導體裝置及與半導體裝置相關聯之製造過程，且更特定言之係關於一種具有臨界電壓設定凹口之電晶體及其製造方法。
發明背景
一段時間以來，半導體工業一直使用塊體CMOS晶圓技術來製作積體電路。將晶圓分割為通常被稱為晶粒或晶片之個別區段，其中每一晶片被封裝為電子裝置。已證明塊體CMOS技術為尤其「可縮放的」，此意謂可使塊體CMOS電晶體變得越來越小，同時最佳化並重複使用現存製造過程及裝備，以便維持可接受的生產成本。在歷史上，當塊體CMOS電晶體之大小減小，該電晶體之功率消耗亦降低，從而有助於工業提供增加的電晶體密度及較低的操作功率。因此，半導體工業已能夠使塊體CMOS電晶體之功率消耗隨電晶體之大小來按比例增減，從而降低操作電晶體及該等電晶體所在之系統的成本。
然而，近年來，降低塊體CMOS電晶體之功率消耗同時減小電晶體之大小已變得越來越困難。電晶體功率消耗 直接影響晶片功率消耗，該晶片功率消耗又影響操作系統之成本，且在一些情況下影響系統之效用。舉例而言，若相同晶片面積中電晶體之數量加倍，同時每一電晶體之功率消耗保持不變或增加，則晶片之功率消耗將多於兩倍。此舉部分是由於需要冷卻所得晶片，該冷卻所得晶片亦需要更多能量。因此，此舉將使向終端使用者索取的用於操作晶片之能源成本多於兩倍。此增加的功率消耗亦可例如藉由減少行動裝置之電池壽命而大幅降低家用電子產品之效用。此亦可能有其他效應，諸如，增加熱產生及需要熱散逸、潛在地降低系統之可靠性及負面地衝擊環境。
在半導體工程師之間已出現普遍感知，連續減少塊體CMOS之功率消耗是不可行的，此係部分因為，據信當電晶體大小減小時，無法再降低電晶體之操作電壓VDD。CMOS電晶體為開啟或關閉。CMOS電晶體之狀態係由相對於電晶體之臨界電壓VT而施加於電晶體之閘極的電壓之值來決定。當電晶體切換為導通時，電晶體即消耗動態功率，該動態功率可由以下方程式表示：Pdynamic=CVDD 2f
其中VDD為提供至電晶體之操作電壓，C為電晶體切換為導通時該電晶體之負載電容，且f為電晶體所操作之頻率。當電晶體切換為截止時，電晶體則消耗靜態功率，該靜態功率可由以下方程式表示：Pstatic=IOFF VDD
其中IOFF為電晶體切換為截止時之漏電流。在歷史上， 工業已主要藉由降低操作電壓VDD來減少電晶體功率消耗，從而減少動態功率與靜態功率。
降低操作電壓VDD之能力部分有賴於要能夠準確設定臨界電壓VT，但是當電晶體尺寸減小時，該準確設定臨界電壓VT已變得越來越困難。對於使用塊體CMOS製程製得之電晶體而言，設定臨界電壓VT之主要參數中之一個參數為通道中之摻雜劑之量。影響VT之其他因素為暈輪植入、源極與汲極低摻雜延伸及通道厚度。理論上，可精確匹配電晶體VT，以使得相同晶片上之相同電晶體將具有相同VT，但是實際上，摻雜劑濃度以及佈局上之製程及統計變化意謂臨界電壓可能顯著變化。此等失配的電晶體將不會回應於相同閘極電壓而同時全部接通，且在極端情況下一些電晶體可能從未接通。更重要的是，即使當電晶體沒有有效地切換時，失配的電晶體亦會產生增加的洩漏損失，該等增加的洩漏損失會損耗電力。
對於具有100nm或更小之通道長度之電晶體而言，可將少至三十至五十個摻雜劑原子以標稱摻雜劑濃度水平定位在通道中。這比得上對於具有大於100奈米左右之通道長度之前代電晶體而言，定位在通道中適當位置處之數千或數以萬計之原子。對於奈米級電晶體而言，此等很少的摻雜劑原子之數量及佈設上之固有統計變化產生被稱為隨機摻雜劑擾動(random dopant fluctuation；RDF)之VT之可偵測變化。與製程及材料變化一起，對於具有摻雜通道之奈米級塊體CMOS電晶體而言，RDF為VT之變化之主要決定因 素(通常稱為ΣVT或σVT)，且由RDF引起之σVT之量僅在通道長度減小時增加。
本產業探尋用於具有大大降低的σVT之新穎電晶體之製程及設計。然而，諸如無摻雜通道FINFET之許多提出的解決方案將需要電晶體製程製造及佈局之大幅變化。此舉已減緩採用，因為產業界寧願避免重新設計，該等重新設計需要習知且廣泛使用之積體電路製造過程及電晶體佈局之大幅變化。此狀況對於單晶片系統(System on a Chip；SoC)或其他高度整合裝置來說尤然，該等其他高度整合裝置包括各式各樣之電路類型，諸如，類比輸入及輸出電路(I/O)、數位電路及其他類型之電路。此外，慮及此等高度整合系統上之不同類型之電路，若可改良一或更多類型之電路，且任何必需之舊有電路保持不變，則應仍然一起生產整體SoC，以避免製造過程中需要額外步驟。舉例而言，若可實現對數位電路之改良，且改良並不適用於類比電路，則將希望同時一起製造諸電路，而不添加其他處理步驟。可重新設計整個積體電路，以適應以降低的電壓電源來操作。如本文所提及，「重新設計」一詞可包括在電路製造之前適當對電晶體閘極定大小。然而，當進行重新設計嘗試時則會遭遇困難。附加製程及遮罩步驟可能複雜、昂貴且技術上有困難。
慮及與向新技術過渡相關聯之實質成本及風險，半導體及電子系統之製造商已長期探尋延長塊體CMOS使用之方式。至少部分由於當使VDD大體上降低至低於一伏特時不 能容易地控制電晶體之群組之σVT變化，連續減少塊體CMOS中之功率消耗在半導體工業中已越來越被視為不可克服的問題。
發明概要
具有低功率數位電晶體製程及結構有其實質優點，該低功率數位電晶體製程及結構容許晶粒上類比I/O電晶體甚至在低功率電晶體替代標準電晶體時保持不變。因此，希望具有電路之混合，其中一些電路改變而其他電路為未改變的舊有電路，但是其中大體上未改變製造該等電路之製程。且為減少成本並增加良率，最佳地，大體上不增加生產整體積體電路中之製造步驟之數量。
因此，此項技術中需要用於互補金氧半導體(CMOS)電晶體及積體電路之改良的結構及製造方法，且亦需要與在單個積體電路晶粒上舊有及新穎數位及類比電晶體的製造相容之電晶體製造過程。如將可見者，本文描述之各種實施例提供此等結構及製程，以解決先前技術中之缺陷並以優雅方式來解決。
本發明提供一套新穎且不同結構及方法，以減少電子裝置及系統之寬陣列中之功率消耗。可與其他裝置一起實施此等新穎且不同結構，該等其他裝置包括共用矽基體上之舊有裝置。可主要藉由重複使用現有塊體CMOS製程流程及製造技術來實施此等結構及方法中之一些，從而允許半導體工業以及更廣泛的電子工業避免向替代性技術之昂貴 且危險的切換。該等結構及方法中之一些係關於一種深空乏通道(DDC)設計，從而允許基於CMOS之裝置具有與習知塊體CMOS相比減少的σVT，且可允許在通道區域中具有摻雜劑之FET之臨界電壓VT得以更精確地設定。存在許多組配DDC之方式，以達成不同利益，且可單獨或結合DDC來使用本文提供之額外結構及方法，以產生額外利益。
本揭示案描述優於習知半導體製造處理之各種技術優點。一個技術優點在於，提供指示鑒別性凹口之摻雜劑分佈輪廓，以便能夠在精確範圍內調整VT設定。另一技術優點在於，可藉由適當選擇金屬來延伸VT設定範圍，以使得在晶粒上容納非常寬範圍的VT設定。另一技術優點包括使用主體偏壓來提供對DDC電晶體中之功率消耗之顯著動態控制。結果為能夠獨立控制VT(具有低σVT)及VDD，以使得對於給定裝置可以與VT分離之方式來調整主體偏壓。
本揭示案之某些實施例可享有此等優點中之一些、所有或無一個此類優點。根據以下圖式、描述及申請專利範圍，其他技術優點對於熟習此項技術者將易於顯而易見。
圖式簡單說明
為更徹底地理解本揭示案，參閱結合隨附圖式進行之以下描述，其中相同元件符號表示相同零件，其中： 第1圖圖示代表性SoC以及示例性剖面圖，該代表性SoC具有DDC數位電晶體、數位舊有電晶體、DDC類比電晶體、類比舊有電晶體、高VT裝置、低VT裝置及其他裝置之概要分組。
第2A圖為圖示根據不同實施例之與處理不同類比及數位裝置有關之不同製程步驟的總流程圖。
第2B圖為圖示可根據各種實施例組配之摻雜劑分佈輪廓之圖表。
第2C圖及第2D圖為圖示根據各種實施例組配之各種摻雜劑分佈輪廓之圖表。
第3圖為圖示根據不同實施例之製程步驟之電晶體製程結構的實例。
第3A圖包括根據不同實施例之裝置特徵之兩個表。
第4A圖-第4L圖為圖示積體電路製程流程之一個實施例的流程圖。
第5A圖-第5J圖為圖示積體電路製程流程之另一實施例的流程圖。
第6A圖-第6M圖為圖示積體電路製程流程之另一實施例的流程圖。
第7A圖-第7J圖為圖示積體電路製程流程之另一實施例的流程圖。
較佳實施例之詳細說明
本發明提供組配來減少電子裝置及系統之寬陣列中之功率消耗的新穎結構及方法，且可與包括數位裝置與類比裝置的各種不同組件一起製造，並且亦可與相同電路中之舊有裝置一起生產。本發明提供製程有益技術，該等技術用於在相同晶粒上將各式各樣之電晶體建置為具有精確且 寬範圍VT控制與改良的σVT。此外，本發明提供結構，該等結構可被建構在具有分別設定主體偏壓係數及VT之能力之單一SoC上。將此等兩個設定解除耦聯，便為設計者提供在單個SoC上混合及匹配很大程度上不同的電晶體裝置類型之能力。
VT之值可使用DDC結構精確地設定(具有低σVT)，且指示鑒別性凹口之新穎摻雜劑分佈輪廓能夠允許在精確範圍內調整VT設定，在一個實例中調整至約+/-0.2V。可藉由適當選擇金屬來延伸此VT設定範圍，以使得在晶粒上容納非常寬範圍的VT設定。而且，對於每一電晶體而言，有可能未必需要多個單獨遮罩步驟。在添加靜態及/或動態偏壓之準確設定的情況下，可將不同類型之電晶體建構為具有在大體上準確的範圍內之寬範圍VT。舉例而言，事實上，可將任何類型之電晶體建構為具有介於-0.9伏特與+0.9伏特之間的VT(對於1.0 VDD電晶體而言)，且可建構在相同晶粒上。
功能上，此意謂，本文描述之實施例提供廣泛適用的電晶體製程步驟，該等製程步驟允許複合的高VT及低VT或混合信號電路之具成本效益的製造。由此製程形成之電晶體很好地得到匹配及/或能夠以舊有模式或必要時以各種低功率模式運作。
可藉由重複使用現存塊體CMOS製程流程及當前基礎架構製造技術來廣泛實施此等新穎結構及方法中之一些，從而允許半導體工業以及更廣泛電子工業避免向需要製造過程及裝備之高價變化的替代性技術作昂貴且具風險的切換。可將不同電晶體設計(包括類比及數位電晶體以及舊有結構與創新結構之混合物)併入單個積體電路或單晶片系統(SoC)中，以實現改良的省電及效能利益。可於必要時達成不同功率模式，包括舊有模式或低功率模式。此外，可將此等新結構與舊有電晶體及佈局結構一起併入製程流程中，從而藉由避免額外製程步驟來降低製造商在積體電路之製程流程中併入新結構之風險。因此，存在很少或不存在併入新穎省電電晶體結構之諸如SoC之積體電路的生產費用之增加。
本發明亦提供用於在系統中(諸如在電子產品中)併入及使用本文描述之新發明的方法及結構，以由於較低功率操作而提供優於習知裝置之實質利益。此等利益包括由於冷卻器低功率系統而在系統層次有較低的功率消耗、改良的系統效能、改良的系統成本、改良的系統可製造性及/或改良的系統可靠性，可根據本文描述並說明之實施例來設計並製造該等冷卻器低功率系統。如將示範的，可有利地將此等新發明用於各式各樣之電子系統中以及各種其他電子裝置中，該等電子系統包括消費者裝置，諸如個人電腦、行動電話、電視、數位音樂播放機、機上盒、膝上型及掌上型計算裝置、電子書閱讀機、數位攝影機、GPS系統、平板顯示器、攜帶型資料儲存裝置及輸入板。在一些實施中，總體上，電晶體及積體電路可大大地增強電子系統之操作，且因此增強商業適合性。在一些實施例中，創新電晶體、積體電路及如本文所描述含有它們之系統亦可能夠實現比替代性方法更環保之實施。
此等及其他利益提供數位電路之改進，該改進滿足設計者、生產者及消費者之許多需要。此等利益可提供由賦能積體電路之連續及進一步改進之新穎結構組成之系統，從而產生具有改良效能之裝置及系統。本文將參酌電晶體、積體電路、電子系統及相關方法來描述實施例及實例，且該等實施例及實例將突顯出此等新穎結構及方法在各種水準之製造過程及包括至電子產品之終端使用者的商業鏈下提供之特徵及利益。將此等實例中固有之概念應用於生產積體電路及電子系統之結構及方法將證明為可擴大的。因此，將理解，本發明之精神及範疇不限於此等實施例及實例，而僅由本文中及相關且共同讓渡之申請案中之隨附申請專利範圍來限制。
在一個實施例中，提供新穎奈米级場效電晶體(FET)結構，與具有相同通道長度之習知摻雜通道裝置相比，該FET結構具有精確受控之臨界電壓。在此方面，精確受控之臨界電壓包括設定並可能調整VT值之能力，該VT值提供σVT之顯著改良或减少。與習知裝置相比，此結構及製作該結構之方法可允許具有低操作電壓之FET電晶體。一個實施例包括奈米級FET結構，該奈米級FET結構可操作以具有空乏區或區域(亦即深空乏通道(DDC))，該空乏區或區域自閘極延伸至以低於閘極之深度而設定之高度摻雜的遮罩層。在一個實施例中，與在閘極下方以至少閘極長度之距離而定位之高濃度遮罩區域相比，接近閘極之通道區域為大體上無摻雜的。此舉提供與高度摻雜的遮罩區域或層成對之大體上無摻雜通道區域或層(小於5×1017原子/立方公分之濃度，且通常形成為磊晶生長矽層)。同時，在操作中，此等結構作用以界定深空乏區或區域，當將近似等於或大於臨界電壓之電壓施加於閘極時，該深空乏區或區域終止發源於閘極之電場。
在某些實施例中，遮罩層係定置成避免直接與源極及汲極接觸。在某些其他實施例中，可將它形成為在多個源極/汲極/通道/遮罩區域之下延伸之薄片。遮罩區域厚度可通常在5奈米至50奈米之範圍。相對於通道、臨界電壓調整區域(若提供)及P型井，遮罩區域高度摻雜。實務上，摻雜遮罩區域，以具有介於1×1018原子/立方公分與1×1020原子/立方公分之間的濃度。在某些實施例中，可將碳、鍺或其類似物之摻雜劑抗遷移層塗覆在遮罩區域上方，以防止摻雜劑向無摻雜通道及閘極遷移。
儘管主要藉由閘極功函數、主體偏壓、通道厚度及遮罩層之深度與摻雜劑濃度之組合來設定臨界電壓，但是可能藉由選擇性地提供與遮罩區域鄰接之單獨磊晶生長矽層對臨界電壓進行小調整。此臨界電壓調整區域具有比遮罩區域之摻雜劑濃度更小之摻雜劑濃度。對於典型應用而言，摻雜臨界電壓調整區域，以具有在5×1017原子/立方公分與2×1019原子/立方公分之範圍的平均濃度。當存在時，臨界調整區域厚度可通常在2奈米厚至50奈米厚之範圍。在某些實施例中，可將碳、鍺或其類似物之摻雜劑抗遷移層塗覆在臨界電壓調整區域上方及/或下方，以防止摻雜劑遷移至通道區域中，或者替代地自遮罩區域遷移至臨界電壓調整區域中。
如將瞭解的，對於低於100 nm之邏輯裝置而言，可藉由閘極下方之遮罩層之深度來確定DDC深度(Xd)，且該DDC深度通常為閘極長度之一半(亦即LG)，可能等於閘極長度(亦即LG)或大約等於中間分數(例如3/4LG)。在一個實例中，可將DDC深度設定為大於或約等於通道長度之一半，此舉在操作中甚至在低於一伏特之低操作電壓下允許臨界電壓之精確設定。取決於特定應用之要求，不同深度可提供不同有益結果。慮及本揭示案，將理解，不同DDC深度在不同應用、不同裝置幾何形狀及特定設計之各種參數中為可能的。取決於特定應用之參數，在形成DDC電晶體中使用之不同區域厚度、摻雜劑濃度及操作條件可提供不同有益結果。
如將論述的，此等結構及方法中之一些係關於一種DDC設計，可與佈置於相同晶圓及晶粒上之單石電路中之舊有電晶體裝置一起生產該DDC設計。與具有高度摻雜通道之習知塊體CMOS相比，此DDC可容許CMOS裝置具有減少的σVT，從而允許VT之增加的可變性。此DDC設計亦可具有與習知塊體CMOS電晶體相比強大的主體效應，此舉可允許電晶體電壓臨界設定有改良的主體偏壓輔助控制。存在有許多組配DDC之方式，以達成不同利益，且可單獨或結合此DDC來使用本文提出之額外結構及方法，以產生額外利益。
與習知奈米級裝置相比，此等結構及製作該等結構之方法允許具有低操作電壓及低臨界電壓之FET電晶體。此外，DDC電晶體可經組配以允許藉助於電壓主體偏壓產生器使臨界電壓得以靜態設定。在一些實施例中，甚至可動態控制臨界電壓，從而允許電晶體漏電流大大地降低(藉由設定電壓偏壓而為低洩漏、低速操作向上調整VT)或增加(藉由為高洩漏、高速操作向下調整VT)。最終，此等結構及製作結構之方法提供設計具有FET裝置之積體電路，當電路處於操作中時可動態調整該等FET裝置。因此，可使用標稱相同結構來設計積體電路中之電晶體，且該等電晶體可經控制、經調變或規劃，以回應於不同偏壓而以不同操作電壓操作，或回應於不同偏壓及操作電壓而以不同操作模式操作。另外，此等電晶體可在製造後組配來用於電路內之不同應用。
本文參酌電晶體來描述某些實施例及實例，且該等實施例及實例突顯出此等新穎結構及方法提供電晶體之特徵及利益。然而，此等實例中固有之概念對生產積體電路之結構及方法之適用性為可擴大的，且不限於電晶體或塊體CMOS。因此，在此項技術中將理解，本發明之精神及範疇不限於此等實施例及實例或本文中及相關且共同讓渡之申請案中之隨附申請專利範圍，而是可有利地將本發明之精神及範疇應用於其他數位電路情境中。
在以下描述中，給出較佳方式中之一些方式之許多特定細節，本發明可在該等較佳方式中實施。顯而易見，可在沒有此等特定細節的情況下實施本發明。在其他實例中，沒有詳細地圖示或以示意性或方塊圖形式圖示習知的電路、組件、演算法及製程，以便不使本發明混淆在不必要的細節中難以理解。另外，在極大程度上，已省略涉及材料、工具、製程時序、電路佈局及晶粒設計之細節，由於此等細節並非為獲得本發明之徹底理解所必需，因為此等細節被認為在相關技術領域一般技術者之理解範圍內。以下描述及申請專利範圍始終使用某些術語來代表特定系統組件。類似地，將瞭解，組件可由不同名稱來代表，且本文描述不意欲區別名稱不同而非功能不同之組件。在以下論述中及在申請專利範圍中，以開放方式使用術語「包括」及「包含」，因此應將該等語詞解釋為例如意謂「包括但不限於」。
本文描述上文提及之方法及結構之各種實施例及實例。將認知到，此詳細描述僅為說明性的，且不意欲為任何方式之限制。其他實施例將容易地浮現在受益於本揭示案之一般技術者腦海裏。將詳細參照在隨附圖式中所示之實施例。圖式及以下詳細描述將始終使用相同元件符號來代表相同或相似零件。
為了清晰，並沒有圖示並描述本文描述之實施及實施例之所有常規特徵。當然，將瞭解，在本文揭示案之任何此類實際實施之開發中，將通常進行許多實施特定決定，以便達成開發者之特定目標。此外，將瞭解，此開發努力可為複雜且耗時的，但是該開發努力對於受益於本揭示案之一般技術者將仍然僅為工程之常規任務。
又，將依據實體及功能區域或層來描述植入或以其他方式存在於半導體之基體或結晶層中以修改半導體之物理及電氣特性的原子之濃度。熟習此項技術者可將此等區域或層理解為具有濃度之特定平均值之材料之三維塊體。或者，可將此等區域或層理解為具有不同或隨空間變化之濃度的子區域或子層。此等區域或層亦可作為摻雜劑原子之小群組、大體上類似的摻雜劑原子或其類似物之區域或其他實體實施例而存在。基於此等性質之該等區域之描述不意欲限制形狀、精確位置或方位。該等描述亦不意欲將此等區域或層限制於任何特定類型或數量之製程步驟、任何特定類型或數量之層(例如，複合或單一的)、半導體沈積、蝕刻技術或使用之生長技術。此等製程可包括磊晶形成區域或原子層沈積、摻雜劑植入方法或特定豎直或橫向摻雜劑分佈輪廓，包括線性、單調增加、逆行或其他合適的空間變化摻雜劑濃度。本文包括之實施例及實例可展示所使用之特定處理技術或材料，諸如磊晶製程及下文所述且在下文諸圖中所示之其他製程。此等實例僅意欲作為說明性實例，而不意欲亦不應將此等實例理解為限制。摻雜劑分佈輪廓可具有含不同摻雜劑濃度之一或更多區域或層，且濃度之變化及區域或層如何被界定(與製程無關)可能為或可能不為可經由一些技術來檢測的，該等技術包括紅外光譜術、拉塞福背向散射(Rutherford Back Scattering；RBS)、二次離子質譜法(SIMS)或使用不同定性或定量摻雜劑濃度決定方法之其他摻雜劑分析工具。
在一個實施例中，用於低功率電路之建構區塊可被組配為具有低功率電晶體，例如，如本文提供之低功率場效電晶體，該低功率場效電晶體可在1.0伏特或更低之電壓VDD下操作。在一個實例中，電晶體可包括具有小於100奈米之閘極長度之多晶矽閘極，其中該閘極包括多晶矽層及介電層。此裝置進一步包括低摻雜磊晶通道，該低摻雜磊晶通道接觸多晶矽閘極之介電層。一高度摻雜遮罩層可以某種方式來定位，以延伸至低摻雜磊晶通道以下且在電晶體主體上方。可處理遮罩層，以減少進入低摻雜磊晶通道中之摻雜劑擴散，如下文更詳細地論述。此裝置包括源極及汲極，其中有一低摻雜磊晶通道在源極與汲極之間延伸。
在某些實施例中，亦可包括主體分接頭，以容許將主體偏壓施加於電晶體主體。主體偏壓依賴主體效應現象，以調變MOSFET之VT，且通常將該主體偏壓定量為主體效應係數。如將瞭解的，相對於源極偏壓主體之順向主體偏壓(FBB)降低VT，從而提高電晶體速度。然而，因為洩漏與VT指數相關，所以它亦導致功率使用量之大量增加。類似地，反向主體偏壓(RBB)減少洩漏，但以降低的速度及增加的延遲為代價。在某些實施例中，例如，主體偏壓之施加容許將臨界電壓VT增加至大於0.3伏特之值。
可將示意地圖示為主體偏壓產生器與電晶體主體之間的連接之主體分接頭，取決於應用而施用於個別裝置、裝置之群組或給定積體電路上之全部電路或子電路。根據此等實施例，改良的σVT允許更強大之主體偏壓係數，該更強大之主體偏壓係數又從而允許改良的VT變化。在先前技術系統中，藉由高度摻雜通道來改良主體偏壓係數，惟此舉產生寬且不良範圍之σVT。因此，此等裝置需要高臨界電壓，以使用主體偏壓中介控制來操作。根據本文描述之實施例，則可將裝置建構為具有低σVT及VT之高可調整值。此外，可分別且獨立地設定及/或調整主體偏壓及VT，從而給予設計者在單個SoC上混合及匹配不同組件之獨特能力。
此外，新穎結構及方法經組配以減少電子裝置及系統之寬陣列中之功率消耗，且可與各種不同組件(包括數位裝置與類比裝置)一起，並且亦可與相同電路中之舊有裝置一起生產。根據本文描述之實施例，提供允許大大改良的(降低的)σVT之裝置、系統及方法，且亦提供改良且強大的主體偏壓係數。因此，在強大主體偏壓的情況下寬範圍之可調整VT為可能的，從而產生以較低功率操作之較佳執行裝置及系統。為實現此舉，提供用於在相同晶粒上將各式各樣之電晶體建置為具有精確且寬範圍VT控制及改良的σVT之製程親和技術。此外，提供了可建構在具有分別設定主體偏壓係數及VT之能力之單一SoC上的結構。將此等兩個設定解除耦聯，為設計者提供在單個SoC上混合及匹配大大不同的電晶體裝置之能力。
第1圖圖示範例性SoC 100，SoC 100被組配為在矽115上具有若干不同數位電晶體組態及類比電晶體組態，可使用本文描述之方法將之併入一裝置中。根據本文論述之方法及製程，可使用塊體CMOS在矽上生產具有新穎及舊有電晶體裝置及結構之各種組合之系統。在不同實施例中，可將晶片分為一或更多區域，其中動態偏壓結構10、靜態偏壓結構12或無偏壓結構14單獨存在或以一些組合存在。在動態偏壓區段10中，例如，動態可調整裝置16可與高VT裝置18及低VT裝置20一起存在，且可能與DDC邏輯裝置21一起存在。在靜態偏壓區段12中，例如，DDC邏輯裝置102可與舊有邏輯裝置104一起存在，且亦與高VT裝置22及低VT裝置24一起存在。在不存在偏壓之區段14中，DDC類比裝置106、舊有類比裝置108及具有I/O通訊通道112之舊有I/O類比系統110可能共同存在。
在此示例性系統中，各種不同裝置可存在於單個SoC 100上，可取決於每一區段所期望之偏壓之類型而將該單個SoC分離為不同區段。因此，SoC 100可能包括DDC數位邏輯裝置102、舊有數位邏輯裝置104、DDC類比裝置106、舊有類比裝置108及舊有輸入及輸出(I/O)類比電路及系統110、高VT裝置18、22及低VT裝置20、24及可能的其他裝置，可經由共用匯流排114、線跡(未圖示)或其他互連體將該等裝置彼此互連於電路內。在通常為矽或其他類似基板的共用基板115上將此等裝置形成或以其他方式處理為塊體CMOS。
SoC 100包括至少一或更多裝置106，該一或更多裝置具有DDC橫截面分佈輪廓，此等裝置之實例在此係圖示為各種類比及數位電晶體120、130、140、150，可在基板115上共同形成所有該等電晶體。第一裝置120為數位電晶體，該數位電晶體具有閘極堆疊122及間隔物、源極及汲極124/126、深空乏通道128下方之淺井127(或電晶體之主體)及在淺溝槽隔離(STI)結構117之間延伸之遮罩層129。此分佈輪廓之意義在於，藉助於深空乏通道及遮罩層，此裝置及其他裝置之可能的低功率特性。另一數位裝置130具有閘極堆疊132及間隔物、源極及汲極134/136及深空乏通道138下方之淺井137。不同於裝置120，此數位裝置130具有遮罩層139，該遮罩層與DDC 138一起在源極與汲極134/136之間延伸。類似於裝置120，此分佈輪廓之意義在於，藉助於深空乏通道及遮罩層，此裝置及其他裝置之可能的低功率特性。
自左側算起之第三裝置及第四裝置為類比裝置，該等類比裝置在其通道區域中共用數位裝置之實體特性中之一些實體特性，從而為此等及其他類似類比裝置提供省電特徵。類比裝置140為數位電晶體，具有閘極堆疊142及間隔物、源極及汲極144/146、在深空乏通道148下方之淺井147及在STI結構117之間延伸之遮罩層149。類似於上文所述之數位裝置，此類比裝置分佈輪廓之意義在於，藉助於深空乏通道及遮罩層，此類比裝置及其他類比裝置之可能的低功率特性。另一類比裝置150具有閘極堆疊152及間隔物、源極及汲極154/156及在深空乏通道158下方之淺井157。不同於裝置140，此數位裝置150具有遮罩層159，該遮罩層與DDC 158一起在源極與汲極154/156之間延伸。類似於裝置140，此分佈輪廓之意義在於，藉助於深空乏通道及遮罩層，此裝置及其他裝置之可能的低功率特性。下文將進一步說明並描述此等及其他裝置。
在一些應用中，可能期望將偏壓施加於電晶體之主體127，諸如，第1圖中所示之偏壓源160。根據一個實施例，可藉由將偏壓施加於主體來動態設定給定裝置或多個裝置之VT。因此，再次，可將示意地圖示為偏壓源160與電晶體之間的連接之主體分接頭，取決於應用而施用於個別裝置、裝置之群組或給定積體電路上之全部電路或子電路。
根據此等實施例，改良的σVT允許更強大主體偏壓係數，該更強大主體偏壓係數則允許VT之改良的變化。此等裝置可具有高VT或低VT，且可建構為具有不同參數。此外，可將此等裝置建構在具有分別設定主體偏壓係數與VT之能力之單一SoC上。此外，將此等兩個設定解除耦聯，為設計者提供在單個SoC上混合及匹配大大不同的電晶體裝置之能力。因此，可調整並匹配諸如長通道裝置及短通道裝置之不同裝置的VT設定，以建立不同裝置之間的功率協作性。實務上，與任一裝置之總VT相比，VT之調整可相對較小，例如，0.2 V。可使用其他製程對VT進行較大變化，該等其他製程諸如金屬閘極之建構、閘極功函數、選擇性EPI沈積、離子植入、退火及提供更廣泛的VT之變化之其他製程。
參閱第2圖，圖示用於為類比及數位裝置生產不同類型之DDC結構之簡要製程流程圖200。在此所示之製程在描述上意欲為通用且廣泛的，以便不使本發明概念難以理解，且下文會闡述更詳細實施例及實例。此等及其他製程步驟允許處理及製造包括DDC結構裝置及舊有裝置之積體電路，從而允許設計涵蓋具有改良的效能及降低的功率之全範圍之類比及數位裝置。
此外，在具有調整VT之能力的情況下，可匹配不同電晶體，從而允許非常不同的裝置得以生產於相同矽晶圓上。而且，可使用習知處理技術及設計規則使本新穎結構與舊有裝置一起形成。藉由分離主體偏壓係數之設定與VT之設定使得此舉成為可能。
在步驟202中，製程自井形成開始，該井形成可為根據不同實施例及實例之許多不同製程中之一個製程。如203中所指示，井形成可在淺溝槽隔離(STI)形成204之前或之後，此取決於所要的應用及結果。硼(B)、銦(I)或其他P型材料可用於P型植入，而砷(As)或磷(P)及其他N型材料可用於N型植入。對於PMOS井植入而言，可在10 keV至80 keV之範圍內且以1×1013/cm2至8×1013/cm2之濃度將P+植入物植入。可在5 keV至60 keV之範圍內且以1×1013/cm2至8×1013/cm2之濃度植入As+。對於NMOS井植入而言，可在0.5 keV至5 keV之範圍內且在1×1013/cm2至8×1013/cm2之濃度範圍內植入硼植入物B+。可在10 keV至60 keV範圍內且以1×1014/cm2至5×1014/cm2之濃度來執行鍺植入物Ge+。可在0.5 keV至5 keV之範圍且以1×1013/cm2至8×1013/cm2之濃度來執行碳植入物C+之植入。
晶圓上之一些裝置為DDC類型裝置，而其他裝置為非DDC類型裝置，一製程可包括與本文描述之製程流程相同之製程流程，其中在不需要DDC製程之某些裝置上方可選擇性地遮蔽一些植入物。
井形成202可包括Ge/B(N)、As(P)之射束線植入，繼之以磊晶(EPI)預清潔製程，且最終繼之以非選擇性的毯覆性EPI沈積，如202A中所示。或者，可使用B(N)、As(P)之電漿植入來形成井，該電漿植入繼之以EPI預清潔，此後最終繼之以非選擇性(毯覆性)EPI沈積202B。或者，井形成可包括B(N)、As(P)之固態源擴散，繼之以EPI預清潔，且最終繼之以非選擇性(毯覆性)EPI沈積202C。作為另一替代方法，井形成可簡單地包括井植入，繼之以B(N)、P(P)之原位摻雜選擇性EPI。如下文將進一步描述的，可使用想到的不同類型之裝置(包括新穎DDC結構、舊有結構、高VT結構、低VT結構、改良的σVT、標準σVT或舊有σVT)來組配井形成程序。本文描述之實施例允許數個裝置中之任一裝置組配在使用不同井結構且根據不同參數的共用基板上。
再次，可發生在井形成202之前或之後的STI形成204，可包括處於比900℃更低之温度的低温溝槽犧牲氧化物(TSOX)襯裡，如下文與第6A圖-第6H圖一起更詳細論述。
可以數個不同方式、由不同材料或由不同功函數來形成或以其他方式建構閘極堆疊206。一個選擇為多晶矽/SiON閘極堆疊206A。另一選擇為先閘極製程206B，該先閘極製程包括SiON/金屬/多晶矽及/或SiON/多晶矽，繼之以高介電常數/金屬閘極。另一選擇為後閘極製程206C，包括高介電常數/金屬閘極堆疊，其中可使用「先高介電常數後金屬閘極」流程或及「後高介電常數後金屬閘極」流程來形成該閘極堆疊。另一選擇206D為一金屬閘極，包括取決於裝置構造N(NMOS)/P(PMOS)/N(PMOS)/P(NMOS)/中間隙或在之間的任何地方之可調整範圍之功函數。在一個實例中，N具有4.05 V±200 mV之功函數(WF)，而P具有5.01 V±200 mV之WF。
接著，在步驟208中，可取決於應用而植入源極/汲極尖端，或選擇性地可不植入該等尖端。可根據需要改變尖端之尺寸，且該等尖端之尺寸將部分取決於是否使用閘極間隔物(SPCR)。在一個選擇中，在208A中可不存在尖端植入。
接著，在選擇性步驟210及212中，可在源極及汲極區域中將PMOS或NMOS EPI層形成為用於帶應變通道之效能增強器。熟習此項技術者將理解，在帶應變通道之領域裡已有寬廣大量的文件。
對於後閘極之閘極堆疊選擇而言，在步驟214中，形成後閘極模組。此舉可能僅用於後閘極製程214A。
下文將更詳細以實例來描述此等及其他特徵。
參閱第2B圖，圖示說明電晶體裝置中之不同範圍之不同通道層的圖表203。此等範圍為深度及濃度之量測，該等量測界定裝置之不同層，該等不同層包括通道、臨界電壓設定層及遮罩層。使用包括本文描述之彼等實例的各種製程在通道內形成此等不同層。深度及濃度之此等範圍界定實例之可能性之範圍，其中主體偏壓(VBB)及臨界電壓(VT)。
■　X=10-50 nm，理想為30 nm(通道)
■　Y=1-30 nm，理想為20 nm(VTA層)
■　Z=10-40 nm，理想為30 nm(遮罩層)
■　A≦5e17 at/cm3，理想為≦1e17 at/cm3
■　5e17 at/cm3≦B≦5e18 at/cm3，理想為1e18 at/cm3
■　5e18 at/cm3≦B≦1e20 at/cm3，理想為1e19 at/cm3
■　m=1-10奈米/十倍頻，理想為<5奈米/十倍頻
■　n1=1-15奈米/十倍頻，理想為<5奈米/十倍頻
■　n2=1-10奈米/十倍頻，理想為<5奈米/十倍頻
■　n3>10奈米/十倍頻，理想為>20奈米/十倍頻
實例：
假設B為5e18
當B增加至1e19時，VT增加(高達0.5 V)
當B減小至0時，VT減小(高達-0.5 V)
假設X為30 nm
當X增加至50 nm時，VT減小(高達-0.5 V)
當X減小10 nm時，VT增加(高達0.5 V)
假設C為1e19
當C增加至2e19時，主體係數增加40%
當C减小至5e19時，主體係數减小40%
假設Y為15 nm
當Y增加至30nm時，VT減小(高達-0.5V)
當Y減少至1nm時，VT增加(高達0.5V)
參閱第2C圖及第2D圖，圖示根據以上範圍組配之各種摻雜分佈輪廓。分佈輪廓220-A、220-B及220-C圖示先前技術分佈輪廓曲線，包括可在沒有EPI層的情況下執行之SSRW或逆行植入、可分別在亦沒有EPI層但僅具有外擴散的情況下形成之凸分佈輪廓及凹分佈輪廓。根據本文描述之實施例，凹口曲線圖示不同層之分佈輪廓，該等不同層界定提供唯一特性之通道區域、VT設定層及遮罩層。此等特性包括在個別電晶體中分別控制VT與VBB之能力。取決於將凹口定置在什麼地方，可達成電晶體之不同特性。在第2C圖及第2D圖中圖示不同組態220-D至220-P。實例220-D包括具有90°或更大之中間反曲點之凹口，且當形成裝置之井及通道時，可使用單個EPI層來生產該實例。反向凹口220-E具有小於90°之中間反曲，從而表示VT設定層與遮罩層之間的摻雜劑濃度之相對下降，且當形成裝置之井及通道時，可使用分層的單個EPI層或使用雙EPI層來生產該反向凹口。淺凹口220-F具有大於120°之凹口角度，從而表示與VT設定層及遮罩層相比相對較平滑之濃度，且當形成裝置之井及通道時，可使用分層的單個EPI層來生產該淺凹口。低階凹口220-G表示VT設定層中之摻雜劑之較低濃度，且當形成裝置之井及通道時，可使用單個EPI層來生產該低階凹口。與淺反向凹口相比，深反向凹口220-H表示VT設定層與遮罩層之間的濃度之較深中間下降，且當形成裝置之 井及通道時，可使用分層的單個EPI層或使用雙EPI層來生產該深反向凹口。220-J中之高階凹口圖示VT設定層中相對較高摻雜劑濃度之實例，及在遮罩層之前的趨於穩定，且當形成裝置之井及通道時，可使用單個EPI層來生產該高階凹口。高反向凹口220-K圖示VT遮罩層中相對較高的摻雜劑含量，繼之以在遮罩層之前摻雜劑含量之中間下降的實例，且當形成裝置之井及通道時，可使用分層的單個EPI層或使用雙EPI層來生產該高反向凹口。在給定上文所述之實施例情況下，其他變化為可能的，該等變化包括多個凹口分佈輪廓220-L及多個反向凹口220-M，且當形成裝置之井及通道時，可使用雙EPI層或多個EPI層來產生該多個凹口220-L，並且當形成裝置之井及通道時，可使用分層的單個EPI層或多個EPI層來產生該多個反向凹口220-M。其他變化亦為可能的，諸如，複合分佈輪廓220-N、複合反向分佈輪廓220-O、埋設通道220-P及通道分佈輪廓之其他變化，可使用單個EPI層或多個EPI層、一或更多分層EPI層及本文描述且熟習此項技術者已知以在通道之不同深度下調整摻雜劑含量之其他製程來生產該等通道分佈輪廓之其他變化。熟習此項技術者將理解，在給定本揭示案情況下，其他分佈輪廓亦為可能的。
參閱第3圖，圖示用於多種結構之各種選擇之實例300，且製程流程圖示於第4A圖-第4L圖中。選擇A 302圖示可用於例如邏輯電路、SRAM裝置或類比裝置之基線新穎電晶體結構，該基線新穎電晶體結構包括具有淺井、DDC通道及TiN/多晶矽閘極堆疊之電晶體。在一個實例中，選擇A包括具有金屬/多晶矽混合閘極堆疊之電晶體。金屬可包括TaN、TiN、TiAlN、Mo或Ni或其他金屬，其中可將所得功函數自中間隙調整至P+或N+多晶矽功函數之程度。此外，例如，可將原子層沈積(ALD)用作沈積技術。沈積之方法可選擇性地包括物理氣相沈積(PVD)或化學氣相沈積(CVD)。選擇B 304包括基線新穎電晶體結構、淺井、DDC通道及TiN/多晶矽閘極堆疊，且該選擇B進一步包括具有POR井、DDC通道及TiN/多晶矽閘極堆疊之非淺井選擇及具有POR井、DDC通道及TiN/多晶矽閘極堆疊之類比電晶體。選擇C 306包括淺井、DDC通道及POR閘極堆疊，以及具有POR井、DDC通道及TiN/多晶矽閘極堆疊之選擇性非淺井。
不同選擇提供不同裝置特性，且提供在閘極中調適N型功函數之能力，該閘極可用於PMOS類比裝置上。參閱表2，將各種裝置製成圖表以展示與NMOS及PMOS結構之相容性，且表3展示三個選擇對淺井、非淺井、舊有裝置之適用性及為每一選擇之流程添加多少個遮罩。遮罩計數隨每一電晶體組合而變化，且如表3中所示，所需要之額外遮罩可取決於哪一個選擇為合意的而少至一個或多至三個。
第4A圖-第4L圖圖示用於新穎電晶體結構之基線，該新穎電晶體結構可用於例如邏輯電路、SRAM裝置或類比裝置，該新穎電晶體結構包括具有淺井、DDC通道及TiN/多晶矽閘極堆疊之電晶體。製程以矽晶圓開始，該矽晶圓通常用來在該矽晶圓上形成多個積體電路。第4A圖-第4L圖將以矽晶圓之一系列漸進的橫截面之方式來圖示處理若干不同電路組件之一個實例。第5A圖-第5J圖及第6A圖-第6M圖將圖示替代性實施例。當製程進行時，存在不同結構之交越及移除，其中會取代或者消除結構中之一些結構。因此，將必然消除漸進圖式中之標號，因此並非在所有圖式中將自始至終均未圖示所有編號標號。此實例將圖示用於處理組件裝置之製程，該等組件裝置包括PMOS DDC邏輯電晶體、NMOS DDC邏輯電晶體、PMOS DDC類比電晶體、NMOS DDC類比電晶體、PMOS舊有邏輯電晶體、NMOS舊有邏輯電晶體、PMOS舊有類比電晶體、NMOS舊有邏輯電晶體、高VT裝置、低VT裝置及單個SoC上之其他裝置。熟習此項技術者將理解，在給定本文描述之實例情況下，此等及其他裝置之不同組合及排列為可能的，且亦將理解，以下實例僅出於說明性目的。
在第4A圖中，裝置400包括P型基板402。首先使STI對準，繼之以P型井(PWL)佈局圖樣化及植入以形成PWL 410，且佈局圖樣化N型井(NWL)以形成NWL 412。在替代性實施例中，可使用如圖所示之相同基座結構來形成非淺井404與類比及輸入/輸出電路(I/O)406。在一個實例中，N型井=As(50-150 keV,1e13-1e14)，且P型井=B(10-80 keV,1e13-1e14)。根據一個實施例，在STI佈局圖樣化之前進行井佈局圖樣化，此舉與習知已知流程相反。又，一些裝置可獲得提供附加電晶體及電路功能性之淺井。在淺井裝置之情況下，在NMOS電晶體中形成N型井，且在PMOS電晶體中形成P型井。在非淺井裝置之情況下，則在PMOS電晶體中形成N型井，及反之。
參閱第4B圖，使用單獨佈局圖樣化來植入淺井414(淺N型井)及淺井416(淺P型井)，以在植入另一井時遮蔽每一井。對於非淺井裝置404與類比及I/O裝置406而言，此實例沒有植入淺井。在一個實例中，SN井=As(15-80 keV,1e13-1e14)，且SP井=B(5-30 keV,1e13-1e14)。在此實例中，淺井為選擇性的，且可使用微影遮罩以在相同晶圓上製作兩種類型之電晶體來形成或阻擋該等淺井。
在第4C圖中，執行N型遮罩，以在淺N型井上方植入As 420，且執行P型遮罩，以在淺P型井上方植入Ge、B或C 424。又，執行邏輯VTP(用於P型裝置之VT設定層)佈局圖樣化418 L/S/H植入，以用於在淺N型井上方設定VT設定層。類似地，執行邏輯VTN(用於N型裝置之VT設定層)佈局圖樣化422 L/H/S植入，以用於在淺P型井上方設定VT設定層。在此實例中，針對非淺井裝置，而非針對類比及I/O裝置，以相同方式形成相同層。在此實例中，P型遮罩可為Ge、B及C植入物中之任一植入物或所有植入物之組合，例如，Ge(30-70 keV,5e14-1e15)、B(0.5-2.5 keV,1e13-5e14)、C(2-8 keV,5e13-5e14)。N型遮罩可為As或P中之任一植入物或所有植入物之組合，例如As(3k-8k 2e13-2e14)、P(2k-5k 2e13-2e14))。NVTA可為B及/或BF2之組合(示例性劑量，能量=B(0.1k-5k 1e12-5e14)、BF2(0.5k-20 keV 1e12-5e14))。PVTA可為As及/或P之組合(示例性劑量，能量=As(1k-20k 1e12-5e14)、磷(0.5k-12 keV 1e12-5e14))。
參閱第4D圖，為每一類型之裝置執行兩個步驟，首先DDC通道EPI預清潔，繼之以DDC通道EPI沈積，以提供EPI層426。在一個實例中，可以磊晶方式在包括DDC井及非DDC井之整個晶圓上沈積Si之本質層(10-80 nm)。在沈積之前，可執行表面處理之組合，以確保EPI與基板之間有原始介面，以提供最佳表面處理，以便維持EPI層中之低缺陷密度。可僅需要在期望有DDC電晶體之井中形成遮罩層。可使用微影術來遮蔽其他區域。又，可由裝置中所要之VT來決定VTA層劑量/能量，例如為製作高VT裝置或低VT裝置，每一個裝置將分別需要或多或少之劑量。
參閱第4E圖，分別為類比裝置之P型井及N型井形成高VT佈局圖樣化及植入物430、432。在此實例中，可以磊晶方式在包括DDC井及非DDC井之整個晶圓上沈積Si之本質層(10-80 nm)。在一個實例中，在沈積之前，可執行表面處理之組合，以確保EPI與基板之間有原始介面。確保適當表面處理以便維持EPI層中之低缺陷密度，可能是重要的。
參閱第4F圖，在所有裝置上執行STI佈局圖樣化及蝕刻，繼之以STI填充/研磨及犧牲氧化，以形成STI 434。可使用習知淺溝槽隔離製程在矽中界定活性區域。實務上，可能需要將STI形成期間之溫度循環限制為<900℃，以便與井堆疊相容。
在第4G圖中，執行諸如SiO2、高介電常數或SiON之閘極介電質形成，以形成用於每一裝置之閘極介電層436。在類比及I/O裝置上方形成厚閘極介電層436，該厚閘極介電層可為高介電常數或SiO2。接著，在淺井、非淺井及類比I/O裝置中之每一個裝置上執行ALD TiN沈積(在此實例中為2-4 nm) 438，繼之以多晶矽沈積(對於此實例為5-10 nm)440，以提供層體438及層體440。此處，可使用習知技術在經曝露Si區域上方生長SiON之薄層，以充當閘極介電質。在一些情況下，SiON可由高介電常數介電質替代。可使用諸如TiN之ALD中間隙金屬之薄層(2-5 nm)來覆蓋介電質。可使用多晶矽之薄層(5 nm)來覆蓋金屬層。在一些實施例中，可使用簡單的SiO2/多晶矽虛設閘極堆疊，該虛設閘極堆疊稍後在替代閘極流程中可由高介電常數金屬閘極替代。
在第4H圖中，將TiN層438剝離類比及I/O裝置。此處，隨後使用微影術曝露諸如類比及I/O裝置之裝置，在該等裝置中金屬閘極並非所要的。自彼等區域剝離多晶矽及TiN。在電路上具有多個裝置的情況下，接著自晶圓移除抗蝕劑，以留下具有金屬之一些裝置及沒有金屬之一些裝置。
在第4I圖中，執行多晶矽層沈積442，其中接著在整個晶圓上方沈積多晶矽，在一個實例中，沈積至80-100 nm之厚度。此舉可繼之以平坦化，以移除由較早的5 nm多晶矽沈積造成之任何構形。此後，繼之以HM沈積，以使用習知微影術來幫助多晶矽佈局圖樣化，從而提供層體444。
參閱第4J圖，佈局圖樣化多晶矽，以在晶圓上方形成閘極446A、446B(448A、448B針對非淺井裝置)。在一些裝置中，可存在多晶矽閘極。在其他裝置中，將存在TiN/多晶矽堆疊閘極。在其他裝置中，將存在帶有或沒有DDC井堆疊之淺井，諸如，類比及I/O裝置、閘極450A、450B。
參閱第4K圖，將尖端及間隔物添加至每一裝置(對於淺井裝置為S/D 452A、452B、456A、456B及間隔物454A、454B、458A、458B；對於非淺井裝置為S/D 462A、462B、466A、466B及間隔物460A、460B、464A、464B；且對於類比及I/O裝置為S/D 470A、470B、474A及474B以及間隔物468A、468B、472A、472B)。在一個實例中，可使用習知處理來植入N型及P型延伸接面，且形成多晶矽上方之間隔物。
參閱第4L圖，一旦形成間隔物，便在每一裝置中使用習知技術在每一NMOS及PMOS裝置中形成深S/D接面476A、476B、478A、478B。在一些情況下，可能在PMOS裝置之S/D區域中整合SiGe，同時可將Si或SiC EPI整合至NMOS裝置中。後續步驟可類似於已普為確立的CMOS處理。閘極材料475及477產生於間隔物之間。根據一個實施例，藉由使用此製程流程，可能形成帶有或沒有淺井且在單個晶圓上具有多晶矽閘極或金屬閘極堆疊之NMOS裝置及PMOS裝置。
第5A圖至第5J圖圖示具有後閘極組態之替代性實施例。在第5A圖中，裝置500包括P型基板502。首先使STI對準，繼之以P型井(PWL)佈局圖樣化及植入以形成PWL 504，並佈局圖樣化N型井(NWL)以形成NWL 506。類似於上文，在一個實例中，N型井=As(50-150 keV,1e13-1e14)，且P型井=B(10-80 keV,1e13-1e14)。類似於上文所述，可在STI佈局圖樣化之前進行井佈局圖樣化，此舉與習知已知流程相反。
參閱第5B圖，使用單獨佈局圖樣化來植入淺井508(淺N型井)及淺井510(淺P型井)，以在植入另一井時遮蔽每一井。類似於上文，在一個實例中，SN井=As(15-80 keV,1e13-1e14)，且SP井=B(5-30 keV,1e13-1e14)。在此實例中，淺井為選擇性的，且可使用微影遮罩來形成或阻擋該等淺井，以在相同晶圓上製作兩種類型之電晶體。在淺井裝置之情況下，在NMOS電晶體中形成N型井，且在PMOS電晶體中形成P型井。在非淺井裝置之情況下，在PMOS電晶體中形成N型井，及反之。
在第5C圖中，執行N型遮罩，以在淺N型井上方植入As 512，且執行P型遮罩，以在淺P型井上方植入Ge/B/C之組合514。又，執行邏輯VTP(用於PMOS裝置之VT設定層)佈局圖樣化516 L/S/H植入，以用於在P型井上方設定VT設定層。類似地，執行邏輯VTN(用於NMOS裝置之VT設定層)佈局圖樣化518 L/H/S植入，以用於在N型井上方設定VT設定層。在此實例中，P型遮罩可為Ge、B及C植入物中之任一植入物或所有植入物之組合。對於N型遮罩而言，製程可為As或P中之任一者或兩者之組合。可僅需要在期望有DDC電晶體之井中形成遮罩層。可使用微影術選擇性地遮蔽其他區域。又，可由裝置中所要之VT來決定VTA層劑量/能量，例如為製作高VT裝置或低VT裝置，每一個裝置將分別需要或多或少之劑量。
參閱第5D圖，為EPI沈積執行兩個步驟，首先DDC通道EPI預清潔，繼之以DDC通道EPI沈積，以提供EPI層520。
參閱第5E圖，在所有裝置上執行STI佈局圖樣化及蝕刻，繼之以STI填充/研磨及犧牲氧化，以形成STI 522。可使用習知淺溝槽隔離製程在矽中界定活性區域。實務上，在STI形成期間之溫度循環可能需要限制為<900℃，以便與井堆疊相容。
在第5F圖中，執行閘極介電質形成，以形成用於每一各別裝置之層體524、526。在兩個裝置上方形成虛設多晶矽層528，例如，達80 nm之虛設多晶矽沈積。隨後添加層體530。
在第5G圖中，佈局圖樣化多晶矽，以在晶圓上方形成閘極532、534。此舉可使用HM/多晶矽佈局圖樣化，繼之為後多晶矽蝕刻清潔製程來執行。
在第5H圖中，將源極/汲極結構及間隔物添加至每一裝置(S/D 536、538及540、542；間隔物542、544及546、548)。在一個實例中，可使用習知處理來植入N型及P型延伸接面，且形成間隔物於多晶矽上方。可使用用於淺N型井上方之源極及汲極的第一NTP佈局圖樣化及植入，及用於形成淺P型井上方之源極及汲極的PTP佈局圖樣化及植入，來形成尖端。可藉由預清潔及沈積，繼之以間隔物蝕刻及清潔製程來形成間隔物。
接著，如第5I圖中所示，可藉由PSD佈局圖樣化及植入，在NMOS裝置受遮蔽之狀況下，來形成PMOS裝置上之源極及汲極。可藉由NSD佈局圖樣化及植入，在PMOS裝置受遮蔽之狀況下，來形成NMOS裝置之源極及汲極。此後，可使用退火製程啟動兩個裝置之每一源極及汲極，以提供每一裝置源極及汲極。
再次，此替代性製程稱為後閘極製程，在習知製程中並沒有進行該後閘極製程。在最終步驟中，如第5J圖中所示，使用若干步驟來執行閘極形成。首先，有ILD沈積及研磨，繼之以空間564中之虛設閘極移除，繼之以高介電常數/金屬閘極沈積及在使用遮罩佈局圖樣化之每一各別裝置中的NMOS金屬沈積558及PMOS金屬沈積562。最終，形成填充金屬，繼之以金屬研磨。
第6A圖-第6M圖圖示另一替代性實施例，其中使用選擇性原位EPI製程。在第6A圖中，裝置600中包括P型基板602。首先使STI對準，繼之以佈局圖樣化並植入P型井(PWL)以形成PWL 604，並佈局圖樣化N型井(NWL)以形成NWL 606。如上文所論述的，在替代性實施例中，可使用如圖所示之相同基本結構來形成非淺井604及類比及輸入/輸出電路(I/O)。在一個實例中，N型井=As(50-150 keV,1e13-1e14)，且P型井=B(10-80 keV,1e13-1e14)。根據一個實施例，在STI佈局圖樣化之前進行井佈局圖樣化，此舉與習知已知流程相反。
參閱第6B圖，使用單獨佈局圖樣化來植入淺井608(淺N型井)及淺井610(淺P型井)，以在植入另一井時遮蔽每一井。在一個實例中，SN井=As(15-80 keV,1e13-1e14)，且SP井=B(5-30 keV,1e13-1e14)。在此實例中，淺井為選擇性的，且可使用微影遮罩來形成或阻擋該等淺井以在相同晶圓上製作兩種類型之電晶體。
參閱第6C圖，在SPWL上執行氧化物層612之氧化物沈積，以曝露SNWL 608。接著，參閱第6D圖，沈積原位As階梯摻雜EPI膜。圖示兩個層體614、616，且可存在選擇性第三層。在一個製程中，使用階梯摻雜來沈積單個EPI膜，其中初始層為10-30 nm之As=1e19，中間層為2 nm至10 nm之As=5e18，且頂層為5 nm至20 nm之小於或等於5e17之As。在另一實例中，僅沈積兩個層，以使用階梯摻雜藉由首先以10-30 nm之As=5e19沈積初始層，繼之以5 nm至20 nm之小於或等於5e17之As沈積頂層來形成單個EPI膜。在一個實例中，刻面被包含在STI寬度內，亦即，寬度Facet<0.5X寬度STI，且對於每10 nm之薄膜厚度而言，刻面寬度為近於7 nm。
參閱第6E圖，剝離氧化物612，且在第6F圖中，在SNWL 608上方之新結構上方沈積氧化物層618。
在第6G圖中，在與第6E圖之結構614、616相同或類似之部件中形成新層620、622，但是該層摻雜有硼而非砷。在一個製程中，使用階梯摻雜來沈積單個EPI膜，其中初始層為10-30 nm之B=1e19，中間層為2 nm至10 nm之B=5e18，且頂層為5 nm至20 nm之小於或等於5e17之B。在另一實例中，僅沈積兩個層，以使用階梯摻雜藉由首先以10-30 nm之B=5e19沈積初始層，繼之以5 nm至20 nm之小於或等於5e17之B沈積頂層來形成單個EPI膜。在第6H圖中，剝離氧化物618，從而在SNWL 608及SPWL 610上方分別留下兩個匹配結構。
在第6I圖中，STI襯墊氧化物(Lo-T熱)及氮化物沈積(Lo-T CVD)提供新襯墊氧化物層624。實務上，可摻雜不同刻面，且因此該等不同刻面具有不同氧化率。
在第6J圖中，在各別N型井及P型井上方沈積STI微影層626、628，以遮蔽單獨電晶體，為STI製程作準備。實務上，最小STI寬度為較佳的，諸如，大於最大刻面寬度之兩倍之STI寬度。在第6K圖中，蝕刻並清潔STI空間，以提供STI空間630。在第6L圖中，移除並清潔抗蝕劑層626、628，且可執行STI溝槽犧牲氧化物及HDP、CVD或SOD填充，以形成STI 632，繼之以氧化物CMP以在氮化物上停止。在第6M圖中，藉由例如熱過氧化物濕式蝕刻移除氮化物，繼之以調整階梯高度(藉由例如HF濕式蝕刻)，以提供井形成634。
根據一個實施例，向先前段落中描述之裝置規格提供低熱預算淺溝槽隔離(STI)製程，以控制摻雜劑在通道及井中之熱擴散。在處理中，特定流程之熱預算為時間及溫度之函數。若時間及溫度之中任一者可相對於另一者降低，則可對製程提供直接經濟利益及裝置利益。如背景技術進一步所述，現代IC技術使用STI作為隔離個別電晶體以避免彼此電氣互動之手段。本文為先進CMOS製程提供新穎低熱預算隔離製程。此製程流程消除典型積體電路製造中使用之傳統高熱預算步驟。堆疊生長/沈積PAD氧化物替代傳統高熱預算(>900℃/>15分鐘)熱氧化物。此新穎的低熱預算堆疊製程可自超薄生長緩衝氧化物開始。緩衝氧化物之目的在於維持矽之原子級平滑且原始的表面，因為繼之為具有較低膜品質之低熱預算沈積氧化物。生長緩衝氧化物之熱預算可為<600℃且<120秒。藉由使厚度降低至小於2 nm將原子級原始緩衝氧化物之整體熱預算保持為低的。緩衝氧化物可為作為自引入晶圓之表面去除金屬雜質之手段的氯化氧化物。為使PAD氧化物之最終堆疊完成至近於11 nm之最終厚度，使用低熱預算沈積氧化物。可沈積在<500℃之電漿增強化學氣相沈積(PECVD)或低壓化學氣相沈積(LPCVD)之沈積氧化物，以達到襯墊氧化物之最終厚度。初始生長緩衝氧化物亦可能消耗引入矽表面、缺陷及雜質中之一些。出於閘極介電質形成之目的，稍後在製程中後續濕式蝕刻移除此氧化物可提供原子級平滑的矽表面。對於NMOS裝置及PMOS裝置而言，此矽之頂表面亦充當CMOS裝置之通道。可配合豎直擴散爐中之快速蒸汽氧化一起使用替代性低熱預算襯墊氧化。
再次，根據一個實施例，為低熱預算處理提供一製程。隔離氮化物遵循襯墊氧化物處理。可將隔離氮化物用作CMP終止層。此氮化物之密度及厚度決定後間隙填充溝槽分佈輪廓、凹陷及懸突。典型的隔離氮化物通常在高溫下於豎直擴散爐中製得。通常形成此族之氮化物，以具有在200 MPa至1 GPa之範圍內的張應力。可沈積具有3 GPa張力及-3 GPa壓縮性質之可調整應力的PECVD氮化物層。可調整諸如折射率、應力、密度及研磨率之基本氮化物膜特性，以匹配給定產品需要之特定製程條件。
該製程繼之以STI微影及佈局圖樣化。典型45 nm節點STI使用近於200/200 nm之間距及深度。在32 nm節點下，可將間距及深度降低至近於150/200 nm。氮化物蝕刻繼之以氧化物蝕刻曝露矽表面，以用於最終隔離矽蝕刻。此後可使用基於氯之化學技術將矽蝕刻為具有所要的溝槽分佈輪廓。在矽蝕刻後，可使用濕式蝕刻化學技術自蝕刻殘餘物清潔矽表面。可將兩階段低熱預算氧化用於矽轉角及側壁之非對稱氧化，從而產生圓形轉角，該等圓形轉角可減少所得電晶體中之洩漏。此後，藉由諸如高密度電漿、旋塗式介電質或次大氣壓化學氣相沈積之氧化物間隙填充製程來填充溝槽。可在小於500℃下(處理溫度之顯著降低)執行沈積製程。
需要此沈積間隙填充氧化物(>900℃/>15分鐘)之高熱預算緻密化，以降低蝕刻率並為後續化學機械研磨步驟硬化此氧化物。此高熱預算緻密化步驟由快速熱處理(RTP)技術或諸如曝露於雷射脈衝之其他快速熱退火技術替代。可最佳化雷射之頻率及脈衝範圍，以配合間隙填充氧化物最大吸收熱量或周圍矽最大吸收熱量。此後，周圍矽將熱量轉移至溝槽中之相鄰間隙填充氧化物。此後，該製程繼之以化學機械研磨，使用氮化物作為蝕刻終止層，繼之以氧化物之乾燥或受控濕式蝕刻，以降低蝕刻率。為控制沈積間隙填充氧化物之濕式蝕刻率，選擇化學處理，以藉由首先在諸如NH3之氮化劑氣體或諸如N2O之雙氮化/氧化氣體劑中使氧化物氮化來使蝕刻率最小化。顯著降低氮化間隙填充氧化物之蝕刻率，從而允許緻密化步驟之熱預算顯著減少。
第7A圖-第7H圖圖示此替代性方法之一個實例，圖示經組配來減少製造過程中之熱預算，從而節約製造成本之製程流程。第7A圖中之形成裝置700之製程始於P+基板702，繼之以P-基板EPI層704，此後為緩衝氧化物層705，此後為襯墊氧化物層706，且最終為隔離氮化物層708。在一個實施例中，可與P+基板上方之P-型EPI一起生產引入晶圓。襯墊氧化物可為近於10 nm熱氧化物，該熱氧化物係在近於900℃下且在VDF製程中生產。襯墊氧化物為緩衝氧化物，且可為沈積的PECVD氧化物。隔離氮化物可為近於100 nm CVD氮化物，該氮化物係在近於500℃下且在VDF製程中生產。隔離氮化物可為PECVD隔離氮化物。
在第7B圖中，在隔離氮化物上方沈積抗蝕劑層710。此舉允許移除多個層712，包括隔離氮化物、襯墊氧化物、P-基板及P+基板之部分。此舉可藉由首先執行氮化物乾式蝕刻，繼之以襯墊氧化物乾式蝕刻，繼之以將矽蝕刻至某一深度來執行。根據此實施例，移除該等層產生在P-基板下方之STI溝槽及進入P+基板之部分的溝槽，從而允許適當隔離用於與各種不同裝置一起形成之DDC結構的井結構。
在第7C圖中，結果圖示為STI結構形成準備之淺溝槽714。在第7D圖中，藉由高溫氧化，繼之以高溫氮化來形成側壁準備716，從而與襯墊氧化物層706及側壁準備層716一起有效地留下延伸襯墊氧化物層。此側壁準備層之利益中之一個利益在於，該側壁準備層在某種程度上保護P-基板，且當如第7E圖中執行淺溝槽隔離(STI)填充時，使P-基板719周圍之轉角成圓形。此圓形轉角減少所得電晶體裝置中之洩漏。在一個實例中，可由高達32 nm節點設計中之HDP壓縮氧化物來執行第7E圖之STI填充。次原子化學氣相沈積(SACVD)抗張氧化物柱狀物可用於32 nm節點設計。旋塗式介電質(SOD)可用於32 nm節點，且可能需要高溫退火。在第7F圖中，可執行化學機械研磨(CMP)，其中藉由化學機械研磨減少隔離氮化物層708上方之頂層720。實務上，使用當前處理裝置，該層自動停止而達不到隔離氮化物層。在第7G圖中，使用HF襯墊氧化物蝕刻製程將襯墊氧化物層蝕刻掉，且使用含磷蝕刻製程將隔離氮化物蝕刻掉。結果為具有P-基板EPI且具有高品質淺溝槽隔離填充722之P+基板。第7H圖圖示可為多個裝置生產之所得結構，該等裝置諸如所示之兩個部分裝置，一個裝置可能為具有用於P型電晶體之P-基板726，而另一個為裝置728，該裝置728可為P-基板上方之N+基板上方之P-基板或其他經組配且藉由STI 724而與其他裝置分離之裝置。
第7I圖及第7J圖圖示替代性實施例，其中STI溝槽隔離填充722向下延伸進入P-基板，而沒有向下進入P+基板。在裝置中，諸如非DDC組配之裝置，此組態可能為所要的，因為在一些裝置中並不需要STI之較深隔離。
根據本文描述之各種實施例，在某些範圍內可達成不同摻雜劑分佈輪廓。此等所示之範圍及闡述之參數意欲作為實例，且熟習此項技術者將理解，本文描述並圖示之實施例之利益通常在彼等範圍附近或之內均可達到。
實務上，設計者及製造商自實際電路收集來自數學模型及樣品量測之統計資料，以決定電路設計之臨界電壓之方差。將導源於製造變化還是RDF之電晶體之間的電壓差異失配決定為σVT。為使電路作為整體來操作，鑒於σVT，必須選擇操作電壓VDD。通常方差愈大，σVT愈高，以使得必須為電晶體設定更高的操作電壓VDD，以適當地操作。使用在一電路上實施之多個裝置，可能需要將VDD設定在最高整體值處，以便適當地操作該電路。
提供減小σVT之結構及其製造方法，從而減小在積體電路上之電晶體之臨界電壓之方差的範圍。使用減小的σVT，可更精確地設定VT之靜態值，且甚至可回應於變化之偏壓而改變該靜態值。用於在電路上之標稱相同裝置之臨界電壓可使用減小的σVT更準確地設定，從而允許使用較低操作電壓VDD來操作裝置，且因此消耗較少功率。此外，藉由有為給定電晶體或電晶體之群組改變VT之更大運用空間，可對應於用於特定模式之不同偏壓而以不同模式來操作裝置。此舉可將功能性添加至許多裝置及系統，且可能尤其有益於用得到裝置功率模式之精密控制的裝置。
在本文描述之各種製程中，儘管在磊晶生長期間可植入或共沈積摻雜劑，但是進一步高溫處理可促進摻雜劑擴散穿過矽晶格。形成電晶體結構所需要之高溫製程步驟可導致摻雜劑原子自遮罩層移動至先前無摻雜通道中，乃至遷移至閘極氧化物中。本文提供若干方法，以致力於在不同製程流程中，例如當在製程中執行熱退火程序時，防止摻雜劑擴散。
在一個方法中，可經由碳化矽(SiC)磊晶層之植入或生長將碳引入至遮罩中。舉例而言，在退火期間，取代式碳截獲(經由逐出機制)諸如硼或磷之任何流動載子。添加碳有助於在多晶矽閘極電晶體通常會經歷之高熱循環期間防止擴散。
銦已知會與硼一起形成叢集，硼不可流動。然而，此亦導致硼之低摻雜劑活化。因此，達成高活化及低擴散之方法包括銦與硼之共植入。本文包括若干實例，且在給定本揭示案情況下其他實例為可能的，包括在不同組合中共同使用之此等實例及其他製程。在一個示例性製程中，可執行銦與硼之共植入，以使得銦與硼之峰值對準。銦與硼之峰值之間的不同比率及諸如閃光及雷射之退火選擇，將導致高濃度且陡的分佈輪廓。在另一實例中，可執行銦與硼之共植入，以使得銦之峰值比硼更接近於表面。銦將減緩硼擴散至表面，同時遮罩層及VT層將達成高活化。在另一實例中，可執行銦與硼之共植入，以使得銦之峰值比硼更接近於基板。此舉將防止銦擴散至基板中，從而允許高濃度存在於遮罩層中。在另一實例中，可使用分子形式之硼及碳。
儘管碳可用於防止硼或其他摻雜劑之遷移，但是碳本身可能遷移至無摻雜通道中，從而增加散射並減少通道遷移率。為防止碳擴散，可用以下程序。若將碳與硼共植入至非晶矽中，則可使用低溫退火來再生長矽層。在此低溫退火期間，碳以替代方式再生長。此是因為，當製程始於矽上之晶體時，需要使該晶體為非晶形或非晶體化，以用於處理，因此該晶體不再處於結晶狀態。接著，必須在退火之後將該晶體置放回結晶狀態中，或再結晶。此後可達成矽上之晶體自非晶形狀態再生長。在碳定位於晶格中之間隙位置的情況下，碳將取代晶格中之矽原子。因此，碳以取代方式再生長。
此再生長產生矽間隙之大濃度。使用後續退火，此等間隙迅速向表面擴散，且將硼自遮罩區域拉至通道區域中。另外，取代式碳經由逐出機制形成間隙，該逐出機制延遲硼擴散。此間隙碳亦向表面擴散，且將通常造成通道之遷移率降級並產生非所欲的表面狀態。
然而，在此製程實施例中，當硼、過量間隙及碳移動至表面時，高溫退火繼之以氧化或高溫氧化用以消耗已移動至表面之硼、碳及間隙濃度。氧化製程將產生額外間隙，因此該氧化需要為薄的(近於2 nm)。此後剝離氧化物，且無摻雜矽通道磊晶生長在無污染表面上。無摻雜EPI已減少曝露於可移動碳及硼，該可移動碳及硼係已經由氧化物生長及剝離而自系統移除。另外，在閘極氧化之前，在EPI生長之後可使用類似的氧化法。此額外氧化可補充第一道氧化或代替第一道氧化。
在植入期間，會將顯著損壞引入至矽中。所得間隙幫助硼快速擴散。根據一個實施例，藉由移除植入損壞，可消除間隙，從而允許更少的擴散及更陡峭的接面。達成此目的之兩種方法為電漿植入及摻雜旋塗式玻璃。在旋塗式玻璃製程中，將大劑量之二氧化矽置放於矽之表面上。對於電漿植入而言，在表面上沈積大劑量之高度摻雜電漿。此時，不會有滲透或沈積至基板中，沒有植入發生。當使摻雜劑退火時，摻雜劑在固體溶解度下被拉入，其中較高溫度產生較高固體溶解度。此後，可藉由熱退火來影響摻雜劑，以拉入更多摻雜劑，而不損壞矽結構。結果為達成具有陡峭接面之較高摻雜，且極大地減少對矽之損壞。
在一個實施例中，可使用SiGe來減緩硼自遮罩層擴散至通道中。可在基板之上沈積SiGe。可將摻雜劑植入基板中，或在SiGe層之磊晶生長期間直接共沈積該等摻雜劑。仍將Si層沈積為通道。SiGe防止自此等摻雜層擴散至Si通道中。
可在遮罩層與EPI層之間的介面處使用C/N/Ge/Cl/F之δ摻雜。此層用來防止摻雜劑跨越層體擴散。此層亦使系統中可擴散至裝置之通道中或分凝至閘極中之摻雜劑之量最小化。
源極/汲極及源極/汲極延伸可能因DDC通道區域之形成招致損壞。由於多晶矽需要深植入及高熱退火以防止多晶矽空乏效應，所以經由橫向離散引入至通道區域之損壞及摻雜劑可能產生自DDC通道堆疊進入通道中之大量擴散(經由間隙或共擴散效應)。因為不能犧牲多晶矽空乏效應，所以無法降低植入能量/劑量或退火準則。阻止通道摻雜到達DDC通道堆疊之兩種方法為使用RSD及二次間隔物。
可使用第二間隔物來增加距SD植入及DDC通道劑量之橫向距離，以在植入摻雜劑時防止損壞矽。在SD植入之後且在矽化金屬沈積之前，可或不移除此間隔物。在Si與DDC通道之間的橫向Si增加情況下，橫向離散之效應即減少。
儘管已描述且在隨附圖式中圖示某些示例性實施例，但是應理解，此等實施例僅說明廣義發明內容而非廣泛發明之限制，且本發明不限於所示並描述之特定構造及佈置，因為一般熟於此技者仍可想到各種其他修改。因此，本說明書及圖式應被視為是說明性意義而非限制性意義。
10．．．動態偏壓結構/動態偏壓區段
12．．．靜態偏壓結構/靜態偏壓區段
14．．．無偏壓結構/無偏壓區段
16．．．動態可調整裝置
18,22．．．高VT裝置
20,24．．．低VT裝置
21．．．DDC邏輯裝置
100．．．單晶片系統/SoC
102．．．DDC邏輯裝置/DDC數位邏輯裝置
104．．．舊有邏輯裝置/舊有數位邏輯裝置
106．．．DDC類比裝置/裝置
108．．．舊有類比裝置
110．．．舊有I/O類比系統/舊有輸入及輸出類比電路及系統
112．．．I/O通訊通道
114．．．共用匯流排
115．．．矽/共用基板/基板
117．．．淺溝槽隔離結構/STI結構
120．．．類比及數位電晶體/第一裝置/裝置
122,132,142,152,206．．．閘極堆疊
124,134,144,154．．．源極
126,136,146,156．．．汲極
127．．．淺井/主體
128,148．．．深空乏通道
129,139,149,159．．．遮罩層
130．．．類比及數位電晶體/數位裝置
137,147,157,414,416,508,510．．．淺井
138,158．．．深空乏通道/DDC
140．．．類比裝置/裝置/類比及數位電晶體
150．．．類比及數位電晶體/類比裝置/數位裝置
160．．．偏壓源
200．．．製程流程圖
202．．．步驟/井形成
202A-202C,208,108A,214．．．步驟
203．．．步驟/圖表
204．．．淺溝槽隔離形成
206A．．．多晶矽/SiON閘極堆疊
206B．．．先閘極製程
206C,214A‧‧‧後閘極製程
206D‧‧‧金屬閘極
210,212‧‧‧選擇性步驟
220-A-220-C‧‧‧分佈輪廓
220-D‧‧‧實例/組配
220-E‧‧‧反向凹口
220-F‧‧‧淺凹口
220-G‧‧‧低階凹口
220-H‧‧‧深反向凹口
220-J‧‧‧高階凹口
220-K‧‧‧高反向凹口
220-L‧‧‧多個凹口分佈輪廓
220-M‧‧‧多個反向凹口
220-N‧‧‧複合分佈輪廓
220-O‧‧‧複合反向分佈輪廓
220-P‧‧‧埋設通道/組配
300‧‧‧實例
302‧‧‧選擇A
304‧‧‧選擇B
306‧‧‧選擇C
400,500,600,700,728‧‧‧裝置
402,502,602‧‧‧P型基板
404‧‧‧非淺井/非淺井裝置
406‧‧‧類比及輸入/輸出電路/類比及I/O裝置
410,504‧‧‧PWL
412,506,606‧‧‧NWL
418‧‧‧邏輯VTP佈局圖樣化
420,512‧‧‧As
422‧‧‧邏輯VTN佈局圖樣化
424‧‧‧Ge/B/C
426,520‧‧‧EPI層
430,432‧‧‧植入物
434,522,632,724‧‧‧STI
436‧‧‧閘極介電層
438‧‧‧ALD TiN沈積/層體/TiN層
440‧‧‧多晶矽沈積/層體
442‧‧‧多晶矽層沈積
444,524,526,530,712‧‧‧層體
446A,446B,448A,448B,450A,450B,532,534‧‧‧閘極
452A,452B,456A,456B,462A,462B,466A,466B,470A,470B,474A,474B,536,538,540‧‧‧S/D
454A,454B,458A,458B,460A,460B,464A,464B,468A,468B,472A,472B,544,546,548‧‧‧間隔物
475,477‧‧‧閘極材料
476A,476B,478A,478B‧‧‧S/D接面
514‧‧‧Ge/B/C之組合
516‧‧‧邏輯VTP佈局圖樣化
518‧‧‧邏輯VTN佈局圖樣化
528‧‧‧虛設多晶矽層
542‧‧‧S/D/間隔物
558‧‧‧NMOS金屬沈積
562‧‧‧PMOS金屬沈積
564‧‧‧空間
604‧‧‧PWL/非淺井
608‧‧‧淺井/SNWL
610‧‧‧淺井/SPWL
612‧‧‧氧化物/氧化物層
614,616‧‧‧層體/結構
618‧‧‧氧化物層/氧化物
620,622‧‧‧新層
624‧‧‧新襯墊氧化物層
626,628‧‧‧STI微影層/抗蝕劑層
630‧‧‧STI空間
634‧‧‧井形成
702‧‧‧P+基板
704‧‧‧P-基板EPI層
705‧‧‧緩衝氧化物層
706‧‧‧襯墊氧化物層
708‧‧‧隔離氮化物層
710‧‧‧抗蝕劑層
714‧‧‧淺溝槽
716‧‧‧側壁準備/側壁準備層
719,726‧‧‧P-基板
720‧‧‧頂層
722‧‧‧淺溝槽隔離填充/STI溝槽隔離填充
第1圖圖示代表性SoC以及示例性剖面圖，該代表性SoC具有DDC數位電晶體、數位舊有電晶體、DDC類比電晶體、類比舊有電晶體、高VT裝置、低VT裝置及其他裝置之概要分組。
第2A圖為圖示根據不同實施例之與處理不同類比及數位裝置有關之不同製程步驟的總流程圖。
第2B圖為圖示可根據各種實施例組配之摻雜劑分佈輪廓之圖表。
第2C圖及第2D圖為圖示根據各種實施例組配之各種摻雜劑分佈輪廓之圖表。
第3圖為圖示根據不同實施例之製程步驟之電晶體製程結構的實例。
第3A圖包括根據不同實施例之裝置特徵之兩個表。
第4A圖-第4L圖為圖示積體電路製程流程之一個實施例的流程圖。
第5A圖-第5J圖為圖示積體電路製程流程之另一實施例的流程圖。
第6A圖-第6M圖為圖示積體電路製程流程之另一實施例的流程圖。
第7A圖-第7J圖為圖示積體電路製程流程之另一實施例的流程圖。
10‧‧‧動態偏壓結構/動態偏壓區段
12‧‧‧靜態偏壓結構/靜態偏壓區段
14‧‧‧無偏壓結構/無偏壓區段
16‧‧‧動態可調整裝置
18‧‧‧高VT裝置
20‧‧‧低VT裝置
21‧‧‧DDC邏輯裝置
22‧‧‧高VT裝置
24‧‧‧低VT裝置
100‧‧‧單晶片系統/SoC
102‧‧‧DDC邏輯裝置/DDC數位邏輯裝置
104‧‧‧舊有邏輯裝置/舊有數位邏輯裝置
106‧‧‧DDC類比裝置/裝置
108‧‧‧舊有類比裝置
110‧‧‧舊有I/O類比系統/舊有輸入及輸出類比電路及系統
112‧‧‧I/O通訊通道
114‧‧‧共用匯流排
115‧‧‧矽/共用基板/基板
117‧‧‧淺溝槽隔離結構/STI結構
120‧‧‧類比及數位電晶體/第一裝置/裝置
122‧‧‧閘極堆疊
124‧‧‧源極
126‧‧‧汲極
127‧‧‧淺井/主體
128‧‧‧深空乏通道
129‧‧‧遮罩層
130‧‧‧類比及數位電晶體/數位裝置
132‧‧‧閘極堆疊
134‧‧‧源極
136‧‧‧汲極
137‧‧‧淺井
138‧‧‧深空乏通道/DDC
139‧‧‧遮罩層
140‧‧‧類比裝置/裝置/類比及數位電晶體
142‧‧‧閘極堆疊
144‧‧‧源極
146‧‧‧汲極
147‧‧‧淺井
148‧‧‧深空乏通道
149‧‧‧遮罩層
150‧‧‧類比及數位電晶體/類比裝置/數位裝置
152‧‧‧閘極堆疊
154‧‧‧源極
156‧‧‧汲極
157‧‧‧淺井
158‧‧‧深空乏通道/DDC
159‧‧‧屏蔽層
160‧‧‧偏壓源

Claims (17)

  1. 一種用於製造含有多個裝置類型之積體電路晶粒之方法，包含以下步驟：形成多個摻雜井；二次摻雜該等多個摻雜井中之至少一些摻雜井，以形成高度摻雜的遮罩層；在該等遮罩層上磊晶生長一毯覆無摻雜層；摻雜該毯覆無摻雜層之至少一些部分，以在該毯覆無摻雜層中形成一臨界電壓設定層，使得該毯覆無摻雜層包括一直接在該臨界電壓設定層上之一無摻雜的通道層；使用淺溝槽隔離來使該等多個摻雜井中之至少一些摻雜井彼此隔離；以及在該毯覆無摻雜層上形成多個閘極堆疊，其中至少一些閘極堆疊具有一第一組成物且可操作以具有一空乏區，該空乏區在該等閘極堆疊與該高度摻雜的遮罩層之間延伸，且其他閘極堆疊具有一第二組成物以允許多個裝置類型，其中，該無摻雜的通道層之濃度係小於1 x 1017原子/立方公分。
  2. 如申請專利範圍第1項之方法，其中使用淺溝槽隔離來使該等多個摻雜井中之至少一些摻雜井彼此分離之步驟發生在磊晶生長該毯覆無摻雜層之步驟之後。
  3. 如申請專利範圍第1項之方法，其中該無摻雜的通道層 之濃度係小於該高度摻雜的遮罩層之濃度的1/100。
  4. 如申請專利範圍第1項之方法，其中該等遮罩層中之摻雜劑在處理期間向外擴散至該毯覆無摻雜層中，以形成該臨界電壓設定層。
  5. 如申請專利範圍第1項之方法，其中係藉由在摻雜劑植入期間遮蔽該毯覆層中之至少一些毯覆無摻雜層，保持受遮蔽的毯覆無摻雜層實質上無摻雜，來形成不同裝置類型。
  6. 如申請專利範圍第1項之方法，其中藉由摻雜該毯覆層及/或通道無摻雜層中之至少一些來形成不同裝置類型。
  7. 如申請專利範圍第1項之方法，其中該磊晶生長之臨界電壓設定層係被摻雜來形成一臨界電壓設定凹口。
  8. 如申請專利範圍第1項之方法，其中該等多個閘極堆疊中之至少一些閘極堆疊係使用一後閘極製程來形成。
  9. 如申請專利範圍第1項之方法，其中藉由以PAD氧化物替代熱氧化物來維持一低熱預算。
  10. 如申請專利範圍第1項之方法，其中該多個裝置類型包含一第一類型裝置和一第二類型裝置，其中該第一類型裝置包含直接在該臨界電壓設定層上的該無摻雜的通道層，直接在該高度摻雜的遮罩層上之該臨界電壓設定層，及在摻雜井上的該高度摻雜的遮罩層，且其中該第二類型裝置包含直接在該摻雜井上的該無摻雜的通道層。
  11. 如申請專利範圍第10項之方法，其中該第一類型裝置包 含於該無摻雜的通道層上具有一第一功函數的一第一閘極堆疊，且該第二類型裝置包含具有一第二功函數的一第二閘極堆疊，該第二功函數不同於該無摻雜的通道層上的該第一功函數。
  12. 如申請專利範圍第1項之方法，其中該第一類型裝置包含由至少該高度摻雜的遮罩層和該臨界電壓設定層之一摻雜組合之一臨界電壓設定凹口。
  13. 一種含有多個裝置類型之積體電路晶粒，包含：多個摻雜井，其中至少一些摻雜井經二次摻雜，以形成用於一第一裝置類型之遮罩層，且至少一些摻雜井支持一第二裝置類型；一毯覆無摻雜層，該毯覆無摻雜層包含一不同摻雜之第一通道層及一臨界電壓設定層，該臨界電壓設定層定置在該第一裝置類型之該等遮罩層上方，該第一通道層係直接於該臨界電壓設定層上；一第二通道層，該第二通道層直接在該第二裝置類型之摻雜井上；以及多個閘極堆疊，該等多個閘極堆疊在該第一通道層及該第二通道層上，其中至少一些閘極堆疊具有一第一組成物，且其他閘極堆疊具有一第二組成物，其中，該第一通道層為一無摻雜層，該無摻雜層之濃度係小於1 x 1017原子/立方公分。
  14. 如申請專利範圍第13項之積體電路晶粒，其中該無摻雜層之濃度係小於該遮罩層之濃度的1/100。
  15. 如申請專利範圍第13項之積體電路晶粒，其中多個不同裝置類型係藉由摻雜該毯覆無摻雜層及/或通道無摻雜層中之至少一些來形成。
  16. 如申請專利範圍第13項之積體電路晶粒，其中該臨界電壓設定層接觸該等遮罩層。
  17. 如申請專利範圍第13項之積體電路晶粒，其中多個裝置類型係選擇為包括以下裝置中之至少一個裝置：一DDC數位邏輯裝置、一舊有數位邏輯裝置、一DDC類比裝置、一舊有類比裝置、一舊有輸入及輸出(I/O)類比電路及系統、一高VT裝置及一低VT裝置。
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Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US9287879B2 (en) * 2011-06-07 2016-03-15 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
KR101891373B1 (ko) 2011-08-05 2018-08-24 엠아이이 후지쯔 세미컨덕터 리미티드 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US9660049B2 (en) 2011-11-03 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor transistor device with dopant profile
US8993424B2 (en) * 2011-11-03 2015-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor transistor device with optimized dopant profile
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US9436250B1 (en) * 2011-12-19 2016-09-06 Altera Corporation Apparatus for improving power consumption of communication circuitry and associated methods
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) * 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) * 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
JP6003363B2 (ja) 2012-08-03 2016-10-05 富士通セミコンダクター株式会社 半導体装置とその製造方法
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) * 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US8815684B2 (en) * 2012-12-07 2014-08-26 International Business Machines Corporation Bulk finFET with super steep retrograde well
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US8969932B2 (en) * 2012-12-12 2015-03-03 Globalfoundries Inc. Methods of forming a finfet semiconductor device with undoped fins
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
CN104078360B (zh) * 2013-03-28 2016-11-23 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9299702B2 (en) * 2013-09-24 2016-03-29 Samar Saha Transistor structure and method with an epitaxial layer over multiple halo implants
CN104810396B (zh) * 2014-01-23 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
US9190516B2 (en) * 2014-02-21 2015-11-17 Globalfoundries Inc. Method for a uniform compressive strain layer and device thereof
US9710006B2 (en) * 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
KR102277398B1 (ko) * 2014-09-17 2021-07-16 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9437500B1 (en) 2015-03-13 2016-09-06 Freescale Semiconductor, Inc. Method of forming supra low threshold devices
US9653164B2 (en) 2015-03-13 2017-05-16 Nxp Usa, Inc. Method for integrating non-volatile memory cells with static random access memory cells and logic transistors
US9490255B1 (en) 2015-12-01 2016-11-08 International Business Machines Corporation Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments
US9425196B1 (en) 2015-12-08 2016-08-23 International Business Machines Corporation Multiple threshold voltage FinFETs
US10205000B2 (en) * 2015-12-29 2019-02-12 Globalfoundries Singapore Pte. Ltd. Semiconductor device with improved narrow width effect and method of making thereof
US9831272B2 (en) 2016-03-31 2017-11-28 Qualcomm Incorporated Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches
US10396076B2 (en) 2017-03-21 2019-08-27 International Business Machines Corporation Structure and method for multiple threshold voltage definition in advanced CMOS device technology
US20190004816A1 (en) * 2017-06-29 2019-01-03 Dell Products L.P. Systems and methods for heterogeneous system on a chip servers
US10790272B2 (en) 2017-08-02 2020-09-29 Qualcomm Incorporated Manufacturability (DFM) cells in extreme ultra violet (EUV) technology
KR102438767B1 (ko) * 2017-12-22 2022-08-31 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 반도체소자 및 반도체소자 패키지
KR102465356B1 (ko) 2018-02-09 2022-11-10 삼성전자주식회사 반도체 소자
US11157674B2 (en) * 2019-01-31 2021-10-26 Drexel University Transistor sizing for parameter obfuscation of analog circuits
WO2021019086A1 (en) 2019-08-01 2021-02-04 Abb Power Grids Switzerland Ag OPTIMIZED RETROGRADE CHANNEL IMPLANT FOR PLANAR SiC MOSFET
KR20210156985A (ko) 2020-06-19 2021-12-28 삼성전자주식회사 일 함수 층들을 갖는 반도체 소자들
KR20210158607A (ko) 2020-06-24 2021-12-31 삼성전자주식회사 캡핑층을 포함하는 반도체 소자
KR20210158615A (ko) 2020-06-24 2021-12-31 삼성전자주식회사 게이트 라인을 포함하는 집적회로 소자
US11653504B2 (en) 2020-07-02 2023-05-16 Samsung Electronics Co., Ltd. Semiconductor memory device with selection transistors with substrate penetrating gates
US20220375977A1 (en) * 2021-05-20 2022-11-24 Omnivision Technologies, Inc. Uniform threshold voltage non-planar transistors

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675172A (en) * 1994-05-17 1997-10-07 Hitachi, Ltd. Metal-insulator-semiconductor device having reduced threshold voltage and high mobility for high speed/low-voltage operation
US6271551B1 (en) * 1995-12-15 2001-08-07 U.S. Philips Corporation Si-Ge CMOS semiconductor device
US20020119292A1 (en) * 2000-12-22 2002-08-29 Sriram Venkatasanthanam Three-dimensional flexible adhesive film structures
US20030094627A1 (en) * 2000-10-18 2003-05-22 Fumio Ootsuka Semiconductor device and a method of manufacturing the same
US20030183856A1 (en) * 2002-03-28 2003-10-02 Karsten Wieczorek Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same
US20090302383A1 (en) * 2005-11-16 2009-12-10 Martin Knaipp High-Voltage Transistor and Component Containing the Latter

Family Cites Families (473)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021835A (en) 1974-01-25 1977-05-03 Hitachi, Ltd. Semiconductor device and a method for fabricating the same
US3958266A (en) 1974-04-19 1976-05-18 Rca Corporation Deep depletion insulated gate field effect transistors
US4000504A (en) 1975-05-12 1976-12-28 Hewlett-Packard Company Deep channel MOS transistor
US4276095A (en) 1977-08-31 1981-06-30 International Business Machines Corporation Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
US4242691A (en) 1978-09-18 1980-12-30 Mitsubishi Denki Kabushiki Kaisha MOS Semiconductor device
EP0024905B1 (en) 1979-08-25 1985-01-16 Zaidan Hojin Handotai Kenkyu Shinkokai Insulated-gate field-effect transistor
US4315781A (en) 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop
JPS56155572A (en) 1980-04-30 1981-12-01 Sanyo Electric Co Ltd Insulated gate field effect type semiconductor device
US4518926A (en) 1982-12-20 1985-05-21 At&T Bell Laboratories Gate-coupled field-effect transistor pair amplifier
JPS59193066A (ja) 1983-04-15 1984-11-01 Matsushita Electric Ind Co Ltd Ｍｏｓ型半導体装置
JPS59193066U (ja) 1983-06-08 1984-12-21 三菱電機株式会社 エレベ−タの防犯テレビカメラ
US4559091A (en) 1984-06-15 1985-12-17 Regents Of The University Of California Method for producing hyperabrupt doping profiles in semiconductors
US5060234A (en) 1984-11-19 1991-10-22 Max-Planck Gesellschaft Zur Forderung Der Wissenschaften Injection laser with at least one pair of monoatomic layers of doping atoms
US4617066A (en) 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4578128A (en) 1984-12-03 1986-03-25 Ncr Corporation Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants
US4662061A (en) 1985-02-27 1987-05-05 Texas Instruments Incorporated Method for fabricating a CMOS well structure
JPH0770606B2 (ja) 1985-11-29 1995-07-31 株式会社日立製作所 半導体装置
JPS62128175A (ja) 1985-11-29 1987-06-10 Hitachi Ltd 半導体装置
GB8606748D0 (en) 1986-03-19 1986-04-23 Secr Defence Monitoring surface layer growth
US4780748A (en) 1986-06-06 1988-10-25 American Telephone & Telegraph Company, At&T Bell Laboratories Field-effect transistor having a delta-doped ohmic contact
EP0248988B1 (de) 1986-06-10 1990-10-31 Siemens Aktiengesellschaft Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
US5156990A (en) 1986-07-23 1992-10-20 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
US5923985A (en) * 1987-01-05 1999-07-13 Seiko Instruments Inc. MOS field effect transistor and its manufacturing method
DE3789894T2 (de) 1987-01-05 1994-09-08 Seiko Instr Inc MOS-Feldeffekttransistor und dessen Herstellungsmethode.
GB2206010A (en) 1987-06-08 1988-12-21 Philips Electronic Associated Differential amplifier and current sensing circuit including such an amplifier
EP0312237A3 (en) 1987-10-13 1989-10-25 AT&T Corp. Interface charge enhancement in delta-doped heterostructure
US5156989A (en) 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
US5034337A (en) 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
US4956311A (en) 1989-06-27 1990-09-11 National Semiconductor Corporation Double-diffused drain CMOS process using a counterdoping technique
US5208473A (en) 1989-11-29 1993-05-04 Mitsubishi Denki Kabushiki Kaisha Lightly doped MISFET with reduced latchup and punchthrough
JP2822547B2 (ja) 1990-03-06 1998-11-11 富士通株式会社 高電子移動度トランジスタ
KR920008834A (ko) 1990-10-09 1992-05-28 아이자와 스스무 박막 반도체 장치
JPH04186774A (ja) 1990-11-21 1992-07-03 Hitachi Ltd 半導体装置
US5166765A (en) 1991-08-26 1992-11-24 At&T Bell Laboratories Insulated gate field-effect transistor with pulse-shaped doping
KR940006711B1 (ko) 1991-09-12 1994-07-25 포항종합제철 주식회사 델타도핑 양자 우물전계 효과 트랜지스터의 제조방법
JP2851753B2 (ja) 1991-10-22 1999-01-27 三菱電機株式会社 半導体装置およびその製造方法
JPH05315598A (ja) 1992-05-08 1993-11-26 Fujitsu Ltd 半導体装置
US5374569A (en) 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
JPH06151828A (ja) 1992-10-30 1994-05-31 Toshiba Corp 半導体装置及びその製造方法
US5298763A (en) 1992-11-02 1994-03-29 Motorola, Inc. Intrinsically doped semiconductor structure and method for making
US5426279A (en) 1993-06-21 1995-06-20 Dasgupta; Sankar Heating rate regulator
US5444008A (en) 1993-09-24 1995-08-22 Vlsi Technology, Inc. High-performance punchthrough implant method for MOS/VLSI
US5625568A (en) 1993-12-22 1997-04-29 Vlsi Technology, Inc. Method and apparatus for compacting integrated circuits with standard cell architectures
DE69516767T2 (de) 1994-02-14 2000-11-23 Koninkl Philips Electronics Nv Referenzschaltung mit kontrollierter temperaturabhängigkeit
KR0144959B1 (ko) 1994-05-17 1998-07-01 김광호 반도체장치 및 제조방법
US5622880A (en) 1994-08-18 1997-04-22 Sun Microsystems, Inc. Method of making a low power, high performance junction transistor
US5889315A (en) 1994-08-18 1999-03-30 National Semiconductor Corporation Semiconductor structure having two levels of buried regions
US5818078A (en) 1994-08-29 1998-10-06 Fujitsu Limited Semiconductor device having a regrowth crystal region
US5559368A (en) 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
JP2701762B2 (ja) 1994-11-28 1998-01-21 日本電気株式会社 半導体装置及びその製造方法
EP0717435A1 (en) 1994-12-01 1996-06-19 AT&T Corp. Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby
US6153920A (en) 1994-12-01 2000-11-28 Lucent Technologies Inc. Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby
JPH08250728A (ja) 1995-03-10 1996-09-27 Sony Corp 電界効果型半導体装置及びその製造方法
US5608253A (en) 1995-03-22 1997-03-04 Advanced Micro Devices Inc. Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits
JP2780670B2 (ja) 1995-04-14 1998-07-30 日本電気株式会社 エピタキシャルチャネルｍｏｓトランジスタの製造方法
US5552332A (en) 1995-06-02 1996-09-03 Motorola, Inc. Process for fabricating a MOSFET device having reduced reverse short channel effects
US5663583A (en) 1995-06-06 1997-09-02 Hughes Aircraft Company Low-noise and power ALGaPSb/GaInAs HEMTs and pseudomorpohic HEMTs on GaAs substrate
JP3462301B2 (ja) 1995-06-16 2003-11-05 三菱電機株式会社 半導体装置及びその製造方法
US5624863A (en) 1995-07-17 1997-04-29 Micron Technology, Inc. Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate
US5754826A (en) 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
KR0172793B1 (ko) 1995-08-07 1999-02-01 김주용 반도체소자의 제조방법
JPH0973784A (ja) 1995-09-07 1997-03-18 Nec Corp 半導体装置及びその制御回路
US6127700A (en) 1995-09-12 2000-10-03 National Semiconductor Corporation Field-effect transistor having local threshold-adjust doping
US5712501A (en) 1995-10-10 1998-01-27 Motorola, Inc. Graded-channel semiconductor device
US5753555A (en) 1995-11-22 1998-05-19 Nec Corporation Method for forming semiconductor device
JP2005260264A (ja) * 1995-12-27 2005-09-22 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US5698884A (en) 1996-02-07 1997-12-16 Thunderbird Technologies, Inc. Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricating same
JP3420879B2 (ja) 1996-03-06 2003-06-30 沖電気工業株式会社 ｐＭＯＳの製造方法、及びＣＭＯＳの製造方法
JPH09270466A (ja) * 1996-04-01 1997-10-14 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH1022462A (ja) 1996-06-28 1998-01-23 Sharp Corp 半導体装置及びその製造方法
US5847419A (en) 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
US5736419A (en) 1996-11-12 1998-04-07 National Semiconductor Corporation Method of fabricating a raised source/drain MOSFET using self-aligned POCl3 for doping gate/source/drain regions
JPH10163342A (ja) 1996-12-04 1998-06-19 Sharp Corp 半導体装置
JPH10223853A (ja) 1997-02-04 1998-08-21 Mitsubishi Electric Corp 半導体装置
US5918129A (en) 1997-02-25 1999-06-29 Advanced Micro Devices, Inc. Method of channel doping using diffusion from implanted polysilicon
JPH10242153A (ja) 1997-02-26 1998-09-11 Hitachi Ltd 半導体ウエハ、半導体ウエハの製造方法、半導体装置および半導体装置の製造方法
US5936868A (en) 1997-03-06 1999-08-10 Harris Corporation Method for converting an integrated circuit design for an upgraded process
JPH10270687A (ja) 1997-03-27 1998-10-09 Mitsubishi Electric Corp 電界効果トランジスタおよびその製造方法
US5923067A (en) 1997-04-04 1999-07-13 International Business Machines Corporation 3-D CMOS-on-SOI ESD structure and method
US6060345A (en) 1997-04-21 2000-05-09 Advanced Micro Devices, Inc. Method of making NMOS and PMOS devices with reduced masking steps
US6593799B2 (en) * 1997-06-20 2003-07-15 Intel Corporation Circuit including forward body bias from supply voltage and ground nodes
US6218895B1 (en) 1997-06-20 2001-04-17 Intel Corporation Multiple well transistor circuits having forward body bias
US6218892B1 (en) 1997-06-20 2001-04-17 Intel Corporation Differential circuits employing forward body bias
US6194259B1 (en) 1997-06-27 2001-02-27 Advanced Micro Devices, Inc. Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants
US6723621B1 (en) 1997-06-30 2004-04-20 International Business Machines Corporation Abrupt delta-like doping in Si and SiGe films by UHV-CVD
US5923987A (en) 1997-06-30 1999-07-13 Sun Microsystems, Inc. Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface
US5946214A (en) 1997-07-11 1999-08-31 Advanced Micro Devices Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns
US5989963A (en) 1997-07-21 1999-11-23 Advanced Micro Devices, Inc. Method for obtaining a steep retrograde channel profile
JP3544833B2 (ja) 1997-09-18 2004-07-21 株式会社東芝 半導体装置及びその製造方法
US5856003A (en) 1997-11-17 1999-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device
US6426260B1 (en) 1997-12-02 2002-07-30 Magepower Semiconductor Corp. Switching speed improvement in DMO by implanting lightly doped region under gate
US6271070B2 (en) 1997-12-25 2001-08-07 Matsushita Electronics Corporation Method of manufacturing semiconductor device
KR100339409B1 (ko) 1998-01-14 2002-09-18 주식회사 하이닉스반도체 반도체소자및그의제조방법
US6088518A (en) 1998-01-30 2000-07-11 Aspec Technology, Inc. Method and system for porting an integrated circuit layout from a reference process to a target process
US6001695A (en) 1998-03-02 1999-12-14 Texas Instruments - Acer Incorporated Method to form ultra-short channel MOSFET with a gate-side airgap structure
US6096611A (en) 1998-03-13 2000-08-01 Texas Instruments - Acer Incorporated Method to fabricate dual threshold CMOS circuits
KR100265227B1 (ko) 1998-06-05 2000-09-15 김영환 씨모스 트랜지스터의 제조 방법
US6072217A (en) 1998-06-11 2000-06-06 Sun Microsystems, Inc. Tunable threshold SOI device using isolated well structure for back gate
US6492232B1 (en) 1998-06-15 2002-12-10 Motorola, Inc. Method of manufacturing vertical semiconductor device
US6262461B1 (en) 1998-06-22 2001-07-17 Motorola, Inc. Method and apparatus for creating a voltage threshold in a FET
US5985705A (en) 1998-06-30 1999-11-16 Lsi Logic Corporation Low threshold voltage MOS transistor and method of manufacture
KR100292818B1 (ko) 1998-07-02 2001-11-05 윤종용 모오스트랜지스터제조방법
US6320222B1 (en) 1998-09-01 2001-11-20 Micron Technology, Inc. Structure and method for reducing threshold voltage variations due to dopant fluctuations
US6066533A (en) 1998-09-29 2000-05-23 Advanced Micro Devices, Inc. MOS transistor with dual metal gate structure
US6143593A (en) 1998-09-29 2000-11-07 Conexant Systems, Inc. Elevated channel MOSFET
US20020008257A1 (en) 1998-09-30 2002-01-24 John P. Barnak Mosfet gate electrodes having performance tuned work functions and methods of making same
JP3560480B2 (ja) * 1998-10-05 2004-09-02 シャープ株式会社 スタティック・ランダム・アクセスメモリ
US6084271A (en) 1998-11-06 2000-07-04 Advanced Micro Devices, Inc. Transistor with local insulator structure
US6380019B1 (en) 1998-11-06 2002-04-30 Advanced Micro Devices, Inc. Method of manufacturing a transistor with local insulator structure
US6221724B1 (en) 1998-11-06 2001-04-24 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit having punch-through suppression
US6184112B1 (en) 1998-12-02 2001-02-06 Advanced Micro Devices, Inc. Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile
US6214654B1 (en) 1999-01-27 2001-04-10 Advanced Micro Devices, Inc. Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget
US6245618B1 (en) 1999-02-03 2001-06-12 Advanced Micro Devices, Inc. Mosfet with localized amorphous region with retrograde implantation
JP2000243958A (ja) 1999-02-24 2000-09-08 Toshiba Corp 半導体装置およびその製造方法
US6060364A (en) 1999-03-02 2000-05-09 Advanced Micro Devices, Inc. Fast Mosfet with low-doped source/drain
US7145167B1 (en) 2000-03-11 2006-12-05 International Business Machines Corporation High speed Ge channel heterostructures for field effect devices
US6928128B1 (en) 1999-05-03 2005-08-09 Rambus Inc. Clock alignment circuit having a self regulating voltage supply
US6232164B1 (en) 1999-05-24 2001-05-15 Taiwan Semiconductor Manufacturing Company Process of making CMOS device structure having an anti-SCE block implant
US6190979B1 (en) 1999-07-12 2001-02-20 International Business Machines Corporation Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
US6235597B1 (en) 1999-08-06 2001-05-22 International Business Machines Corporation Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication
US6271547B1 (en) 1999-08-06 2001-08-07 Raytheon Company Double recessed transistor with resistive layer
US6268640B1 (en) 1999-08-12 2001-07-31 International Business Machines Corporation Forming steep lateral doping distribution at source/drain junctions
US6426279B1 (en) 1999-08-18 2002-07-30 Advanced Micro Devices, Inc. Epitaxial delta doping for retrograde channel profile
US6503801B1 (en) 1999-08-18 2003-01-07 Advanced Micro Devices, Inc. Non-uniform channel profile via enhanced diffusion
US6444550B1 (en) * 1999-08-18 2002-09-03 Advanced Micro Devices, Inc. Laser tailoring retrograde channel profile in surfaces
DE19940362A1 (de) 1999-08-25 2001-04-12 Infineon Technologies Ag MOS-Transistor und Verfahren zu dessen Herstellung
US6162693A (en) 1999-09-02 2000-12-19 Micron Technology, Inc. Channel implant through gate polysilicon
US7091093B1 (en) 1999-09-17 2006-08-15 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor device having a pocket dopant diffused layer
US6506640B1 (en) 1999-09-24 2003-01-14 Advanced Micro Devices, Inc. Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through
JP3371871B2 (ja) 1999-11-16 2003-01-27 日本電気株式会社 半導体装置の製造方法
US6313489B1 (en) 1999-11-16 2001-11-06 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device
US6449749B1 (en) 1999-11-18 2002-09-10 Pdf Solutions, Inc. System and method for product yield prediction
US6541829B2 (en) 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
GB9929084D0 (en) 1999-12-08 2000-02-02 Regan Timothy J Modification of integrated circuits
US7638380B2 (en) 2000-01-05 2009-12-29 Agere Systems Inc. Method for manufacturing a laterally diffused metal oxide semiconductor device
US6633066B1 (en) 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
US6297132B1 (en) 2000-02-07 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Process to control the lateral doping profile of an implanted channel region
US6797994B1 (en) 2000-02-14 2004-09-28 Raytheon Company Double recessed transistor
US7015546B2 (en) 2000-02-23 2006-03-21 Semiconductor Research Corporation Deterministically doped field-effect devices and methods of making same
US6326666B1 (en) 2000-03-23 2001-12-04 International Business Machines Corporation DTCMOS circuit having improved speed
US6548842B1 (en) 2000-03-31 2003-04-15 National Semiconductor Corporation Field-effect transistor for alleviating short-channel effects
US6638847B1 (en) 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6319799B1 (en) 2000-05-09 2001-11-20 Board Of Regents, The University Of Texas System High mobility heterojunction transistor and method
US6461928B2 (en) 2000-05-23 2002-10-08 Texas Instruments Incorporated Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants
JP2001352057A (ja) 2000-06-09 2001-12-21 Mitsubishi Electric Corp 半導体装置、およびその製造方法
WO2002001641A1 (fr) 2000-06-27 2002-01-03 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur
DE10034942B4 (de) 2000-07-12 2004-08-05 Infineon Technologies Ag Verfahren zur Erzeugung eines Halbleitersubstrats mit vergrabener Dotierung
US6624488B1 (en) 2000-08-07 2003-09-23 Advanced Micro Devices, Inc. Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices
US6503783B1 (en) 2000-08-31 2003-01-07 Micron Technology, Inc. SOI CMOS device with reduced DIBL
US6391752B1 (en) 2000-09-12 2002-05-21 Taiwan Semiconductor Manufacturing, Co., Ltd. Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane
US7064399B2 (en) 2000-09-15 2006-06-20 Texas Instruments Incorporated Advanced CMOS using super steep retrograde wells
US6891627B1 (en) 2000-09-20 2005-05-10 Kla-Tencor Technologies Corp. Methods and systems for determining a critical dimension and overlay of a specimen
US6617217B2 (en) 2000-10-10 2003-09-09 Texas Instruments Incorpated Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride
US6448590B1 (en) 2000-10-24 2002-09-10 International Business Machines Corporation Multiple threshold voltage FET using multiple work-function gate materials
DE10061191A1 (de) 2000-12-08 2002-06-13 Ihp Gmbh Schichten in Substratscheiben
US6300177B1 (en) 2001-01-25 2001-10-09 Chartered Semiconductor Manufacturing Inc. Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials
US6852602B2 (en) 2001-01-31 2005-02-08 Matsushita Electric Industrial Co., Ltd. Semiconductor crystal film and method for preparation thereof
JP2002237575A (ja) * 2001-02-08 2002-08-23 Sharp Corp 半導体装置及びその製造方法
US6787424B1 (en) 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
US6797602B1 (en) 2001-02-09 2004-09-28 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts
US6551885B1 (en) 2001-02-09 2003-04-22 Advanced Micro Devices, Inc. Low temperature process for a thin film transistor
KR101027485B1 (ko) 2001-02-12 2011-04-06 에이에스엠 아메리카, 인코포레이티드 반도체 박막 증착을 위한 개선된 공정
US6821852B2 (en) 2001-02-13 2004-11-23 Micron Technology, Inc. Dual doped gates
KR100393216B1 (ko) 2001-02-19 2003-07-31 삼성전자주식회사 엘디디 구조를 갖는 모오스 트랜지스터의 제조방법
US6432754B1 (en) 2001-02-20 2002-08-13 International Business Machines Corporation Double SOI device with recess etch and epitaxy
US6534373B1 (en) 2001-03-26 2003-03-18 Advanced Micro Devices, Inc. MOS transistor with reduced floating body effect
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
JP2002299454A (ja) 2001-04-02 2002-10-11 Toshiba Corp 論理回路設計方法、論理回路設計装置及び論理回路マッピング方法
US6576535B2 (en) 2001-04-11 2003-06-10 Texas Instruments Incorporated Carbon doped epitaxial layer for high speed CB-CMOS
US6693333B1 (en) 2001-05-01 2004-02-17 Advanced Micro Devices, Inc. Semiconductor-on-insulator circuit with multiple work functions
US6620671B1 (en) 2001-05-01 2003-09-16 Advanced Micro Devices, Inc. Method of fabricating transistor having a single crystalline gate conductor
US6586817B1 (en) 2001-05-18 2003-07-01 Sun Microsystems, Inc. Device including a resistive path to introduce an equivalent RC circuit
US6489224B1 (en) 2001-05-31 2002-12-03 Sun Microsystems, Inc. Method for engineering the threshold voltage of a device using buried wells
US6822297B2 (en) 2001-06-07 2004-11-23 Texas Instruments Incorporated Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness
US6500739B1 (en) 2001-06-14 2002-12-31 Taiwan Semiconductor Manufacturing Company Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect
US6358806B1 (en) 2001-06-29 2002-03-19 Lsi Logic Corporation Silicon carbide CMOS channel
JP4035354B2 (ja) 2001-07-11 2008-01-23 富士通株式会社 電子回路設計方法及び装置、コンピュータプログラム及び記憶媒体
JP2003031803A (ja) * 2001-07-19 2003-01-31 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
US6444551B1 (en) 2001-07-23 2002-09-03 Taiwan Semiconductor Manufacturing Company N-type buried layer drive-in recipe to reduce pits over buried antimony layer
US6995397B2 (en) 2001-09-14 2006-02-07 Matsushita Electric Industrial Co., Ltd. Semiconductor device
EP1428262A2 (en) 2001-09-21 2004-06-16 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
AU2002341803A1 (en) 2001-09-24 2003-04-07 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6751519B1 (en) 2001-10-25 2004-06-15 Kla-Tencor Technologies Corporation Methods and systems for predicting IC chip yield
US6521470B1 (en) 2001-10-31 2003-02-18 United Microelectronics Corp. Method of measuring thickness of epitaxial layer
US20050250289A1 (en) 2002-10-30 2005-11-10 Babcock Jeffrey A Control of dopant diffusion from buried layers in bipolar integrated circuits
US6770521B2 (en) 2001-11-30 2004-08-03 Texas Instruments Incorporated Method of making multiple work function gates by implanting metals with metallic alloying additives
US6760900B2 (en) 2001-12-03 2004-07-06 Anadigics Inc. Integrated circuits with scalable design
ITTO20011129A1 (it) 2001-12-04 2003-06-04 Infm Istituto Naz Per La Fisi Metodo per la soppressione della diffusione anomala transiente di droganti in silicio.
US6849528B2 (en) 2001-12-12 2005-02-01 Texas Instruments Incorporated Fabrication of ultra shallow junctions from a solid source with fluorine implantation
US6653698B2 (en) * 2001-12-20 2003-11-25 International Business Machines Corporation Integration of dual workfunction metal gate CMOS devices
US7013359B1 (en) 2001-12-21 2006-03-14 Cypress Semiconductor Corporation High speed memory interface system and method
KR100794094B1 (ko) 2001-12-28 2008-01-10 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조 방법
US6662350B2 (en) 2002-01-28 2003-12-09 International Business Machines Corporation FinFET layout generation
US20030141033A1 (en) 2002-01-31 2003-07-31 Tht Presses Inc. Semi-solid molding method
US7919791B2 (en) 2002-03-25 2011-04-05 Cree, Inc. Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same
CN100399576C (zh) 2002-03-28 2008-07-02 先进微装置公司 于沟道区域中具有退化掺杂分布的半导体组件及用于制造该半导体组件的方法
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6957163B2 (en) 2002-04-24 2005-10-18 Yoshiyuki Ando Integrated circuits having post-silicon adjustment control
KR100410574B1 (ko) 2002-05-18 2003-12-18 주식회사 하이닉스반도체 데카보렌 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법
KR100414736B1 (ko) 2002-05-20 2004-01-13 주식회사 하이닉스반도체 반도체소자의 트랜지스터 형성방법
US6893947B2 (en) 2002-06-25 2005-05-17 Freescale Semiconductor, Inc. Advanced RF enhancement-mode FETs with improved gate properties
US6849492B2 (en) 2002-07-08 2005-02-01 Micron Technology, Inc. Method for forming standard voltage threshold and low voltage threshold MOSFET devices
US7673273B2 (en) 2002-07-08 2010-03-02 Tier Logic, Inc. MPGA products based on a prototype FPGA
US6743291B2 (en) 2002-07-09 2004-06-01 Chartered Semiconductor Manufacturing Ltd. Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth
JP4463482B2 (ja) 2002-07-11 2010-05-19 パナソニック株式会社 Ｍｉｓｆｅｔ及びその製造方法
US6869854B2 (en) 2002-07-18 2005-03-22 International Business Machines Corporation Diffused extrinsic base and method for fabrication
JP4020730B2 (ja) 2002-08-26 2007-12-12 シャープ株式会社 半導体装置およびその製造方法
KR100464935B1 (ko) 2002-09-17 2005-01-05 주식회사 하이닉스반도체 불화붕소화합물 도핑에 의한 초박형 에피채널을 갖는반도체소자의 제조 방법
JP2004119513A (ja) 2002-09-24 2004-04-15 Toshiba Corp 半導体装置及びその製造方法
US7226843B2 (en) 2002-09-30 2007-06-05 Intel Corporation Indium-boron dual halo MOSFET
US6743684B2 (en) 2002-10-11 2004-06-01 Texas Instruments Incorporated Method to produce localized halo for MOS transistor
US6864135B2 (en) 2002-10-31 2005-03-08 Freescale Semiconductor, Inc. Semiconductor fabrication process using transistor spacers of differing widths
DE10251308B4 (de) 2002-11-04 2007-01-18 Advanced Micro Devices, Inc., Sunnyvale Integrierte geschaltete Kondensatorschaltung und Verfahren
US6660605B1 (en) 2002-11-12 2003-12-09 Texas Instruments Incorporated Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss
JP3769262B2 (ja) 2002-12-20 2006-04-19 株式会社東芝 ウェーハ平坦度評価方法、その評価方法を実行するウェーハ平坦度評価装置、その評価方法を用いたウェーハの製造方法、その評価方法を用いたウェーハ品質保証方法、その評価方法を用いた半導体デバイスの製造方法、およびその評価方法によって評価されたウェーハを用いた半導体デバイスの製造方法
KR100486609B1 (ko) 2002-12-30 2005-05-03 주식회사 하이닉스반도체 이중 도핑구조의 초박형 에피채널 피모스트랜지스터 및그의 제조 방법
US7205758B1 (en) 2004-02-02 2007-04-17 Transmeta Corporation Systems and methods for adjusting threshold voltage
WO2004061898A2 (en) 2003-01-02 2004-07-22 Pdf Solutions, Inc. Yield improvement
US6963090B2 (en) 2003-01-09 2005-11-08 Freescale Semiconductor, Inc. Enhancement mode metal-oxide-semiconductor field effect transistor
KR100499159B1 (ko) 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
US20040175893A1 (en) 2003-03-07 2004-09-09 Applied Materials, Inc. Apparatuses and methods for forming a substantially facet-free epitaxial film
KR100989006B1 (ko) 2003-03-13 2010-10-20 크로스텍 캐피탈, 엘엘씨 씨모스 이미지센서의 제조방법
WO2004084310A1 (de) 2003-03-19 2004-09-30 Siced Electronics Development Gmbh & Co. Kg Halbleiteraufbau mit hoch dotiertem kanalleitungsgebiet und verfahren zur herstellung eines halbleiteraufbaus
JP2006524429A (ja) 2003-03-28 2006-10-26 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Ｎドープシリコン層のエピタキシャル成長のための方法
SE0300924D0 (sv) 2003-03-28 2003-03-28 Infineon Technologies Wireless A method to provide a triple well in an epitaxially based CMOS or BiCMOS process
US7294877B2 (en) 2003-03-28 2007-11-13 Nantero, Inc. Nanotube-on-gate FET structures and applications
AU2003236078A1 (en) 2003-04-10 2004-11-04 Fujitsu Limited Semiconductor device and its manufacturing method
JP4469139B2 (ja) 2003-04-28 2010-05-26 シャープ株式会社 化合物半導体ｆｅｔ
US7176137B2 (en) 2003-05-09 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method for multiple spacer width control
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6794235B1 (en) 2003-06-05 2004-09-21 Texas Instruments Incorporated Method of manufacturing a semiconductor device having a localized halo implant
WO2004112145A1 (ja) 2003-06-10 2004-12-23 Fujitsu Limited パンチスルー耐性を向上させた半導体集積回路装置およびその製造方法、低電圧トランジスタと高電圧トランジスタとを含む半導体集積回路装置
US6808994B1 (en) 2003-06-17 2004-10-26 Micron Technology, Inc. Transistor structures and processes for forming same
US20060273299A1 (en) 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7260562B2 (en) 2003-06-30 2007-08-21 Intel Corporation Solutions for constraint satisfaction problems requiring multiple constraints
US7036098B2 (en) 2003-06-30 2006-04-25 Sun Microsystems, Inc. On-chip signal state duration measurement and adjustment
EP1519421A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum Vzw Multiple gate semiconductor device and method for forming same
EP1647046A2 (en) 2003-07-23 2006-04-19 ASM America, Inc. DEPOSITION OF SiGE ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES
JP2007504660A (ja) 2003-09-03 2007-03-01 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ ダブルゲート電界効果トランジスタ装置を製造する方法、及びそのようなダブルゲート電界効果トランジスタ装置
US6930007B2 (en) 2003-09-15 2005-08-16 Texas Instruments Incorporated Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
JP4186774B2 (ja) 2003-09-25 2008-11-26 沖電気工業株式会社 情報抽出装置，情報抽出方法，およびプログラム
US7127687B1 (en) 2003-10-14 2006-10-24 Sun Microsystems, Inc. Method and apparatus for determining transistor sizes
US7109099B2 (en) 2003-10-17 2006-09-19 Chartered Semiconductor Manufacturing Ltd. End of range (EOR) secondary defect engineering using substitutional carbon doping
US7274076B2 (en) 2003-10-20 2007-09-25 Micron Technology, Inc. Threshold voltage adjustment for long channel transistors
US7141468B2 (en) 2003-10-27 2006-11-28 Texas Instruments Incorporated Application of different isolation schemes for logic and embedded memory
US7057216B2 (en) 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US7132323B2 (en) 2003-11-14 2006-11-07 International Business Machines Corporation CMOS well structure and method of forming the same
US6927137B2 (en) 2003-12-01 2005-08-09 Texas Instruments Incorporated Forming a retrograde well in a transistor to enhance performance of the transistor
US8187959B2 (en) 2003-12-18 2012-05-29 Imec Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same
US7045456B2 (en) 2003-12-22 2006-05-16 Texas Instruments Incorporated MOS transistor gates with thin lower metal silicide and methods for making the same
US7111185B2 (en) 2003-12-23 2006-09-19 Micron Technology, Inc. Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit
DE10360874B4 (de) 2003-12-23 2009-06-04 Infineon Technologies Ag Feldeffekttransistor mit Heteroschichtstruktur sowie zugehöriges Herstellungsverfahren
US7015741B2 (en) 2003-12-23 2006-03-21 Intel Corporation Adaptive body bias for clock skew compensation
US7005333B2 (en) 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
KR100597460B1 (ko) 2003-12-31 2006-07-05 동부일렉트로닉스 주식회사 반도체 소자의 트랜지스터 및제조방법
US6917237B1 (en) 2004-03-02 2005-07-12 Intel Corporation Temperature dependent regulation of threshold voltage
US7089515B2 (en) 2004-03-09 2006-08-08 International Business Machines Corporation Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power
US7176530B1 (en) 2004-03-17 2007-02-13 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor
US7089513B2 (en) 2004-03-19 2006-08-08 International Business Machines Corporation Integrated circuit design for signal integrity, avoiding well proximity effects
US7564105B2 (en) 2004-04-24 2009-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-plannar and FinFET-like transistors on bulk silicon
US7402207B1 (en) 2004-05-05 2008-07-22 Advanced Micro Devices, Inc. Method and apparatus for controlling the thickness of a selective epitaxial growth layer
JP4795653B2 (ja) 2004-06-15 2011-10-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7562233B1 (en) 2004-06-22 2009-07-14 Transmeta Corporation Adaptive control of operating and body bias voltages
US7221021B2 (en) 2004-06-25 2007-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming high voltage devices with retrograde well
US7491988B2 (en) 2004-06-28 2009-02-17 Intel Corporation Transistors with increased mobility in the channel zone and method of fabrication
US7169675B2 (en) 2004-07-07 2007-01-30 Chartered Semiconductor Manufacturing, Ltd Material architecture for the fabrication of low temperature transistor
US7462908B2 (en) 2004-07-14 2008-12-09 International Rectifier Corporation Dynamic deep depletion field effect transistor
US7186622B2 (en) 2004-07-15 2007-03-06 Infineon Technologies Ag Formation of active area using semiconductor growth process without STI integration
US7846822B2 (en) 2004-07-30 2010-12-07 The Board Of Trustees Of The University Of Illinois Methods for controlling dopant concentration and activation in semiconductor structures
US7002214B1 (en) 2004-07-30 2006-02-21 International Business Machines Corporation Ultra-thin body super-steep retrograde well (SSRW) FET devices
US7071103B2 (en) 2004-07-30 2006-07-04 International Business Machines Corporation Chemical treatment to retard diffusion in a semiconductor overlayer
DE102004037087A1 (de) 2004-07-30 2006-03-23 Advanced Micro Devices, Inc., Sunnyvale Selbstvorspannende Transistorstruktur und SRAM-Zellen mit weniger als sechs Transistoren
US7119381B2 (en) 2004-07-30 2006-10-10 Freescale Semiconductor, Inc. Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices
JP4469677B2 (ja) 2004-08-04 2010-05-26 パナソニック株式会社 半導体装置およびその製造方法
JP4664631B2 (ja) 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
US7189627B2 (en) 2004-08-19 2007-03-13 Texas Instruments Incorporated Method to improve SRAM performance and stability
US20060049464A1 (en) 2004-09-03 2006-03-09 Rao G R Mohan Semiconductor devices with graded dopant regions
US8106481B2 (en) 2004-09-03 2012-01-31 Rao G R Mohan Semiconductor devices with graded dopant regions
JP4540438B2 (ja) * 2004-09-27 2010-09-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US7095094B2 (en) 2004-09-29 2006-08-22 Agere Systems Inc. Multiple doping level bipolar junctions transistors and method for forming
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7268049B2 (en) 2004-09-30 2007-09-11 International Business Machines Corporation Structure and method for manufacturing MOSFET with super-steep retrograded island
KR100652381B1 (ko) 2004-10-28 2006-12-01 삼성전자주식회사 다수의 나노 와이어 채널을 구비한 멀티 브릿지 채널 전계효과 트랜지스터 및 그 제조방법
US7226833B2 (en) 2004-10-29 2007-06-05 Freescale Semiconductor, Inc. Semiconductor device structure and method therefor
DE102004053761A1 (de) 2004-11-08 2006-05-18 Robert Bosch Gmbh Halbleitereinrichtung und Verfahren für deren Herstellung
US7402872B2 (en) 2004-11-18 2008-07-22 Intel Corporation Method for forming an integrated circuit
US20060113591A1 (en) 2004-11-30 2006-06-01 Chih-Hao Wan High performance CMOS devices and methods for making same
US7105399B1 (en) 2004-12-07 2006-09-12 Advanced Micro Devices, Inc. Selective epitaxial growth for tunable channel thickness
KR100642407B1 (ko) 2004-12-29 2006-11-08 주식회사 하이닉스반도체 반도체 메모리 소자의 셀 트랜지스터 제조 방법
KR100613294B1 (ko) 2004-12-30 2006-08-21 동부일렉트로닉스 주식회사 단채널 효과가 개선되는 모스 전계효과 트랜지스터 및 그제조 방법
US20060154428A1 (en) 2005-01-12 2006-07-13 International Business Machines Corporation Increasing doping of well compensating dopant region according to increasing gate length
US7193279B2 (en) 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US20060166417A1 (en) 2005-01-27 2006-07-27 International Business Machines Corporation Transistor having high mobility channel and methods
US7531436B2 (en) 2005-02-14 2009-05-12 Texas Instruments Incorporated Highly conductive shallow junction formation
US7404114B2 (en) 2005-02-15 2008-07-22 International Business Machines Corporation System and method for balancing delay of signal communication paths through well voltage adjustment
US20060203581A1 (en) 2005-03-10 2006-09-14 Joshi Rajiv V Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions
US7407850B2 (en) 2005-03-29 2008-08-05 Texas Instruments Incorporated N+ poly on high-k dielectric for semiconductor devices
JP4493536B2 (ja) 2005-03-30 2010-06-30 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US7170120B2 (en) 2005-03-31 2007-01-30 Intel Corporation Carbon nanotube energy well (CNEW) field effect transistor
US7338817B2 (en) 2005-03-31 2008-03-04 Intel Corporation Body bias compensation for aged transistors
US7271079B2 (en) 2005-04-06 2007-09-18 International Business Machines Corporation Method of doping a gate electrode of a field effect transistor
US7605429B2 (en) 2005-04-15 2009-10-20 International Business Machines Corporation Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
US7598545B2 (en) * 2005-04-21 2009-10-06 International Business Machines Corporation Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
US7446380B2 (en) 2005-04-29 2008-11-04 International Business Machines Corporation Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS
US7441211B1 (en) 2005-05-06 2008-10-21 Blaze Dfm, Inc. Gate-length biasing for digital circuit optimization
US20060273379A1 (en) 2005-06-06 2006-12-07 Alpha & Omega Semiconductor, Ltd. MOSFET using gate work function engineering for switching applications
US7354833B2 (en) 2005-06-10 2008-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving threshold voltage stability of a MOS device
US20070040222A1 (en) 2005-06-15 2007-02-22 Benjamin Van Camp Method and apparatus for improved ESD performance
US7190050B2 (en) 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
JP4800700B2 (ja) 2005-08-01 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体集積回路
US7409651B2 (en) 2005-08-05 2008-08-05 International Business Machines Corporation Automated migration of analog and mixed-signal VLSI design
US7314794B2 (en) 2005-08-08 2008-01-01 International Business Machines Corporation Low-cost high-performance planar back-gate CMOS
US7307471B2 (en) 2005-08-26 2007-12-11 Texas Instruments Incorporated Adaptive voltage control and body bias for performance and energy optimization
US7838369B2 (en) 2005-08-29 2010-11-23 National Semiconductor Corporation Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
JP2007073578A (ja) 2005-09-05 2007-03-22 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007103863A (ja) 2005-10-07 2007-04-19 Nec Electronics Corp 半導体デバイス
US7465642B2 (en) 2005-10-28 2008-12-16 International Business Machines Corporation Methods for forming semiconductor structures with buried isolation collars
JP4256381B2 (ja) 2005-11-09 2009-04-22 株式会社東芝 半導体装置
US8255843B2 (en) 2005-11-14 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing strained-silicon semiconductor device
US7462538B2 (en) 2005-11-15 2008-12-09 Infineon Technologies Ag Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
US7759206B2 (en) 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
EP1958245B1 (en) 2005-12-09 2013-10-16 Semequip, Inc. Method for the manufacture of semiconductor devices by the implantation of carbon clusters
WO2007078802A2 (en) 2005-12-22 2007-07-12 Asm America, Inc. Epitaxial deposition of doped semiconductor materials
KR100657130B1 (ko) 2005-12-27 2006-12-13 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US7633134B2 (en) 2005-12-29 2009-12-15 Jaroslav Hynecek Stratified photodiode for high resolution CMOS image sensor implemented with STI technology
US7485536B2 (en) 2005-12-30 2009-02-03 Intel Corporation Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers
JP5145691B2 (ja) 2006-02-23 2013-02-20 セイコーエプソン株式会社 半導体装置
US20070212861A1 (en) 2006-03-07 2007-09-13 International Business Machines Corporation Laser surface annealing of antimony doped amorphized semiconductor region
US7380225B2 (en) 2006-03-14 2008-05-27 International Business Machines Corporation Method and computer program for efficient cell failure rate estimation in cell arrays
JP5283827B2 (ja) 2006-03-30 2013-09-04 富士通セミコンダクター株式会社 半導体装置の製造方法
US7681628B2 (en) 2006-04-12 2010-03-23 International Business Machines Corporation Dynamic control of back gate bias in a FinFET SRAM cell
US7348629B2 (en) 2006-04-20 2008-03-25 International Business Machines Corporation Metal gated ultra short MOSFET devices
US20070257315A1 (en) 2006-05-04 2007-11-08 International Business Machines Corporation Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors
KR100703986B1 (ko) 2006-05-22 2007-04-09 삼성전자주식회사 동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법
JPWO2007136102A1 (ja) 2006-05-23 2009-10-01 日本電気株式会社 集積回路、及び半導体装置の製造方法
US7384835B2 (en) 2006-05-25 2008-06-10 International Business Machines Corporation Metal oxide field effect transistor with a sharp halo and a method of forming the transistor
US7941776B2 (en) 2006-05-26 2011-05-10 Open-Silicon Inc. Method of IC design optimization via creation of design-specific cells from post-layout patterns
JP5073968B2 (ja) 2006-05-31 2012-11-14 住友化学株式会社 化合物半導体エピタキシャル基板およびその製造方法
US7503020B2 (en) 2006-06-19 2009-03-10 International Business Machines Corporation IC layout optimization to improve yield
US7469164B2 (en) 2006-06-26 2008-12-23 Nanometrics Incorporated Method and apparatus for process control with in-die metrology
US7538412B2 (en) 2006-06-30 2009-05-26 Infineon Technologies Austria Ag Semiconductor device with a field stop zone
GB0613289D0 (en) 2006-07-04 2006-08-16 Imagination Tech Ltd Synchronisation of execution threads on a multi-threaded processor
WO2008016650A2 (en) 2006-07-31 2008-02-07 Applied Materials, Inc. Methods of forming carbon-containing silicon epitaxial layers
US7496862B2 (en) 2006-08-29 2009-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for automatically modifying integrated circuit layout
TW200821417A (en) 2006-09-07 2008-05-16 Sumco Corp Semiconductor substrate for solid state imaging device, solid state imaging device, and method for manufacturing them
US20080067589A1 (en) 2006-09-20 2008-03-20 Akira Ito Transistor having reduced channel dopant fluctuation
JP2008085253A (ja) 2006-09-29 2008-04-10 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7683442B1 (en) 2006-09-29 2010-03-23 Burr James B Raised source/drain with super steep retrograde channel
JP2008103492A (ja) * 2006-10-18 2008-05-01 Nec Electronics Corp 半導体装置およびその製造方法
US7642150B2 (en) 2006-11-08 2010-01-05 Varian Semiconductor Equipment Associates, Inc. Techniques for forming shallow junctions
US7750374B2 (en) 2006-11-14 2010-07-06 Freescale Semiconductor, Inc Process for forming an electronic device including a transistor having a metal gate electrode
US7696000B2 (en) 2006-12-01 2010-04-13 International Business Machines Corporation Low defect Si:C layer with retrograde carbon profile
US7741200B2 (en) 2006-12-01 2010-06-22 Applied Materials, Inc. Formation and treatment of epitaxial layer containing silicon and carbon
US7821066B2 (en) 2006-12-08 2010-10-26 Michael Lebby Multilayered BOX in FDSOI MOSFETS
US7897495B2 (en) 2006-12-12 2011-03-01 Applied Materials, Inc. Formation of epitaxial layer containing silicon and carbon
US8217423B2 (en) 2007-01-04 2012-07-10 International Business Machines Corporation Structure and method for mobility enhanced MOSFETs with unalloyed silicide
US7416605B2 (en) 2007-01-08 2008-08-26 Freescale Semiconductor, Inc. Anneal of epitaxial layer in a semiconductor device
KR100819562B1 (ko) 2007-01-15 2008-04-08 삼성전자주식회사 레트로그레이드 영역을 갖는 반도체소자 및 그 제조방법
US20080169516A1 (en) 2007-01-17 2008-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices for alleviating well proximity effects
KR100862113B1 (ko) 2007-01-22 2008-10-09 삼성전자주식회사 공정 변화에 대한 정보를 이용하여 공급전압/공급주파수를제어할 수 있는 장치와 방법
US7644377B1 (en) 2007-01-31 2010-01-05 Hewlett-Packard Development Company, L.P. Generating a configuration of a system that satisfies constraints contained in models
KR100836767B1 (ko) 2007-02-05 2008-06-10 삼성전자주식회사 높은 전압을 제어하는 모스 트랜지스터를 포함하는 반도체소자 및 그 형성 방법
KR101312259B1 (ko) 2007-02-09 2013-09-25 삼성전자주식회사 박막 트랜지스터 및 그 제조방법
US7781288B2 (en) 2007-02-21 2010-08-24 International Business Machines Corporation Semiconductor structure including gate electrode having laterally variable work function
US7818702B2 (en) 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
US7831873B1 (en) 2007-03-07 2010-11-09 Xilinx, Inc. Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits
US7602017B2 (en) 2007-03-13 2009-10-13 Fairchild Semiconductor Corporation Short channel LV, MV, and HV CMOS devices
US7598142B2 (en) 2007-03-15 2009-10-06 Pushkar Ranade CMOS device with dual-epi channels and self-aligned contacts
JP2008235568A (ja) 2007-03-20 2008-10-02 Toshiba Corp 半導体装置およびその製造方法
US8394687B2 (en) 2007-03-30 2013-03-12 Intel Corporation Ultra-abrupt semiconductor junction profile
US7496867B2 (en) 2007-04-02 2009-02-24 Lsi Corporation Cell library management for power optimization
US7737472B2 (en) 2007-04-05 2010-06-15 Panasonic Corporation Semiconductor integrated circuit device
CN101030602B (zh) 2007-04-06 2012-03-21 上海集成电路研发中心有限公司 一种可减小短沟道效应的mos晶体管及其制作方法
US7692220B2 (en) 2007-05-01 2010-04-06 Suvolta, Inc. Semiconductor device storage cell structure, method of operation, and method of manufacture
US7586322B1 (en) 2007-05-02 2009-09-08 Altera Corporation Test structure and method for measuring mismatch and well proximity effects
US20080272409A1 (en) 2007-05-03 2008-11-06 Dsm Solutions, Inc.; JFET Having a Step Channel Doping Profile and Method of Fabrication
US20080308870A1 (en) * 2007-06-15 2008-12-18 Qimonda Ag Integrated circuit with a split function gate
US20080315206A1 (en) 2007-06-19 2008-12-25 Herner S Brad Highly Scalable Thin Film Transistor
US7759714B2 (en) 2007-06-26 2010-07-20 Hitachi, Ltd. Semiconductor device
WO2009000934A1 (en) 2007-06-28 2008-12-31 Sagantec Israel Ltd Semiconductor layout modification method based on design rule and user constraints
US7651920B2 (en) 2007-06-29 2010-01-26 Infineon Technologies Ag Noise reduction in semiconductor device using counter-doping
KR100934789B1 (ko) 2007-08-29 2009-12-31 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
US7895546B2 (en) 2007-09-04 2011-02-22 Lsi Corporation Statistical design closure
JP2009064860A (ja) 2007-09-05 2009-03-26 Renesas Technology Corp 半導体装置
US7795677B2 (en) 2007-09-05 2010-09-14 International Business Machines Corporation Nanowire field-effect transistors
JP5242103B2 (ja) 2007-09-07 2013-07-24 ルネサスエレクトロニクス株式会社 半導体集積回路のレイアウト方法
US7675317B2 (en) 2007-09-14 2010-03-09 Altera Corporation Integrated circuits with adjustable body bias and power supply circuitry
US7926018B2 (en) 2007-09-25 2011-04-12 Synopsys, Inc. Method and apparatus for generating a layout for a transistor
US8053340B2 (en) 2007-09-27 2011-11-08 National University Of Singapore Method for fabricating semiconductor devices with reduced junction diffusion
US7704844B2 (en) 2007-10-04 2010-04-27 International Business Machines Corporation High performance MOSFET
US7948008B2 (en) 2007-10-26 2011-05-24 Micron Technology, Inc. Floating body field-effect transistors, and methods of forming floating body field-effect transistors
US8329564B2 (en) 2007-10-26 2012-12-11 International Business Machines Corporation Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method
DE102007052220B4 (de) 2007-10-31 2015-04-09 Globalfoundries Inc. Verfahren zur Dotierstoffprofileinstellung für MOS-Bauelemente durch Anpassen einer Abstandshalterbreite vor der Implantation
JP5528667B2 (ja) 2007-11-28 2014-06-25 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の制御方法
US7994573B2 (en) 2007-12-14 2011-08-09 Fairchild Semiconductor Corporation Structure and method for forming power devices with carbon-containing region
US7745270B2 (en) 2007-12-28 2010-06-29 Intel Corporation Tri-gate patterning using dual layer gate stack
US7622341B2 (en) 2008-01-16 2009-11-24 International Business Machines Corporation Sige channel epitaxial development for high-k PFET manufacturability
DE102008006961A1 (de) 2008-01-31 2009-08-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen eines verformten Kanalgebiets in einem Transistor durch eine tiefe Implantation einer verformungsinduzierenden Sorte unter das Kanalgebiet
JP2011512677A (ja) 2008-02-14 2011-04-21 マックスパワー・セミコンダクター・インコーポレイテッド 半導体素子構造及び関連プロセス
JP2009200211A (ja) * 2008-02-21 2009-09-03 Renesas Technology Corp 半導体装置およびその製造方法
US7700424B2 (en) 2008-02-27 2010-04-20 Applied Materials, Inc. Method of forming an embedded silicon carbon epitaxial layer
FR2928028B1 (fr) 2008-02-27 2011-07-15 St Microelectronics Crolles 2 Procede de fabrication d'un dispositif semi-conducteur a grille enterree et circuit integre correspondant.
US7867835B2 (en) 2008-02-29 2011-01-11 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system for suppressing short channel effects
US7750682B2 (en) 2008-03-10 2010-07-06 International Business Machines Corporation CMOS back-gated keeper technique
US7968440B2 (en) 2008-03-19 2011-06-28 The Board Of Trustees Of The University Of Illinois Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
KR101502033B1 (ko) 2008-04-11 2015-03-12 삼성전자주식회사 Ａｄｃ의 전류 제어 회로 및 방법
EP2112686B1 (en) 2008-04-22 2011-10-12 Imec Method for fabricating a dual workfunction semiconductor device made thereof
JP2009267159A (ja) 2008-04-25 2009-11-12 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体ウェーハの製造装置及び方法
JP5173582B2 (ja) 2008-05-19 2013-04-03 株式会社東芝 半導体装置
US8225255B2 (en) 2008-05-21 2012-07-17 International Business Machines Corporation Placement and optimization of process dummy cells
DE102008026213B3 (de) 2008-05-30 2009-09-24 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Durchlassstromerhöhung in Transistoren durch asymmetrische Amorphisierungsimplantation
FR2932609B1 (fr) 2008-06-11 2010-12-24 Commissariat Energie Atomique Transistor soi avec plan de masse et grille auto-alignes et oxyde enterre d'epaisseur variable
US8471307B2 (en) 2008-06-13 2013-06-25 Texas Instruments Incorporated In-situ carbon doped e-SiGeCB stack for MOS transistor
US8129797B2 (en) 2008-06-18 2012-03-06 International Business Machines Corporation Work function engineering for eDRAM MOSFETs
US20100012988A1 (en) 2008-07-21 2010-01-21 Advanced Micro Devices, Inc. Metal oxide semiconductor devices having implanted carbon diffusion retardation layers and methods for fabricating the same
US7951678B2 (en) 2008-08-12 2011-05-31 International Business Machines Corporation Metal-gate high-k reference structure
DE102008045037B4 (de) 2008-08-29 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren
US7927943B2 (en) 2008-09-12 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for tuning a work function of high-k metal gate devices
WO2010036621A2 (en) 2008-09-25 2010-04-01 Applied Materials, Inc. Defect-free junction formation using octadecaborane self-amorphizing implants
US20100100856A1 (en) 2008-10-17 2010-04-22 Anurag Mittal Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics
JP5519140B2 (ja) 2008-10-28 2014-06-11 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US7824986B2 (en) 2008-11-05 2010-11-02 Micron Technology, Inc. Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions
US8103983B2 (en) 2008-11-12 2012-01-24 International Business Machines Corporation Electrically-driven optical proximity correction to compensate for non-optical effects
US8170857B2 (en) 2008-11-26 2012-05-01 International Business Machines Corporation In-situ design method and system for improved memory yield
DE102008059501B4 (de) 2008-11-28 2012-09-20 Advanced Micro Devices, Inc. Technik zur Verbesserung des Dotierstoffprofils und der Kanalleitfähigkeit durch Millisekunden-Ausheizprozesse
US20100148153A1 (en) 2008-12-16 2010-06-17 Hudait Mantu K Group III-V devices with delta-doped layer under channel region
US7960238B2 (en) 2008-12-29 2011-06-14 Texas Instruments Incorporated Multiple indium implant methods and devices and integrated circuits therefrom
DE102008063427B4 (de) 2008-12-31 2013-02-28 Advanced Micro Devices, Inc. Verfahren zum selektiven Herstellen eines Transistors mit einem eingebetteten verformungsinduzierenden Material mit einer graduell geformten Gestaltung
JP5350815B2 (ja) 2009-01-22 2013-11-27 株式会社東芝 半導体装置
US7829402B2 (en) 2009-02-10 2010-11-09 General Electric Company MOSFET devices and methods of making
US20100207182A1 (en) 2009-02-13 2010-08-19 International Business Machines Corporation Implementing Variable Threshold Voltage Transistors
US8048791B2 (en) 2009-02-23 2011-11-01 Globalfoundries Inc. Method of forming a semiconductor device
US8163619B2 (en) 2009-03-27 2012-04-24 National Semiconductor Corporation Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
US8178430B2 (en) 2009-04-08 2012-05-15 International Business Machines Corporation N-type carrier enhancement in semiconductors
US8214190B2 (en) 2009-04-13 2012-07-03 International Business Machines Corporation Methodology for correlated memory fail estimations
US7943457B2 (en) 2009-04-14 2011-05-17 International Business Machines Corporation Dual metal and dual dielectric integration for metal high-k FETs
JP2010258264A (ja) 2009-04-27 2010-11-11 Toshiba Corp 半導体集積回路装置およびその設計方法
US8183107B2 (en) 2009-05-27 2012-05-22 Globalfoundries Inc. Semiconductor devices with improved local matching and end resistance of RX based resistors
US8173499B2 (en) 2009-06-12 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a gate stack integration of complementary MOS device
US8227307B2 (en) 2009-06-24 2012-07-24 International Business Machines Corporation Method for removing threshold voltage adjusting layer with external acid diffusion process
CN101661889B (zh) 2009-08-15 2011-09-07 北京大学深圳研究生院 一种部分耗尽的绝缘层上硅mos晶体管的制作方法
JP5110062B2 (ja) * 2009-09-24 2012-12-26 富士通セミコンダクター株式会社 半導体装置の製造方法
US8236661B2 (en) 2009-09-28 2012-08-07 International Business Machines Corporation Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage
CN102034865B (zh) 2009-09-30 2012-07-04 中国科学院微电子研究所 半导体器件及其制造方法
US20110079861A1 (en) 2009-09-30 2011-04-07 Lucian Shifren Advanced Transistors with Threshold Voltage Set Dopant Structures
US8273617B2 (en) * 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) * 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
EP2309544B1 (en) 2009-10-06 2019-06-12 IMEC vzw Tunnel field effect transistor with improved subthreshold swing
US8552795B2 (en) 2009-10-22 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate bias control circuit for system on chip
WO2011062789A1 (en) 2009-11-17 2011-05-26 Suvolta, Inc. Electronic devices and systems,and methods for making and using the same
CN101707210B (zh) * 2009-11-27 2012-05-30 北京大学 一种抗辐照的场效应晶体管、cmos集成电路及其制备
US8114761B2 (en) 2009-11-30 2012-02-14 Applied Materials, Inc. Method for doping non-planar transistors
US8598003B2 (en) 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
TWI404209B (zh) 2009-12-31 2013-08-01 Univ Nat Chiao Tung 高電子遷移率電晶體及其製作方法
US8343818B2 (en) 2010-01-14 2013-01-01 International Business Machines Corporation Method for forming retrograded well for MOSFET
US8697521B2 (en) 2010-01-21 2014-04-15 International Business Machines Corporation Structure and method for making low leakage and low mismatch NMOSFET
US8048810B2 (en) 2010-01-29 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal gate N/P patterning
US8288798B2 (en) 2010-02-10 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Step doping in extensions of III-V family semiconductor devices
US20110212590A1 (en) 2010-02-26 2011-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. High temperature implantation method for stressor formation
US8385147B2 (en) 2010-03-30 2013-02-26 Silicon Storage Technology, Inc. Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8176461B1 (en) 2010-05-10 2012-05-08 Xilinx, Inc. Design-specific performance specification based on a yield for programmable integrated circuits
US8201122B2 (en) 2010-05-25 2012-06-12 International Business Machines Corporation Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes
JP5614877B2 (ja) 2010-05-28 2014-10-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8361872B2 (en) 2010-09-07 2013-01-29 International Business Machines Corporation High performance low power bulk FET device and method of manufacture
JP2012060016A (ja) 2010-09-10 2012-03-22 Renesas Electronics Corp 半導体装置の評価方法、評価装置、及びシミュレーション方法
US8450169B2 (en) 2010-11-29 2013-05-28 International Business Machines Corporation Replacement metal gate structures providing independent control on work function and gate leakage current
US8466473B2 (en) 2010-12-06 2013-06-18 International Business Machines Corporation Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs
US8656339B2 (en) 2010-12-22 2014-02-18 Advanced Micro Devices, Inc. Method for analyzing sensitivity and failure probability of a circuit
US8299562B2 (en) 2011-03-28 2012-10-30 Nanya Technology Corporation Isolation structure and device structure including the same
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675172A (en) * 1994-05-17 1997-10-07 Hitachi, Ltd. Metal-insulator-semiconductor device having reduced threshold voltage and high mobility for high speed/low-voltage operation
US6271551B1 (en) * 1995-12-15 2001-08-07 U.S. Philips Corporation Si-Ge CMOS semiconductor device
US20030094627A1 (en) * 2000-10-18 2003-05-22 Fumio Ootsuka Semiconductor device and a method of manufacturing the same
US20020119292A1 (en) * 2000-12-22 2002-08-29 Sriram Venkatasanthanam Three-dimensional flexible adhesive film structures
US20030183856A1 (en) * 2002-03-28 2003-10-02 Karsten Wieczorek Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same
US20090302383A1 (en) * 2005-11-16 2009-12-10 Martin Knaipp High-Voltage Transistor and Component Containing the Latter

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