US20030189215A1 - Method of fabricating vertical structure leds - Google Patents

Method of fabricating vertical structure leds Download PDF

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Publication number
US20030189215A1
US20030189215A1 US10/118,316 US11831602A US2003189215A1 US 20030189215 A1 US20030189215 A1 US 20030189215A1 US 11831602 A US11831602 A US 11831602A US 2003189215 A1 US2003189215 A1 US 2003189215A1
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Prior art keywords
layer
forming
gan
metal support
trenches
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Abandoned
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US10/118,316
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English (en)
Inventor
Jong-Lam Lee
In-kwon Jeong
Myung Yoo
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Oriol Inc
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Individual
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=28674400&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US20030189215(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Individual filed Critical Individual
Priority to US10/118,316 priority Critical patent/US20030189215A1/en
Assigned to ORIOL, INC. reassignment ORIOL, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEONG, IN-KWON, LEE, JONG-LAM, YOO, MYUNG C.
Priority to EP10183473.7A priority patent/EP2261949B1/en
Priority to EP14194356.3A priority patent/EP2863444B1/en
Priority to EP10183510.6A priority patent/EP2261951B1/en
Priority to DE20321880U priority patent/DE20321880U1/de
Priority to EP14194349.8A priority patent/EP2860753B1/en
Priority to DE20321881U priority patent/DE20321881U1/de
Priority to EP14194354.8A priority patent/EP2860779B1/en
Priority to AU2003241280A priority patent/AU2003241280A1/en
Priority to DE60324413T priority patent/DE60324413D1/de
Priority to EP10183495.0A priority patent/EP2261950B1/en
Priority to PCT/US2003/009501 priority patent/WO2003088318A2/en
Priority to EP07013949.8A priority patent/EP1848026B1/en
Priority to EP03731009A priority patent/EP1502286B1/en
Priority to KR1020047016177A priority patent/KR100921457B1/ko
Priority to JP2003585153A priority patent/JP5325365B2/ja
Priority to AT03731009T priority patent/ATE412972T1/de
Publication of US20030189215A1 publication Critical patent/US20030189215A1/en
Priority to US11/002,413 priority patent/US7569865B2/en
Priority to US11/030,323 priority patent/US7588952B2/en
Priority to US11/232,957 priority patent/US7563629B2/en
Priority to US11/232,956 priority patent/US7250638B2/en
Priority to US11/896,307 priority patent/US7462881B2/en
Priority to US11/896,772 priority patent/US7576368B2/en
Priority to US12/458,703 priority patent/US7816705B2/en
Priority to US12/797,335 priority patent/US7928465B2/en
Priority to US13/047,371 priority patent/US8384120B2/en
Priority to US13/750,376 priority patent/US8809898B2/en
Priority to JP2013077709A priority patent/JP2013175748A/ja
Priority to US14/098,185 priority patent/US8896017B2/en
Priority to US14/496,076 priority patent/US9224907B2/en
Priority to JP2015076060A priority patent/JP6546432B2/ja
Priority to US14/950,773 priority patent/US9472727B2/en
Priority to US15/261,172 priority patent/US9882084B2/en
Priority to JP2016208006A priority patent/JP6268259B2/ja
Priority to US15/831,084 priority patent/US10243101B2/en
Priority to JP2018168460A priority patent/JP6547047B2/ja
Priority to US16/268,161 priority patent/US10461217B2/en
Priority to US16/387,312 priority patent/US10453993B1/en
Priority to US16/567,875 priority patent/US10600933B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/006—Thin film resistors
    • H—ELECTRICITY
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    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/008—Thermistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
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    • H01L33/0004—Devices characterised by their operation
    • H01L33/002—Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
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    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
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    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Definitions

  • the present invention relates to semiconductor device fabrication. More particularly, the present invention relates to a method of fabricating vertical devices using a metal support layer.
  • LEDs Light emitting diodes
  • the color (wavelength) of the light that is emitted by an LED depends on the semiconductor material that is used to fabricate the LED. This is because the wavelength of the emitted light depends on the semiconductor material's band-gap, which represents the energy difference between the material's valence band and conduction band electrons.
  • GaN Gallium-Nitride
  • InGaN/GaN semiconductor layers that emit green, blue, and white light.
  • This wavelength control ability enables an LED semiconductor designer to tailor material characteristics to achieve beneficial device characteristics. For example, GaN enables an LED semiconductor designer to produce blue LEDs, which are beneficial in optical recordings, and white LEDs, which can replace incandescent lamps.
  • GaN-based LEDs Because of the foregoing and other advantageous, the market for GaN-based LEDs is rapidly growing. Accordingly, GaN-based opto-electronic device technology has rapidly evolved since their commercial introduction in 1994. Because the efficiency of GaN light emitting diodes has surpassed that of incandescent lighting, and is now comparable with that of fluorescent lighting, the market for GaN based LEDs is expected to continue its rapid growth.
  • GaN devices are too expensive for many applications.
  • One reason for this is the high cost of manufacturing GaN-based devices, which in turn is related to the difficulties of growing GaN epitaxial layers and of subsequently dicing out completed GaN-based devices.
  • GaN-based devices are typically fabricated on sapphire substrates. This is because sapphire wafers are commercially available in dimensions that are suitable for mass-producing GaN-based devices, because sapphire supports relatively high-quality GaN epitaxial layer growths, and because of the extensive temperature handling capability of sapphire.
  • GaN-based devices are fabricated on 2′′ diameter sapphire wafers that are either 330 or 430 microns thick. Such a diameter enables the fabrication of thousands of individual devices, while the thickness is sufficient to support device fabrication without excessive wafer warping.
  • sapphire is chemically and thermally stable, has a high melting temperature that enables high temperature fabrication processes, has a high bonding energy (122.4 Kcal/mole), and a high dielectric constant.
  • sapphires are crystalline aluminum oxide, Al 2 O 3 .
  • Fabricating semiconductor devices on sapphire is typically performed by growing an n-GaN epitaxial layer on a sapphire substrate using metal oxide chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Then, a plurality of individual devices, such as GaN LEDs, is fabricated on the epitaxial layer using normal semiconductor processing techniques. After the individual devices are fabricated they must be diced out (separated) of the sapphire substrate. However, since sapphires are extremely hard, are chemically resistant, and do not have natural cleave angles, sapphire substrates are difficult to dice.
  • MOCVD metal oxide chemical vapor deposition
  • MBE molecular beam epitaxy
  • dicing typically requires that the sapphire substrate be thinned to about 100 microns by mechanical grinding, lapping, and/or polishing. It should be noted that such mechanical steps are time consuming and expensive, and that such steps reduce device yields. Even after thinning sapphires remain difficult to dice. Thus, after thinning and polishing, the sapphire substrate is usually attached to a supporting tape. Then, a diamond saw or stylus forms scribe lines between the individual devices. Such scribing typically requires at least half an hour to process one substrate, adding even more to the manufacturing costs. Additionally, since the scribe lines have to be relatively wide to enable subsequent dicing, the device yields are reduced, adding even more to manufacturing costs. After scribing, the sapphire substrates can be rolled using a rubber roller or struck with a knife-edge to produce stress cracks that can be used to dice out the individual semiconductor devices. Such mechanical handling reduces yields even more.
  • the LED device topologies that are available when using sapphire substrates (or other insulating substrates) are, in practice, limited to lateral and vertical topologies.
  • the metallic electrical contacts that are used to inject electrical current into the LED are both located on upper surfaces (or on the same side of the substrate).
  • the sapphire (insulating) substrate is removed, and the other contact is located on a lower surface.
  • FIGS. 1A and 1B illustrate a typical lateral GaN-based LED 20 that is fabricated on a sapphire substrate 22 .
  • an n-GaN buffer layer 24 is formed on the substrate 22 .
  • a relatively thick n-GaN layer 26 is formed on the buffer layer 24 .
  • An active layer 28 having multiple quantum wells of aluminum-indium-gallium-nitride (AlInGaN) or of InGaN/GaN is then formed on the n-type GaN layer 26 .
  • a p-GaN layer 30 is then formed on the active layer 26 .
  • a transparent conductive layer 32 is then formed on the p-GaN layer 30 .
  • the transparent conductive layer 32 may be made of any suitable material, such as Ru/Au, Ni/Au or indium-tin-oxide (ITO).
  • a p-type electrode 34 is then formed on one side of the transparent conductive layer 32 . Suitable p-type electrode materials include Ni/Au, Pd/Au, Pd/Ni and Pt.
  • a pad 36 is then formed on the p-type electrode 34 . Beneficially, the pad 36 is Au.
  • the transparent conductive layer 32 , the p-GaN layer 30 , the active layer 28 and part of the n-GaN layer 26 are etched to form a step. Because of the difficulty of wet etching GaN, a dry etch is usually used.
  • the LED 20 is completed by forming an n-electrode pad 38 (usually Au) and a pad 40 on the step.
  • FIG. 1B illustrates a top down view of the LED 20 .
  • lateral GaN-based LEDs have a significant draw back in that having both metal contacts ( 36 and 40 ) on the same side of the LED significantly reduces the surface area available for light emission.
  • the metal contacts 36 and 40 are physically close together.
  • the pads 36 are often Au.
  • the Au often spreads. Au spreading can bring the electrical contacts even closer together.
  • Such closely spaced electrodes 34 are highly susceptible to ESD damage.
  • FIGS. 2A and 2B illustrate a vertical GaN-based LED 50 that was formed on a sapphire substrate that was subsequently removed.
  • the LED 50 includes a GaN buffer layer 54 having an n-metal contact 56 on a bottom side, and a relatively thick n-GaN layer 58 on the other.
  • the n-metal contact 56 is beneficially formed from a high reflectively layer that is overlaid by a high conductivity metal, including, for example, Au.
  • An active layer 60 having multiple quantum wells is formed on the n-type GaN layer 58 , and a p-GaN layer 62 is formed on the active layer 60 .
  • a transparent conductive layer 64 is then formed on the p-GaN layer 62 , and a p-type electrode 66 is formed on the transparent conductive layer 64 .
  • a pad 68 is formed on the p-type electrode 66 .
  • the materials for the various layers are similar to those used in the lateral LED 20 .
  • the vertical GaN-based LED 50 as the advantage that etching a step is not required.
  • the sapphire substrate (not shown) has to be removed. Such removal can be difficult, particularly if device yields are of concern.
  • sapphire substrate removal using laser lift off is known.
  • vertical GaN-based LEDs have the advantage that only one metal contact ( 68 ) blocks light.
  • lateral GaN-based LEDs must have a larger surface area, which lowers device yields.
  • the reflecting layer of the n-type contact 56 of vertical GaN-based LEDs reflect light that is otherwise absorbed in lateral GaN-based LEDs.
  • a lateral GaN-based LED must have a significantly larger surface area. Because of these issues, a 2′′ diameter sapphire wafer can produce about 35,000 vertical GaN-based LEDs, but only about 12,000 lateral GaN-based LEDs.
  • the lateral topology is more vulnerable to static electricity, primarily because the two electrodes ( 36 and 40 ) are so close together. Additionally, as the lateral topology is fabricated on an insulating substrate, and as the vertical topology can be attached to a heat sink, the lateral topology has relatively poor thermal dissipation. Thus, in many respects the vertical topology is operationally superior to the lateral topology.
  • a new method of fabricating vertical topology devices would be beneficial.
  • a method that provides for mechanical stability of semiconductor wafer layers, that enables vertical topology electrical contact formation, and that improves heat dissipation would be highly useful, particularly with devices subject to high electrical currents, such as laser diodes or high-power LEDs.
  • such a method would enable forming multiple semiconductor layers on an insulating substrate, the adding of a top support metal layer that provides for top electrical contacts and for structural stability, and the removal of the insulating substrate.
  • the principles of the present invention provide for a method of fabricating semiconductor devices on insulating substrates by first forming semiconductor layers on the insulating substrate, followed by forming a metal layer over the semiconductor layers, followed by removal of the insulating substrate to isolate a structurally supported wafer comprised of the formed semiconductor layers and the metal layer.
  • the metal layer supports the semiconductor layers to prevent warping and/or other damage and provides for electrical contacts.
  • the metal layer includes a metal, such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or a metal containing material such as titanium nitride.
  • Forming of the metal layer can be performed in numerous ways, for example, by electroplating, by electro-less plating, by CVD, or by sputtering. Subsequently, bottom electrical contacts can be added to the semiconductor layers and then individual semiconductor devices can be diced from the resulting structure.
  • the principles of the present invention further provide for a method of fabricating vertical topology GaN-based devices on an insulating substrate by the use of a metal support film and by the subsequent removal of the insulating substrate.
  • semiconductor layers for the GaN-based devices are formed on an insulating (sapphire) substrate using normal semiconductor fabrication techniques.
  • trenches that define the boundaries of the individual devices are formed through the semiconductor layers. Those trenches may also be formed into the insulating substrate.
  • Trench forming is beneficially performed using inductive coupled plasma reactive ion etching (ICPRIE).
  • ICPRIE inductive coupled plasma reactive ion etching
  • the trenches are then filled with an easily removed layer (such as a photo-resist).
  • a metal support structure is then formed on the semiconductor layers.
  • the metal support structure includes a metal, such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or a metal-containing material such as titanium nitride.
  • a metal such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al
  • a metal-containing material such as titanium nitride.
  • Forming of the metal support structure can be performed in numerous ways, for example, by electroplating, by electro-less plating, by CVD, or by sputtering.
  • the insulating substrate is then removed, beneficially using a laser-lift off process. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
  • the principles of the present invention specifically provide for a method of fabricating vertical topology GaN-based LEDs on sapphire substrates.
  • semiconductor layers for the vertical topology GaN-based LEDs are formed on a sapphire substrate using normal semiconductor fabrication techniques.
  • trenches that define the boundaries of the individual vertical topology GaN-based LEDs are formed through the semiconductor layers. Those trenches may also be formed into the sapphire substrate.
  • Trench forming is beneficially performed using inductive coupled plasma reactive ion etching (ICPRIE).
  • ICPRIE inductive coupled plasma reactive ion etching
  • the trenches are fabricated using ICPRIE.
  • the trenches are then beneficially filled with an easily removed layer (such as a photo-resist).
  • a metal support structure is then formed on the semiconductor layers.
  • the metal support structure includes a metal, such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al, or a metal-containing material such as titanium nitride.
  • a metal such as Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al
  • a metal-containing material such as titanium nitride.
  • Forming of the metal layer can be performed in numerous ways, for example, by electroplating, by electro-less plating, by CVD, or by sputtering.
  • the sapphire substrate is then removed, beneficially using a laser-lift off process. Electrical contacts, a passivation layer, and metallic pads are then added to the individual LEDs, and the individual LEDs are then diced out.
  • FIG. 1A illustrates a sectional view of a typical lateral topology GaN-based LED
  • FIG. 1B shows a top down view of the GaN-based LED illustrated in FIG. 1A;
  • FIG. 2A illustrates a sectional view of a typical vertical topology GaN-based LED
  • FIG. 2B shows a top down view of the GaN-based LED illustrated in FIG. 2A.
  • FIGS. 3 - 15 illustrate steps of forming a light emitting diode that are in accord with the principles of the present invention.
  • the principles of the present invention provide for methods of fabricating semiconductor devices, such as GaN-based vertical topology LEDs, on insulating substrates, such as sapphire substrates, using metal support films. While those principles are illustrated in a detailed description of a method of fabricating vertical topology GaN-based LEDs on a sapphire substrate, those principles are broader than that illustrated method. Therefore, the principles of the present invention are to be limited only by the appended claims as understood under United States Patent Laws.
  • FIGS. 3 - 15 illustrate a method of manufacturing vertical topology GaN-based light emitting diodes (LEDs) on sapphire substrates.
  • Sapphire substrates are readily available in suitable sizes, are thermally, chemically, and mechanically stable, are relatively inexpensive, and support the growth of good quality GaN epitaxial layers. It should be understood that those figures are not to scale.
  • a GaN-based LED layer structure is formed on a 330-430 micron-thick, 2′′ diameter (0001) sapphire substrate 122 .
  • the GaN-based LED layer structure includes an n-GaN buffer layer 124 , an InGaN/GaN active layer 126 (beneficially having the proper composition to emit blue light) on the buffer layer 124 , and a p-GaN contact layer 128 on the active layer 126 .
  • the buffer layer 124 beneficially includes both a 2 ⁇ m undoped GaN layer formed directly on the substrate, and a 1 ⁇ m thick, n-type, silicon doped, GaN layer.
  • the p-GaN contact layer 128 is beneficially about 0.05 ⁇ m thick and is doped with Mg.
  • the GaN-based LED layer structure is beneficially less than about 5 microns thick.
  • Various standard epitaxial growth techniques such as vapor phase epitaxy, MOCVD, and MBE, together with suitable dopants and other materials, can be used to produce the GaN-based LED layer structure.
  • trenches 130 are formed through the vertical topology GaN-based LED layer structure. Those trenches 130 may extend into the sapphire substrate 122 .
  • the trenches 130 define the individual LED semiconductor structures that will be produced. Each individual LED semiconductor structure is beneficially a square about 200 microns wide.
  • the trenches 130 are beneficially narrower than about 10 microns (preferably close to 1 micron) and extend deeper than about 5 microns into the sapphire substrate 122 .
  • the trenches 130 assist a subsequent chip separation process.
  • the trenches 130 are beneficially formed in the structure of FIG. 3 using reactive ion etching, preferably inductively coupled plasma reactive ion etching (ICP RIE).
  • ICP RIE inductively coupled plasma reactive ion etching
  • Forming trenches using ICP RIE has two main steps: forming scribe lines and etching. Scribe lines are formed on the structure of FIG. 3 using a photo-resist pattern in which areas of the sapphire substrate 122 where the trenches 130 are to be formed are exposed. The exposed areas are the scribe lines, while all other areas are covered by photo-resist.
  • the photo-resist pattern is beneficially fabricated from a relatively hard photo-resist material that withstands intense plasma.
  • the photo-resist could be AZ 9260, while the developer used to develop the photo-resist to form the scribe lines could be AZ MIF 500.
  • the photo-resist is beneficially spin coated to a thickness of about 10 microns.
  • the photo-resist thickness should be about the same as the thickness of the vertical topology GaN-based LED layer structure plus the etch depth into the sapphire substrate 122 . This helps ensure that the photo-resist mask remains intact during etching. Because it is difficult to form a thick photo-resist coating in one step, the photo-resist can be applied in two coats, each about 5 microns thick. The first photo-resist coat is spin coated on and then soft baked, for example, at 90° F. for about 15 minutes.
  • the second photo-resist coat is applied in a similar manner, but is soft baked, for example, at 110° F. for about 8 minutes.
  • the photo-resist coating is then patterned to form the scribe lines. This is beneficially performed using lithographic techniques and development. Development takes a relatively long time because of the thickness of the photo-resist coating.
  • the photo-resist pattern is hard baked, for example, at about 80° F. for about 30 minutes.
  • the hard baked photo-resist is beneficially dipped in a MCB (Metal Chlorobenzene) treatment for about 3.5 minutes. Such dipping further hardens the photo-resist.
  • MCB Metal Chlorobenzene
  • the structure of FIG. 3 is etched.
  • the ICP RIE etch process is performed by placing the structure of FIG. 3 on a bottom electrode 132 in a RIE chamber 134 having an insulating window 136 (beneficially a 1 cm-thick quartz window).
  • the bottom electrode 132 is connected to a bias voltage supply 138 that biases the structure of FIG. 3 to enable etching.
  • the bias voltage supply 138 beneficially supplies 13 . 56 MHz RF power and a DC-bias voltage.
  • the distance from the insulating window 136 to the bottom electrode 132 is beneficially about 6.5 cm.
  • a 2.5-turn or so spiral Cu coil 144 is located above the insulating window 136 .
  • Radio frequency (RF) power at 13.56 MHz is applied to the coil 144 from an RF source 146 . It should be noted that magnetic fields are produced at right angles to the insulating window 136 by the RF power.
  • thin p-contacts 150 are formed on the individual LED semiconductor structures of the GaN-based LED layer structure.
  • Those contacts 150 are beneficially comprised of Pt/Au, Pd/Au, Ru/Au, Ni/Au, Cr/Au, or of indium tin oxide (ITO)/Au and are less then 10 nm.
  • Such contacts can be formed using a vacuum evaporator (electron beam, thermal, sputter), followed by thermal annealing at an intermediate temperature (approximately 300-700° C.).
  • the trenches 130 are filled with an easily removed material (beneficially a photo-resist) to form posts 154 .
  • a metal support layer 156 approximately 50 ⁇ m is formed over the posts 154 and over the p-contacts 150 .
  • the posts 154 prevent the metal that forms the metal support layer 156 from entering into the trenches.
  • the metal support layer 156 is beneficially comprised of a metal having good electrical and thermal conductivity and that is easily formed, such as by electroplating, by electro-less plating, by CVD, or by sputtering. Before electroplating or electro-less plating, it is beneficial to coat the surface with a suitable metal, such as by sputtering.
  • the metal support layer 156 can be Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al.
  • the metal support layer 156 can be comprised of a metal-containing material such as titanium nitride.
  • the sapphire substrate 122 is then removed from the remainder of the structure using light 158 from an eximer layer (having a wavelength less than 350 nanometers), while the sapphire substrate is biased away from the remainder of the structure (such as by use of vacuum chucks).
  • the laser beam 158 passes through the sapphire substrate 122 , causing localized heating at the junction of the sapphire substrate 122 and the n-GaN buffer layer 124 . That heat decomposes the GaN at the interface of the sapphire substrate, which, together with the bias, causes the sapphire substrate 122 to separate, reference FIG. 10. It is beneficial to hold the other side of the structure with a vacuum chuck during laser lift off. This enable easy application of a separation bias.
  • the posts 154 are then removed, leaving the trenches 130 behind.
  • FIG. 11 the structure of FIG. 10 is inverted. Then, the side opposite the metal support layer 156 is cleaned with HCl to remove Ga droplets (laser beam 158 heating separates GaN into Ga+N). After cleaning, ICP RIE polishing (using Cl 2 an/or Cl 2 +BCl 3 ) is performed to smooth the exposed surface (which is rough due to the separation of the sapphire substrate). Polishing produces an atomically flat surface of pure n-GaN on the n-GaN buffer layer 124 .
  • n-type ohmic contacts 160 are formed on the n-GaN buffer layer 124 using normal semiconductor-processing techniques. Beneficially, the n-type ohmic contacts 160 are comprised of Ti/Al-related materials.
  • a passivation layer 162 is formed on the n-type ohmic contacts 160 and in the trenches 130 . Electrical insulation comprised Of SiO 2 or Si 3 N 4 are suitable passivation layer materials. Additionally, as shown, the passivation layer 162 is patterned to expose top surface portions of the n-type ohmic contacts 160 .
  • metal pads 164 are formed on the n-type ohmic contacts 160 . As shown in FIG. 14, the metal pads 164 extend over portions of the passivation layer 162 .
  • the metal pads 164 are beneficially comprised of Cr and Au.
  • dicing is beneficially accomplished using photolithographic techniques to etch through the metal support layer 156 to the bottom of the passivation layer 162 (at the bottom of the trenches 130 ) and by removal of the passivation layer 162 .
  • sawing can be used. In practice, it is probably better to perform sawing at less than about 0° C. The result is a plurality of vertical topology GaN LEDs 199 on conductive substrates.
  • trenches 130 before laser lift off of the sapphire substrate 122 .
  • the sapphire substrate 122 could be removed first, and then trenches 130 can be formed.

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US10/118,316 2002-04-09 2002-04-09 Method of fabricating vertical structure leds Abandoned US20030189215A1 (en)

Priority Applications (39)

Application Number Priority Date Filing Date Title
US10/118,316 US20030189215A1 (en) 2002-04-09 2002-04-09 Method of fabricating vertical structure leds
DE60324413T DE60324413D1 (de) 2002-04-09 2003-03-31 Verfahren zur herstellung von vertikalstruktur-leds
JP2003585153A JP5325365B2 (ja) 2002-04-09 2003-03-31 縦方向構造を有するｌｅｄの製作方法
AT03731009T ATE412972T1 (de) 2002-04-09 2003-03-31 Verfahren zur herstellung von vertikalstruktur- leds
EP07013949.8A EP1848026B1 (en) 2002-04-09 2003-03-31 LED having vertical structure
EP10183510.6A EP2261951B1 (en) 2002-04-09 2003-03-31 Method for fabricating an LED having vertical structure
DE20321880U DE20321880U1 (de) 2002-04-09 2003-03-31 LEDS mit vertikaler Struktur
EP14194349.8A EP2860753B1 (en) 2002-04-09 2003-03-31 Vertical structure LEDs
DE20321881U DE20321881U1 (de) 2002-04-09 2003-03-31 LEDS mit vertikaler Struktur
EP14194354.8A EP2860779B1 (en) 2002-04-09 2003-03-31 Vertical-structure light-emitting device
AU2003241280A AU2003241280A1 (en) 2002-04-09 2003-03-31 Method of fabricating vertical structure leds
EP10183473.7A EP2261949B1 (en) 2002-04-09 2003-03-31 LED having vertical structure
EP10183495.0A EP2261950B1 (en) 2002-04-09 2003-03-31 LED having vertical structure and method for fabricating the same
PCT/US2003/009501 WO2003088318A2 (en) 2002-04-09 2003-03-31 Method of fabricating vertical structure leds
EP14194356.3A EP2863444B1 (en) 2002-04-09 2003-03-31 Vertical structure LEDs
EP03731009A EP1502286B1 (en) 2002-04-09 2003-03-31 Method of fabricating vertical structure leds
KR1020047016177A KR100921457B1 (ko) 2002-04-09 2003-03-31 수직 구조의 발광 다이오드 및 그 제조방법
US11/002,413 US7569865B2 (en) 2002-04-09 2004-12-03 Method of fabricating vertical structure LEDs
US11/030,323 US7588952B2 (en) 2002-04-09 2005-01-07 Method of fabricating vertical structure LEDs
US11/232,957 US7563629B2 (en) 2002-04-09 2005-09-23 Method of fabricating vertical structure LEDs
US11/232,956 US7250638B2 (en) 2002-04-09 2005-09-23 Method of fabricating vertical structure LEDs
US11/896,307 US7462881B2 (en) 2002-04-09 2007-08-30 Method of fabricating vertical structure LEDs
US11/896,772 US7576368B2 (en) 2002-04-09 2007-09-05 Method of fabricating vertical structure LEDs
US12/458,703 US7816705B2 (en) 2002-04-09 2009-07-21 Method of fabricating vertical structure LEDs
US12/797,335 US7928465B2 (en) 2002-04-09 2010-06-09 Method of fabricating vertical structure LEDs
US13/047,371 US8384120B2 (en) 2002-04-09 2011-03-14 Method of fabricating vertical structure LEDs
US13/750,376 US8809898B2 (en) 2002-04-09 2013-01-25 Method of fabricating vertical structure LEDs
JP2013077709A JP2013175748A (ja) 2002-04-09 2013-04-03 縦方向構造を有するｌｅｄの製作方法
US14/098,185 US8896017B2 (en) 2002-04-09 2013-12-05 Vertical structure LEDs
US14/496,076 US9224907B2 (en) 2002-04-09 2014-09-25 Vertical structure LEDs
JP2015076060A JP6546432B2 (ja) 2002-04-09 2015-04-02 縦方向構造を有するｌｅｄの製作方法
US14/950,773 US9472727B2 (en) 2002-04-09 2015-11-24 Vertical structure LEDs
US15/261,172 US9882084B2 (en) 2002-04-09 2016-09-09 Vertical structure LEDs
JP2016208006A JP6268259B2 (ja) 2002-04-09 2016-10-24 発光デバイス
US15/831,084 US10243101B2 (en) 2002-04-09 2017-12-04 Vertical structure LEDs
JP2018168460A JP6547047B2 (ja) 2002-04-09 2018-09-10 発光デバイス
US16/268,161 US10461217B2 (en) 2002-04-09 2019-02-05 Vertical structure LEDs
US16/387,312 US10453993B1 (en) 2002-04-09 2019-04-17 Vertical structure LEDs
US16/567,875 US10600933B2 (en) 2002-04-09 2019-09-11 Vertical structure LEDs

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US10/118,316 US20030189215A1 (en) 2002-04-09 2002-04-09 Method of fabricating vertical structure leds

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US11/002,413 Division US7569865B2 (en) 2002-04-09 2004-12-03 Method of fabricating vertical structure LEDs
US11/002,413 Continuation US7569865B2 (en) 2002-04-09 2004-12-03 Method of fabricating vertical structure LEDs
US11/030,323 Division US7588952B2 (en) 2002-04-09 2005-01-07 Method of fabricating vertical structure LEDs
US11/030,323 Continuation US7588952B2 (en) 2002-04-09 2005-01-07 Method of fabricating vertical structure LEDs
US11/896,307 Division US7462881B2 (en) 2002-04-09 2007-08-30 Method of fabricating vertical structure LEDs

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US11/030,323 Expired - Lifetime US7588952B2 (en) 2002-04-09 2005-01-07 Method of fabricating vertical structure LEDs
US11/232,956 Expired - Lifetime US7250638B2 (en) 2002-04-09 2005-09-23 Method of fabricating vertical structure LEDs
US11/232,957 Expired - Lifetime US7563629B2 (en) 2002-04-09 2005-09-23 Method of fabricating vertical structure LEDs
US11/896,307 Expired - Lifetime US7462881B2 (en) 2002-04-09 2007-08-30 Method of fabricating vertical structure LEDs
US11/896,772 Expired - Lifetime US7576368B2 (en) 2002-04-09 2007-09-05 Method of fabricating vertical structure LEDs
US12/458,703 Expired - Fee Related US7816705B2 (en) 2002-04-09 2009-07-21 Method of fabricating vertical structure LEDs
US12/797,335 Expired - Fee Related US7928465B2 (en) 2002-04-09 2010-06-09 Method of fabricating vertical structure LEDs
US13/047,371 Expired - Lifetime US8384120B2 (en) 2002-04-09 2011-03-14 Method of fabricating vertical structure LEDs
US13/750,376 Expired - Lifetime US8809898B2 (en) 2002-04-09 2013-01-25 Method of fabricating vertical structure LEDs
US14/098,185 Expired - Fee Related US8896017B2 (en) 2002-04-09 2013-12-05 Vertical structure LEDs
US14/496,076 Expired - Fee Related US9224907B2 (en) 2002-04-09 2014-09-25 Vertical structure LEDs
US14/950,773 Expired - Lifetime US9472727B2 (en) 2002-04-09 2015-11-24 Vertical structure LEDs
US15/261,172 Expired - Lifetime US9882084B2 (en) 2002-04-09 2016-09-09 Vertical structure LEDs
US15/831,084 Expired - Fee Related US10243101B2 (en) 2002-04-09 2017-12-04 Vertical structure LEDs
US16/268,161 Expired - Fee Related US10461217B2 (en) 2002-04-09 2019-02-05 Vertical structure LEDs
US16/387,312 Expired - Fee Related US10453993B1 (en) 2002-04-09 2019-04-17 Vertical structure LEDs
US16/567,875 Expired - Fee Related US10600933B2 (en) 2002-04-09 2019-09-11 Vertical structure LEDs

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US11/232,956 Expired - Lifetime US7250638B2 (en) 2002-04-09 2005-09-23 Method of fabricating vertical structure LEDs
US11/232,957 Expired - Lifetime US7563629B2 (en) 2002-04-09 2005-09-23 Method of fabricating vertical structure LEDs
US11/896,307 Expired - Lifetime US7462881B2 (en) 2002-04-09 2007-08-30 Method of fabricating vertical structure LEDs
US11/896,772 Expired - Lifetime US7576368B2 (en) 2002-04-09 2007-09-05 Method of fabricating vertical structure LEDs
US12/458,703 Expired - Fee Related US7816705B2 (en) 2002-04-09 2009-07-21 Method of fabricating vertical structure LEDs
US12/797,335 Expired - Fee Related US7928465B2 (en) 2002-04-09 2010-06-09 Method of fabricating vertical structure LEDs
US13/047,371 Expired - Lifetime US8384120B2 (en) 2002-04-09 2011-03-14 Method of fabricating vertical structure LEDs
US13/750,376 Expired - Lifetime US8809898B2 (en) 2002-04-09 2013-01-25 Method of fabricating vertical structure LEDs
US14/098,185 Expired - Fee Related US8896017B2 (en) 2002-04-09 2013-12-05 Vertical structure LEDs
US14/496,076 Expired - Fee Related US9224907B2 (en) 2002-04-09 2014-09-25 Vertical structure LEDs
US14/950,773 Expired - Lifetime US9472727B2 (en) 2002-04-09 2015-11-24 Vertical structure LEDs
US15/261,172 Expired - Lifetime US9882084B2 (en) 2002-04-09 2016-09-09 Vertical structure LEDs
US15/831,084 Expired - Fee Related US10243101B2 (en) 2002-04-09 2017-12-04 Vertical structure LEDs
US16/268,161 Expired - Fee Related US10461217B2 (en) 2002-04-09 2019-02-05 Vertical structure LEDs
US16/387,312 Expired - Fee Related US10453993B1 (en) 2002-04-09 2019-04-17 Vertical structure LEDs
US16/567,875 Expired - Fee Related US10600933B2 (en) 2002-04-09 2019-09-11 Vertical structure LEDs

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