TWI508195B - 晶圓中之順應互連 - Google Patents

晶圓中之順應互連 Download PDF

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Publication number
TWI508195B
TWI508195B TW100145366A TW100145366A TWI508195B TW I508195 B TWI508195 B TW I508195B TW 100145366 A TW100145366 A TW 100145366A TW 100145366 A TW100145366 A TW 100145366A TW I508195 B TWI508195 B TW I508195B
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TW
Taiwan
Prior art keywords
substrate
microelectronic unit
conductive
microelectronic
joint
Prior art date
Application number
TW100145366A
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English (en)
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TW201246413A (en
Inventor
Vage Oganesian
Belgacem Haba
Ilyas Mohammed
Piyush Savalia
Craig Mitchell
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Tessera Inc
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Application filed by Tessera Inc filed Critical Tessera Inc
Publication of TW201246413A publication Critical patent/TW201246413A/zh
Application granted granted Critical
Publication of TWI508195B publication Critical patent/TWI508195B/zh

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    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

晶圓中之順應互連
本發明係關於堆疊微電子總成及製造此等總成之方法，且係關於在此等總成中有用的組件。
常提供半導體晶片作為個別、封裝單元。一標準晶片具有擁有一前表面之一平坦、矩形本體，該前表面具有連接至該晶片之主動電路之若干接觸件。各個別晶片通常安裝於一封裝中，該封裝繼而安裝於一電路板(諸如，一印刷電路板)上且將該晶片之接觸件連接至該電路板之導體。在許多習知設計中，該晶片封裝佔有遠大於該晶片自身之面積之電路板之一面積。如本發明參考具有一前表面之一平坦晶片所使用，「晶片之面積」應理解為係指該前表面之面積。
在「覆晶」設計中，該晶片之前表面面向一封裝基板之一表面(亦即，一晶片載體)，及該晶片上的接觸件係藉由焊球或其他連接元件直接結合至該晶片載體之接觸件。繼而，該晶片載體可透過覆蓋該晶片之前表面之端子結合至一電路板。該「覆晶」設計提供一相對緊密之配置；各晶片佔有等於或稍大於該晶片之前表面之面積之該電路板之一面積，例如，諸如共同讓與之美國專利第5,148,265號、第5,148,266號及第5,679,977號之某些實施例中所揭示，該等案之揭示內容以引用的方式併入本文中。
除了最小化由微電子總成佔有之電路板之平面面積外， 亦期望產生存在垂直於該電路板之平面之一低整體高度或尺寸之一晶片封裝。此等薄微電子封裝容許具有安裝於其內之封裝之一電路板緊密接近於相鄰結構而放置，因此減少併入該電路板之產品之整體大小。
亦已提出封裝一「堆疊」配置(亦即，複數個晶片彼此重疊放置之一配置)中的複數個晶片。在一堆疊配置中，若干晶片可安裝於小於該等晶片之總面積之該電路板之一面積中。某些堆疊晶片配置係揭示於(例如)前述美國專利第5,148,265號、第5,679,977號及美國專利第5,347,159號之某些實施例中，該等案之揭示內容以引用的方式併入本文中。亦以引用的方式併入本文中的美國專利第4,941,033號揭示晶片彼此互相堆疊且藉由與該等晶片相關聯之所謂「佈線膜」上的導體彼此互連之一配置。
習知晶片接觸件可由於接觸件上的一非最佳化應力分佈及一半導體晶片與(例如)晶片所結合之結構之間的熱膨脹係數(CTE)之一不匹配而具有可靠性挑戰。例如，當一半導體晶片之一表面上的導電接觸件係藉由一相對較薄且勁性之介電質材料而絕緣時，該等接觸件上可存在明顯的應力。此外，當半導體晶片結合至一聚合基板之導電元件時，晶片與基板之較高CTE結構之間的電連接將經受由於CTE不匹配而引起之應力。
大小在晶片之任意實體配置中係一重要考慮因素。隨著可攜式電子裝置之快速發展，更緊密之晶片實體配置之需求已變得更強烈。僅以實例之方式，常稱為「智慧型電 話」之裝置整合一蜂巢式電話與高效資料處理器、記憶體及輔助裝置(諸如，全球定位系統接收器、電子照相機及區域網路連接以及高解析度顯示器及相關影像處理晶片)之功能。此等裝置可提供諸如全網際網路連接、包含全解析度視訊之娛樂、航空、電子銀行業及更多之能力，所有皆在一口袋型裝置中。複雜的可攜式裝置需要將許多個晶片封裝至一小空間中。此外，該等晶片之一些具有許多輸入及輸出連接，常稱為「I/O」。此等I/O必須與其他晶片之I/O互連。該等互連應為短的且應具有低阻抗以最小化信號傳播延遲。形成該等互連之組件不應大幅增加總成之大小。類似需求亦發生於其他應用中，例如，發生於(諸如)用於網際網路搜尋引擎之資料伺服器中。例如，提供複雜晶片之間的許多短小、低阻抗之互連之結構可增加該搜尋引擎之頻寬且減少其之功率消耗。
儘管半導體接觸件形成及互連得到了提升，然亦需要進行改良以最小化半導體晶片之大小，同時增強電互連可靠性。本發明之此等屬性係藉由如下文所描述之微電子封裝之構造而達成。
根據本發明之一態樣，一種微電子總成可包含一基板及一導電元件。該基板可具有小於10ppm/℃之一CTE、具有不延伸穿過該基板之一凹部之一主要表面及安置於該凹部內之具有小於10GPa之一彈性模數之一材料。該導電元件可包含覆蓋該凹部且自藉由該基板支撐之一錨定部延伸之 一接合部。該接合部可至少部分曝露於該主要表面以連接至該微電子單元之外之一組件。
在一實施例中，該基板可具有小於7ppm/℃之一CTE。在一特定實施例中，該接合部可移動以便減少(諸如)可於操作、製造或測試微電子單元期間存在之該接合部上的應力。在一例示性實施例中，該基板實質上可由自半導體、玻璃及陶瓷組成之群組選擇之一材料組成。在一實施例中，該基板可包含複數個主動半導體裝置及該導電元件可與該複數個主動半導體裝置之至少一者電連接。在一特定實施例中，安置於該凹部內的材料可包含自聚醯亞胺、聚矽氧及環氧樹脂組成之群組選擇之至少一材料。
在一例示性實施例中，該凹部可不延伸穿過該基板。在一實施例中，該接合部可在實質上平行於該基板之主要表面之一方向上延伸。在一特定實施例中，該錨定部及該接合部可在相同方向上延伸。在一例示性實施例中，該導電元件可與朝向與該主要表面相對之該基板之一第二表面延伸之一導通體電耦合。在一實施例中，該導通體可曝露於該第二表面。在一特定實施例中，該導通體可延伸於自該第二表面延伸至該主要表面之該基板中的一孔內。
在一實施例中，該孔可包含自該主要表面朝向該第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口。該第一開口及該第二開口之內表面分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。在一例示性實施例中，一堆疊總成可包含至少第 一微電子單元及第二微電子單元，該第二微電子單元堆疊有該第一微電子單元，其中該第一微電子單元之基板於其內與該第二微電子單元之一基板電連接。在一特定實施例中，該堆疊總成可進一步包含電耦合至該第一微電子單元之接合部之一導電塊(conductive mass)及該第二微電子單元之一導電元件。
根據本發明之另一態樣，一種微電子總成可包含一基板及一導電元件。該基板可具有小於10ppm/℃之一CTE、具有不延伸穿過該基板之一凹部之一主要表面及安置於該凹部內之具有小於10GPa之一彈性模數之一材料。該導電元件可具有相對於該基板而固定之一錨定部、至少部分覆蓋該凹部之一接合部及自該接合部向下延伸至該錨定部之一連接部。該接合部可在遠離該錨定部之一方向上延伸且可曝露於該主要表面以連接至微電子單元之外之一組件。該連接部可具有不符合該凹部之內表面之一輪廓之一輪廓。
在一例示性實施例中，該基板可具有小於7ppm/℃之一CTE。在一實施例中，該接合部可移動以便減少(諸如)可於操作、製造或測試微電子單元期間存在之該接合部上的應力。在一特定實施例中，該基板實質上可由自半導體、玻璃及陶瓷組成之群組選擇之一材料組成。在一實施例中，該基板可包含複數個主動半導體裝置，及該導電元件可與該複數個主動半導體裝置之至少一者電連接。在一例示性實施例中，該連接部可延伸至該凹部中。
在一特定實施例中，該導電元件可與朝向與該主要表面 相對之該基板之一第二表面延伸之一導通體電耦合。在一實施例中，該導通體可曝露於該第二表面。在一例示性實施例中，該導通體可延伸於自該第二表面延伸至該主要表面之該基板中的一孔內。在一特定實施例中，該孔可包含自該主要表面朝向該第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口。該第一開口及該第二開口之內表面分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。在一實施例中，該錨定部可具有符合該孔之一內表面之一輪廓之一輪廓。在一例示性實施例中，該接合部可界定一內部孔隙。
在一實施例中，該孔隙可延伸穿過該接合部至該連接部中。在一特定實施例中，該孔隙之至少一部分可填充有一介電質材料。在一例示性實施例中，一堆疊總成可包含至少第一微電子單元及第二微電子單元，該第二微電子單元堆疊有該第一微電子單元，其中該第一微電子單元之基板於其內與該第二微電子單元之一基板電連接。在一特定實施例中，該堆疊總成可進一步包含電耦合至該第一微電子單元之接合部一導電塊及該第二微電子單元之一導電元件。
根據本發明之又一態樣，一種製作一微電子單元之方法可包含如下步驟：形成支撐於具有小於10ppm/℃之一CTE之一基板之一主要表面上的一導電元件；自該主要表面移除支撐該導電元件之至少一接合部之材料以形成不延伸穿過該基板之一凹部；及將一材料沈積於具有小於10GPa之 一彈性模數之凹部內。該接合部可不藉由該基板支撐，而鄰近該接合部之該導電元件之一錨定部可藉由該基板支撐。該接合部可至少部分曝露於該基板之主要表面以連接至該微電子單元之外之一組件。
在一實施例中，該基板可具有小於7ppm/℃之一CTE。在一例示性實施例中，該基板實質上可由自半導體、玻璃及陶瓷組成之群組選擇之一材料組成。在一特定實施例中，該基板可包含複數個主動半導體裝置，及形成該導電元件之步驟可以該複數個主動半導體裝置之至少一者而與該導電元件電連接。在一例示性實施例中，可執行形成該導電元件之步驟使得該接合部係實質上平行於該主要表面而安置。在一實施例中，該方法可進一步包含如下步驟：自該基板移除材料以形成自該主要表面延伸至與該主要表面相對之該基板之一第二表面之一孔，及形成延伸於該孔內之一導通體使得該導通體與該導電元件電耦合且朝向該第二表面延伸。
在一特定實施例中，自該基板移除材料以形成一孔之步驟可包含形成自該主要表面朝向該第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口。該第一開口及該第二開口之內表面可分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。在一實施例中，一種製作包含至少第一微電子單元及第二微電子單元之一堆疊總成之方法可進一步包含將該第一微電子單元之基板電連接至該第二微電子單元之一基板之步驟。
根據本發明之又一態樣，一種製作一微電子單元之方法可包含如下步驟：自具有小於10ppm/℃之一CTE之一基板移除材料以形成自該基板之一主要表面延伸至與該主要表面相對之一第二表面之一孔；形成具有延伸於該主要表面之上且支撐於該主要表面上之一接合部之一導電元件、相對於該基板固定之一錨定部及自該接合部向下延伸至該錨定部之一連接部；自該主要表面移除支撐該導電元件之至少一接合部之材料以形成一凹部使得該接合部至少部分覆蓋該凹部；及將一材料沈積於具有小於10GPa之一彈性模數之該凹部內。該連接部之一表面可具有符合該孔之一內表面之一輪廓之一輪廓。該連接部之表面之輪廓可不符合該凹部之一內表面之一輪廓。該接合部可至少部分曝露於該基板之主要表面以連接至該微電子單元之外之一組件。
在一特定實施例中，該基板可具有小於7ppm/℃之一CTE。在一例示性實施例中，製作一微電子單元之方法可進一步包含：在形成導電元件之步驟之前，形成延伸於孔內且朝向第二表面延伸之一導通體，使得形成該導電元件之步驟藉由該導通體與該導電元件電耦合。在一實施例中，可執行形成導電元件之步驟使得接合部相對於連接部非居中。在一特定實施例中，該基板實質上可由自半導體、玻璃及陶瓷組成之群組選擇之一材料組成。在一例示性實施例中，該基板可包含複數個主動半導體裝置，及形成該導電元件之步驟可藉由該複數個主動半導體裝置之至少一者而與該導電元件電連接。在一實施例中，可執行形 成該導電元件之步驟使得該接合部界定一內部孔隙。在一特定實施例中，可執行形成該導電元件之步驟使得該孔隙延伸穿過該接合部至該連接部中。
在一實施例中，製作一微電子單元之方法可進一步包含將一介電質材料沈積至該孔隙之至少一部分中之步驟。在一特定實施例中，自基板移除材料以形成一孔之步驟可包含形成自主要表面朝向第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口。該第一開口及該第二開口之內表面可分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。在一例示性實施例中，一種製作包含至少第一微電子單元及第二微電子單元之一堆疊總成之方法可進一步包含將該第一微電子單元之基板電連接至該第二微電子單元之一基板之步驟。
本發明之進一步態樣提供併入根據本發明之前述態樣之微電子結構、根據本發明之前述態樣之複合晶片或兩者與其他電子裝置結合之系統。例如，該系統可安置於一單一外殼中，該單一外殼可為一可攜式外殼。根據本發明之此態樣中的較佳實施例之系統比相稱習知系統更緊密。
本發明之進一步態樣提供可包含根據本發明之前述態樣之複數個微電子總成之模組。各模組可具有用於傳輸信號至該等微電子總成之各者及自該等微電子總成之各者傳輸信號之一共同電介面。
參考圖1A，根據本發明之一實施例之一堆疊微電子總成 10包含一第一微電子單元12及一第二微電子單元14。在一些實施例中，該第一微電子單元12及該第二微電子單元14可為一半導體晶片、一晶圓、一介電質基板或類似物。例如，該第一微電子單元12及該第二微電子單元14之一者或兩者可包含一記憶體儲存元件。如本文所使用，一「記憶體儲存元件」係指連同用於儲存資料及自記憶體單元擷取資料(諸如，用於在一電介面上傳輸資料)之電路以一陣列配置之多個記憶體單元。
該第一微電子單元12包含：一基板20，該基板20具有一凹部30，該凹部30自一主要表面21朝向一第二表面22部分延伸穿過該基板；及一導電元件40，該導電元件40具有藉由該基板支撐之一錨定部41、自該錨定部延伸之一接合部42及一端部46，該接合部42至少部分覆蓋該凹部30且至少部分曝露於該主要表面以與該第一微電子單元之外之一組件互連。如展示，該端部46位於該接合部42之一端上。一介電質區域50至少覆蓋該凹部30內的一內表面31。
在圖1A中，平行於該主要表面21之方向在本文稱為「水平」或「橫向」方向，而垂直於前表面之方向在本文稱為向上或向下方向且亦在本文稱為「垂直」方向。本文中所指之方向係在所指之結構之參考系(frame of reference)中。因此，此等方向對於正常或重力參考系可處於任意定向。相較於另一特徵部，一特徵部安裝於「一表面之上」之一較高高度上之一陳述意謂：相較於另一特徵部，一特徵部在遠離表面之相同正交方向上具有一較大距離。相 反，相較於另一特徵部，一特徵部安裝於「一表面之上」之一較低高度上之一陳述意謂：相較於其他特徵部，一特徵部在遠離該表面之相同正交方向上具有一較小距離。
基板20較佳具有小於10×10-6 /℃(或ppm/℃)之一熱膨脹係數(「CTE」)。在一特定實施例中，該基板20可具有小於7×10-6 /℃(或ppm/℃)之一熱膨脹係數(「CTE」)。該基板20實質上較佳由諸如半導體、玻璃或陶瓷之一材料組成。在該基板20係由一半導體(諸如，聚矽氧)製成之實施例中，複數個主動半導體裝置(例如，電晶體、二極體等)可安置於位於該主要表面21或該第二表面22上或之下之一主動半導體區域中。該主要表面21與該第二表面22之間的該基板20之厚度通常為小於200微米，及可顯著更小，例如，130微米、70微米或甚至更小。
該基板20可進一步包含安置於該主要表面21與至少一導電元件40之間的一介電層。一介電層可覆蓋該第二表面22。此一介電層可使導電元件與該基板20電絕緣。此等介電層之一者或兩者可稱為該第一微電子單元12之一「鈍化層」。該介電層可包含一有機或無機介電質材料或兩者。該介電層可包含一電鍍保形塗層或其他介電質材料，例如，一可光成像聚合材料(例如，一焊料遮罩材料)。
該第一微電子單元12可包含曝露於該基板20之主要表面21之一或多個導電元件40。各導電元件40之接合部42可曝露於該主要表面21以與該第一微電子單元12之外之一組件(諸如，第二微電子元件14)互連。儘管圖中未具體展示， 然該基板20中的主動半導體裝置亦可導電連接至該接合部42。因此，該等主動半導體裝置可透過延伸於該基板20之一或多個介電層內或之上之所併入之佈線而導電接達。該等導電元件40(及本文所描述之其他導電元件之任意者)可由任意導電金屬(包含(例如)銅或金)製成。
例如，如展示，在圖1C中，接合部42'可具有一導電結合墊(例如，一薄平坦構件)之仰視圖形狀。各接合部42可具有任意仰視圖形狀，其包含(例如)如圖1B中所展示之一矩形跡線形狀、如圖1C中所展示之圓形墊形狀、橢圓形狀、正方形形狀、三角形形狀或更複雜形狀。在其他實施例中，該接合部42可為任意其他類型之導電接觸件，其包含(例如)一導電柱。
該接合部42可與凹部30對準且可整體或部分安置於由該凹部界定之該基板20之一區域中。如圖1A可見，該接合部42係整體安置於由該凹部30界定之一區域中。如展示，由該接合部42之一頂表面43界定之一平面實質上平行於由該基板20之主要表面21界定之一平面。如展示。該接合部42之一底表面44位於由該基板20之主要表面21界定之一平面上。在其他實施例中，該接合部42之底表面44可位於由該主要表面21界定之平面之上或之下。該導電元件40之端部46未藉由該基板20支撐，使得該端部可相對於該錨定部41懸掛在外。覆蓋該主要表面21及鄰近於該介電質區域50而定位之該接合部42之此一未支撐之端部46可相對於該經支撐之錨定部41自由移動，使得該接合部42可用作一懸臂。
如本發明中所使用，一導電元件「曝露於」一基板之一表面或覆蓋該基板之一表面之一介電質元件之一陳述指示：該導電元件係用於與以垂直於該介電質元件之表面自該介電質元件之外部朝向該介電質元件之一方向移動之一理論點接觸。因此，曝露於一介電質元件之一表面之一端子或其他導電元件可自此表面突出；可與此表面同高；或可相對於此表面凹進及透過該介電質中的一孔或凹陷曝露。
儘管實質上用於形成導電元件之任意技術可用於形成本文所描述之導電元件，然亦可利用如更詳細討論於2010年7月23日申請之共同擁有之美國專利申請案第12/842,669號中的特定技術，該案以引用的方式併入本文中。此等技術可包含(例如)以一雷射或機械程序(諸如，銑切或噴沙)選擇性處理一表面以便沿著不同於該表面之其他部分形成導電元件之路徑處理該表面之該等部分。例如，一雷射或機械程序可用於僅沿著一特定路徑自該表面切除或移除一材料(諸如，一犧牲層)且因此形成沿著該路徑延伸之一凹槽。接著，一材料(諸如，一催化劑)可沈積於該凹槽中，及一或多個金屬層亦可沈積於該凹槽中。
該導電元件40之端部46在圖中展示為非橫向(亦即，以平行於該基板20之主要表面21之一方向)延伸超過該凹部30之外邊界32(見圖1B)。在本文所揭示之實施例之任意者中，導電元件之端部及/或接合部可橫向延伸超過凹部之外邊界。在一實施例中，接合部之一端可耦合至橫向延伸 超過對應凹部之外邊界之一導電跡線(未展示)，但該接合部亦可以下文所描述之方式相對於對應基板而移動。
該凹部30自該主要表面21朝向該第二表面22部分延伸穿過該基板20。該凹部30之內表面31以任意角度自該主要表面21延伸穿過該基板20。較佳地，該內表面31以介於0度與90度之間的一角度自該主要表面21延伸至由該主要表面21界定之水平面。該內表面31可具有一恆定斜率或一變化斜率。例如，隨著該內表面31進一步朝向該第二表面22貫穿時，相對於由該主要表面21界定之水平面之該內表面31之角度或斜率可呈量值減少(亦即，變為弱正或弱負)。
該凹部30可具有任意仰視圖形狀，其包含(例如)如圖1B中所展示之一橢圓形或如圖1C中所展示之一圓形。在圖1B中所展示之實施例中，凹部30在沿著該主要表面21之一第一橫向方向上具有一寬度W，及該凹部在橫向於該第一橫向方向之沿著該主要表面之一第二橫向方向上具有一長度L，該長度大於該寬度。在一些實例中，該凹部30可具有任意三維形狀，其除了其他以外亦包含(例如)一圓柱體形狀、一立方體形狀、一稜柱形狀或一截頭圓錐體形狀。
在一特定實施例中，如圖1D中所展示，該凹部30可為具有至少部分覆蓋該凹部之複數個接合部42之一矩形通道。任意數量之接合部42可覆蓋一單一凹部30，及該等接合部可以覆蓋一單一凹部之任意幾何組態配置。例如，如圖1D中所示，三個接合部42可沿著覆蓋一單一凹部30之一共同軸配置。
在所展示之實施例中，該介電質區域50填充該凹部30使得該介電質區域之一輪廓符合該凹部之一輪廓(亦即，該凹部之內表面31之形狀)。該介電質區域50可相對於該基板20提供良好的介電隔離。該介電質區域50可為順應，具有一足夠低之彈性模數及足夠的厚度使得該彈性模數及該厚度之乘積提供順應性。較佳地，該導電元件40之接合部42至少部分覆蓋該介電質區域50。當一外部負載施加至該接合部時，一順應介電質區域50可容許該導電元件40之接合部42相對於該基板20及支撐於其上之該導電元件之錨定部41稍微撓曲或移動。以此方式，該第一微電子單元12之接合部42與該第二微電子單元14之端子之間之結合能更好地經受由於該第一微電子單元與該第二微電子單元之間的熱膨脹係數(「CTE」)之不相配所引起之熱應力。
如本文結合一導電元件之一接合部所使用，「可移動」意謂接合部可藉由施加至其之一外部負載相對於基板之主要表面位移至一定程度以致該位移可略微減緩或減少機械應力，諸如，與不具有此位移之導電元件電連接而存在之於操作、製造或測試微電子單元期間所引起之該等應力。
藉由介電質區域50之厚度與其彈性模數之乘積所提供之順應度可足以對由於第一微電子單元12與該第一微電子單元透過接合部安裝之第二微電子單元14之間的熱膨脹不相配所引起之施加至接合部42之應力作補償。一側填滿料(未展示)可提供於該介電質區域50之一外表面51與此第二微電子單元14之間以增強對由於CTE不相配所引起之熱應 力之阻抗。
在所展示之實施例中，該介電質區域50之外表面51(圖1A)係位於由該基板20之主要表面21界定之一平面內。替代地，該介電質區域50之外表面51可延伸於由該基板20之主要表面21界定之一平面之上，或該介電質區域之外表面可凹陷低於由該基板之主要表面界定之一平面。
一介電層25可覆蓋基板20之主要表面21及不為接合部42之導電元件40之部分以相對於該基板及不為接合部之該等導電元件之部分提供良好的介電隔離。該介電層25可包含一無機或有機介電質材料或兩者。在一特定實施例中，該介電層25可包含與介電質區域50相同之順應介電質材料。在一例示性實施例中，可藉由該介電質區域50連續形成該介電層25。
第二微電子單元14可包含一基板15及至少部分曝露於該基板之一主要表面17以與第一微電子單元12之接合部42互連之導電接觸件16a及16b。藉由提供該第一微電子單元12中的接合部42及該第二微電子單元14中的背面導電接觸件14，複數個微電子單元可彼此互相堆疊以形成堆疊微電子總成10。在此配置中，該等接合部42與該等導電接觸件16a及16b對準。
如圖1A中所展示，該導電接觸件16a為一導電柱。該導電柱16a可為任意類型之導電柱且可具有任意形狀，其包含一截頭圓錐形狀。各導電柱16a之基座及頂端實質上可為圓形或具有一不同形狀(例如，長方形)。可使用導電柱 之其他實例，如展示及描述於2010年7月8日申請之共同擁有之美國專利申請案第12/832,376號中。導電接觸件16b展示為一導電墊。該導電墊16b可具有任意形狀，其包含圓形形狀、正方向形狀、長方形形狀、矩形形狀或一更複雜形狀。
該第一微電子單元12與該第二微電子單元14之間的連接可穿過導電塊18。基板20之主要表面21上的介電層25及介電質區域50及覆蓋基板15之主要表面17之一介電層(例如，一鈍化層)除了提供互連外亦可提供第一微電子單元12與第二微電子單元14之間的電隔離。
導電塊18可包括具有一相對較低之熔融溫度之一可溶金屬(例如，焊料、錫或包含複數個金屬之一共熔混合物(eutectic mixture))。替代地，該等導電塊18可包含一可濕金屬(例如，銅或具有高於焊料或另一可熔金屬之熔融溫度之一熔融溫度之其他貴金屬或非貴金屬)。此可濕金屬可與一對應特徵部(例如，一互連元件(諸如，第二微電子單元14)之一可熔金屬特徵部)接合以將第一微電子單元12外部互連至此互連元件。在一特定實施例中，該等導電塊18可包含散佈於一媒介(例如，一導電膏(例如，金屬填充膏、焊料填充膏或同向導電黏著劑或異向導電黏著劑))中的一導電材料。
參考圖2A至圖2D，現將描述一種製作微電子總成10(圖1A至圖1D)之方法。如圖2A中所繪示，第一微電子單元12包含基板20及覆蓋主要表面21之一或多個導電元件40。該 等導電元件40可藉由一介電層(諸如，一鈍化層(未展示))與該基板20絕緣。
在圖2B中所繪示之製作階段中，一介電層25形成於基板20之主要表面21上且充當期望保留該主要表面之剩餘部分之一蝕刻遮罩層，其中。例如，該介電層25可為一可光成像層(例如，一光阻層)，其經沈積且圖案化以在實行一定時蝕刻程序以形成凹部30之後僅覆蓋該主要表面21之部分。各導電元件40之接合部42可維持至少部分曝露於該主要表面21(亦即，未藉由該介電層25覆蓋)以連接至該第一微電子單元12之外之一組件。
可使用各種方法來形成該介電層25。在一實例中，將一流動介電質材料施加至該基板20之主要表面21，及接著在一旋塗操作期間接著可包含加熱之一乾燥循環使該流動材料跨該主要表面更均勻分佈。在另一實例中，介電質材料之一熱塑膜可在加熱或於一真空環境(亦即，置於低於周圍壓力之一環境中)中加熱總成之後施加至該主要表面21。在另一實例中，可使用蒸汽沈積以形成該介電層25。
在又一實例中，包含基板20之總成可浸入一介電質沈積浴液中以形成一保形介電質塗層或介電層25。如本文所使用，一「保形塗層」為符合塗覆之表面之一輪廓(諸如，當該介電層25符合該主要表面21之一輪廓時)之一特定材料之一塗層。可使用一種電化學沈積方法以形成該保形介電層25，其包含(例如)電泳沈積或電解沈積。
在一實例中，可使用一電泳沈積技術以形成保形介電質 塗層，使得該保形介電質塗層僅沈積於總成之曝露導電及半導電表面上。在沈積期間，半導體裝置晶圓保持在一所需電位上，及將一電極浸入至浴液中以保持該浴液處於一不同所需電位上。接著，該總成在適當條件下保持在該浴液中一足夠時間以在為導電或半導電之基板之曝露表面(包含但不限於沿著該主要表面21)上形成一電沈積保形介電層25。只要於藉此塗覆之表面與該浴液之間維持一足夠強之電場，就能發生電泳沈積。當由於電泳沈積達到由參數(例如，沈積之電壓、濃度等)控管之某一厚度塗層之後而自身限制時，沈積停止。
電泳沈積在該總成之導電及/或半導電外表面上形成一連續且均勻厚度之保形塗層。此外，可沈積該電泳塗層使得歸因於其介電質(非導電)性質，而未形成在覆蓋該主要表面21之一剩餘鈍化層上。換句話說，電泳沈積之一性質在於，其，倘若覆蓋一導體之一介電質材料層具有足夠厚度、給定其介電質材料，則電泳沈積不形成在該介電質材料層上。通常，電泳沈積不發生於具有大於約10微米至幾十微米之厚度之介電層上。可由一陰極環氧沈積前驅物形成該保形介電層25。替代地，可使用一聚胺基甲酸酯或丙烯酸沈積前驅物。各種電泳塗層前驅組合物及供應來源列於下文表1中。
在另一實例中，可電解形成介電層。此程序類似於電泳沈積，惟經沈積之層之厚度未受限於接近形成其之導電或半導電表面除外。以此方式，一電解沈積介電層可形成為基於需求而選擇之一厚度，及處理時間為達成該厚度之一因數。
隨後，在圖2C中所繪示之製作階段中，凹部30可經形成而自該主要表面21朝向該基板20之第二表面22向下延伸。例如，可在形成期望保留該主要表面21之剩餘部分之一遮罩層(例如，介電層25)之後，藉由選擇性蝕刻該基板20以移除該基板之材料而形成該凹部30。該凹部30可經形成使得移除支撐至少接合部42之該基板20之材料。
如圖2C中所展示，可使自該主要表面21朝向該第二表面22向下延伸之該凹部30之內表面31傾斜，亦即，可以除了與該主要表面成一垂直角(直角)之外的角度延伸。除了其他之外，濕蝕刻程序(例如，同向蝕刻程序及使用一錐形刀片之鋸切)可用於形成具有傾斜內表面31之凹部30。除了其他之外，雷射切除、機械銑切、化學蝕刻、電漿蝕刻、朝向該基板20引導一細小磨料粒子噴流亦可用於形成具有傾斜內表面31之凹部30(或本文所描述之任意其他孔或開口)。
替代地，該凹部30之內表面可在一垂直或實質上垂直方向上實質上以與該主要表面成直角自該主要表面21向下延伸，而非傾斜。除了其他之外，各向異性蝕刻程序、雷射切除、機械移除程序(例如，銑切、超音波加工、朝向該 基板20引導一細小磨料粒子噴流)可用於形成具有實質上垂直之內表面之凹部30。
隨後，在圖2D中所繪示之製作階段中，於該凹部30內形成介電質區域50。該介電質區域50可包含一無機材料、一聚合材料或兩者。視情況，該介電質區域50可經形成使得該區域之曝露外表面51與基板20之主要表面21或介電層25之一曝露表面共面或實質上共面。例如，一自平坦化介電質材料可(例如)藉由一施配或模板網印程序沈積於該凹部30中。在另一實例中，在形成該介電質區域50之後，一研磨、研光或拋光程序可運用於該基板20之主要表面21或該介電層25之曝露表面，以使該介電質區域50之表面平坦化至該主要表面21或該介電層25之曝露表面。
隨後，再參考圖1A，第一微電子單元12可堆疊於第二微電子單元14之頂上，藉此形成堆疊微電子總成10。如上文所描述，該第一微電子單元12與該第二微電子單元14之間的連接方式可為透過導電塊18。該等導電塊18可提供該第一微電子單元12之接合部42與該第二微電子單元14之導電接觸件16a及16b之間的一電連接。在此配置中，該等接合部42與該等導電接觸件16a及16b對準。
現參考圖3A，根據本發明之另一實施例之一堆疊微電子總成110包含一第一微電子單元112及一第二微電子單元114。該等微電子單元112及114具有與上文所描述之該等微電子單元12及14類似之功能。
該第一微電子單元112包含一基板120，該基板120具有 一凹部130a及130b，凹部自一主要表面121朝向與該主要表面相對之一第二表面122部分延伸穿過該基板；及導電元件140a及140b，各導電元件具有藉由該基板支撐之一各自錨定部141a及141b、至少部分覆蓋該各自凹部130a或130b且至少部分曝露於該主要表面以與該第一微電子單元之外之一組件互連之一各自接合部142a或142b、延伸於該錨定部與接合部之間的一或多個各自連接部145a或145b，及若干端部146。如展示，該等端部146位於各接合部142a及142b之一端。一介電質區域150覆蓋至少在該凹部130a或130b內之一內表面131。
該基板120進一步包含自開口130延伸至該第二表面122之一孔160及在該孔內自該各自錨定部141a或141b延伸至該第二表面之一導通體170。該導通體170包含曝露於該第二表面122以與該堆疊微電子總成110之外之一組件互連之一接觸部180。
該基板120具有與上文參考圖1A至圖2D所描述之基板20類似之性質。例如，該基板120較佳具有小於10ppm/℃之一CTE，及該基板120較佳實質上由一材料(諸如，一半導體、玻璃或陶瓷)組成。在該基板120係由一半導體(諸如，矽)製成之實施例中，複數個主動半導體裝置可安置於其內。該基板120可進一步包含覆蓋該主要表面121及/或該第二表面122之一介電層(例如，一「鈍化層」)。
該微電子元件112可包含曝露於該基板120之主要表面121之一或多個導電元件140a及140b。該等各自導電元件 140a及140b之接合部142a及142b可曝露於該主要表面121以與該第一微電子單元112之外之一組件(諸如，第二微電子單元114)互連。該基板120中的主動半導體裝置可導電連接至該等接合部142a及142b。
各接合部142a及142b可具有任意仰視圖形狀。如展示，例如，在圖3B中，該等接合部142a及142b可具有一導電結合墊(例如，一薄平坦構件或一導電結合墊之一部分)之形狀。例如，圖3B及圖3C中所展示之接合部142b具有一圓形、實心仰視圖形狀。圖3B中所展示之接合部142a具有擁有延伸穿過其中之一孔隙147之一圓形仰視圖形狀。圖3C中所展示之接合部區段142a'共同具有擁有延伸穿過其中之孔隙147及延伸於鄰近接合部區段之間之間隙148之一圓形仰視圖形狀。
該等接合部142a及142b可具有其他仰視圖形狀，其包含(例如)一矩形跡線形狀或矩形跡線形狀部分。例如，圖3D中所展示之接合部142b"具有一矩形跡線形狀。圖3D中所展示之接合部142a"為具有位於其中之孔隙147之矩形跡線形狀部分。替代地，該等接合部142a及142b可具有更複雜形狀。在其他實施例中，該等接合部142a及142b可為任意其他類型之導電接觸件，其包含(例如)一導電柱。
該等接合部142a及142b可與該各自凹部130a或130b對準且可整體或部分安置於由該凹部界定之基板120之一區域中。如圖3A中可見，該等接合部142a及142b係整體安置於由該各自凹部130a或130b界定之一區域中。如展示，由該 等各自接合部142a或142b之頂表面143a及143b界定之一平面實質上平行於由該基板120之主要表面121界定之一平面。如展示，該等各自接合部142a或142b之底表面144a及144b係位於由該基板120之主要表面121界定之一平面上。在其他實施例中，該等底表面144a及144b可位於由該主要表面121界定之平面之上或之下。
該等連接部145a及145b自該等各自接合部142a或142b向下延伸至該各自錨定部141a或141b。該等連接部145a及145b之至少一部分具有不符合該各自凹部130a或130b之內表面131之一輪廓之一輪廓。在一特定實施例中，可有自該錨定部141b延伸至該接合部142b之一單一跡線形狀連接部145b。在替代實施例中，可具有自該錨定部延伸之任意數量之連接部。例如，在一實施例中，諸如於圖3B中所展示之實施例中，該連接部145a可具有擁有一內孔隙147之一空心截頭圓錐形狀。在另一實施例中，可具有延伸於一單一錨定部141a與各自接合部(諸如，圖3C中所展示之接合部142a')之間的四個個別連接部。在又一實施例中，可具有延伸於一單一錨定部141a與各自接合部(諸如，圖3D中所展示之接合部142a")之間的兩個個別連接部。該等接合部142a及142b較佳相對於該等各自連接部145a或145b不居中，使得該各自導電元件140a或140b之端部146可相對於該各自錨定部141a或141b懸掛在外。
該等凹部130a及130b類似於上文參考圖1A至圖2D所展示及描述之凹部30。該等凹部130a及130b自該主要表面 121朝向該第二表面122部分延伸穿過該基板120。該等凹部130a及130b之內表面131可以任意角度自該主要表面121延伸穿過該基板120。較佳地，該等內表面131以0度與90度之間的一角度自該主要表面121延伸至由該主要表面121界定之水平平面。
該等凹部130a及130b可具有任意仰視圖形狀，其包含(例如)一橢圓形(諸如，圖3B至圖3D中所展示之凹部130b)或一圓形(諸如，圖3B及圖3C中所展示之凹部130a)。在一些實施例中，該等凹部130a及130b可具有任意三維形狀，除了其他之外亦包含(例如)圓柱體形狀、立方體形狀、稜柱形狀或截頭圓錐形狀。在一特定實施例中，在類似於圖1D中所展示之該等接合部42之組態之一組態中，該等凹部130a及130b可為具有至少部分覆蓋該凹部之複數個各自接合部142a及142b之一矩形通道。
介電質區域150具有與上文參考圖1A至圖2D所展示及描述之介電質區域50類似之可能組態及性質。例如，在圖3A至圖3D中所展示之實施例中，該介電質區域150填充該等凹部130a及130b使得該介電質區域之一輪廓符合該凹部之一輪廓(亦即，該等凹部之內表面131之形狀)。該介電質區域150可為順應，其具有一足夠低之彈性模數及足夠之厚度使得該彈性模數及該厚度之乘積提供順應性。較佳地，該等接合部142a及142b至少部分覆蓋該介電質區域150使得該等接合部可相對於該基板120移動。
類似於上文參考圖1A至圖2D所描述之介電層25，一介 電層125可覆蓋該基板120之主要表面121及不為接合部142a及142b之導電元件140a及140b之部分，以相對於該基板及不為接合部之該導電元件之部分提供良好的介電隔離。
如圖3A至圖3D中所展示，階化孔160，該孔160包含自開口130朝向第二表面122延伸之一第一開口161及自該第一開口延伸至該第二表面之一第二開口162。該階化孔160可具有更詳細展示且描述於2010年7月23日申請之共同擁有之美國專利申請案第12/842,717號及共同擁有之美國專利申請公開案第2008/0246136號中的任意結構，該等案以引用的方式併入本文中。在其他實施例中，孔(諸如，參考圖6所展示及描述之孔60b)可具有一更簡單非階化結構。
該第一開口161自該凹部130朝向該第二表面122部分延伸穿過該基板120。該第一開口161包含以0度與90度之間的一角度自該凹部130延伸穿過該基板120至由該主要表面121界定之水平平面之若干內表面163。該等內表面163可具有一恆定斜率或一變化斜率。例如，當該等內表面163進一步朝向該第二表面122貫穿時，該等內表面163相對於由該主要表面121界定之水平平面之角度或斜率可呈量值減少(亦即，變為弱正或弱負)。如展示，例如，在圖4D中，該第一開口161具有在該凹部130處的一寬度W1及在該第一開口交會小於W1之第二開口162處的一寬度W2，使得該第一開口在自該主要表面121朝向該第二表面122之一 方向上漸縮。在其他實例中，該第一開口可具有一恆定寬度，或該第一開口可在自該第二表面朝向前表面之一方向上漸縮。該第一開口161可具有任意三維形狀，其除了其他之外亦包含(例如)立方體、圓柱體、截頭圓錐體或稜柱。
該第二開口162自該第一開口161朝向該第二表面122部分延伸穿過該基板120。該第二開口162包含以0度與90度之間的一角度自該第一開口161延伸穿過該基板120至由該主要表面121界定之水平平面之若干內表面164。類似於上文所描述之內表面163，該等內表面164可具有一恆定斜率或一變化斜率。如展示，例如，在圖4D中，該第二開口162具有在該第二開口交會該第一開口161處的一寬度W3及在大於W3之該第二表面122處的一寬度W4，使得該第一開口在自該第二表面122朝向該主要表面121之一方向上漸縮。在其他實例中，該第二開口可具有一恆定寬度，或該第二開口可在自前表面朝向該第二表面之一方向上漸縮。該第二開口162可具有任意三維形狀，其除了其他之外亦包含(例如)立方體、圓柱體、截頭圓錐體或稜柱。
在一特定實施例中，該等內表面163及164可分別在相對於該主要表面121之第一方向及第二方向上延伸以界定一實質角度。任意數量之第一開口161可自一單一第二開口162延伸，及任意數量之第二開口可自一單一第一開口延伸。第一開口161及該等第二開口162可相對於彼此及相對於該基板120以任意幾何組態配置。各種第一開口組態及 第二開口組態及形成此等組態之方法之特定實例係描述於前述共同擁有之美國專利申請案第12/842,717號及美國專利申請公開案第2008/0246136號中。
該等各自導電元件140a及140b之錨定部141a及141b較佳具有符合該各自第一開口161之一輪廓之輪廓，使得該等錨定部具有相對於該基板120而固定之位置。一錨定部141a或141b可用作一支點，一附接接合部142a或142b在處於(諸如，由關於一附接微電子單元之差異熱膨脹所引起之)機械應力下時可關於該支點樞轉。
導通體170延伸穿過該各自錨定部141a或141b與該第二表面122之間的孔160。如圖3A中所展示，該導通體170可填充可使該基板120與該導通體電絕緣之一選用之介電層(未展示)之內側之第二開口162內的所有體積。該導通體170可符合該第二開口162之輪廓。該導通體170可具有一圓柱形狀或截頭圓錐形狀。該導通體170可由一金屬(包含(例如)銅或金)或一金屬之導電化合物製成。
在其他實施例中(未展示)，導通體170之一輪廓(亦即，該導通體之外表面之形狀)不符合第二開口162之一輪廓(亦即，該第二開口之內表面164之形狀)。在此非保形導通體實施例中，該導通體170可具有任意形狀，其包含(例如)圓柱形狀、截頭圓錐形狀，或距離第二表面122不同距離之圓柱形狀及截頭圓錐形狀之組合。
該導通體170可為實心或空心。在一些實施例中，該導通體可包含填充有一介電質材料之一內部空間。例如，可 藉由沈積覆蓋該第二開口162之內表面164之一金屬而形成該導通體170，藉此產生覆蓋該第二開口之內表面之一導電層。各種導通體組態及形狀此等組態之方法之特定實例係描述於前述共同擁有之美國專利申請案第No.12/842,717號及美國專利申請公開案第2008/0246136號中。
該等導通體170各包含曝露於該第二表面122以與堆疊微電子總成110之外之一組件互連之一接觸部180。在一些實施例中，各導通體170可電耦合至曝露於該第二表面122之一分離導電接觸件。
第二微電子單元114類似於上文參考圖1A所展示及描述之第二微電子單元14。該第二微電子單元114可包含一基板115及至少部分曝露於該基板之一主要表面117以與第一微電子單元112之接合部142a及142b互連之導電接觸件116。
如圖3A中所展示，該等導電接觸件116為導電墊。該等導電墊116可具有任意形狀，其包含圓形、正方形、長方形、矩形或更複雜形狀。在特定實施例中，該等導電接觸件116可為任意類型之導電接觸件，其包含(例如)一導電柱，諸如，圖1A中所展示之導電柱16a。如於2010年7月8日申請之共同擁有之美國專利申請案第12/832,376號中所展示及描述，可使用導電柱之其他實例。
該第一微電子單元112與該第二微電子單元114之間的連接可以類似於參考圖1A至圖2D所描述之方式之一方式穿 過導電塊118。基板120之主要表面121上的介電層125及介電質區域150及覆蓋該基板115之主要表面117之一介電層(例如，一鈍化層)除了提供互連外亦可提供該第一微電子單元112與該第二微電子單元114之間的電隔離。
參考圖4A至圖4D，現將描述製作微電子總成110(圖3A至圖3D)之一方法。在圖4A中所繪示之製作階段中，第一微電子單元112包含基板120。可藉由自該基板移除材料而形成自主要表面121延伸至該基板120之第二表面122之孔160。在一特定實施例中，可形成自該主要表面121向內延伸之第一開口161，及可形成自該第二表面122向內延伸之第二開口。在其他實施例中，可由該主要表面121或該第二表面122形成該第一開口161及該第二開口162之任一者或兩者。
可如上文關於形成凹部30所描述之一類似方式且使用類似程序形成該等孔160。例如，可在形成期望保留該主要表面121之剩餘部分之一遮罩層之後藉由選擇性蝕刻該基板120以移除該基板之材料而形成該等孔160，其中。類似於該凹部30，該第一開口161之內表面163及該第二開口162之內表面164可相對於該主要表面121以任意恆定或變化角度延伸。
儘管未展示，一介電層可視情況形成於基板120之主要表面121上及/或覆蓋第一開口161之內表面163及第二開口162之內表面164以提供導電元件140a及140b及導通體170與該基板之電隔離。可使用上文參考圖2B中所展示之介電 層25所描述之各種方法之任意者而形成此一介電層。此一介電層可另外為或取代為已覆蓋基板120之主要表面121之一鈍化層。
在圖4B中所繪示之製作階段中，可於第一開口161內形成導電元件140a及140b之錨定部141a及141b及各自連接部145a及145b，可形成覆蓋主要表面121之接合部142a及142b，及可於第二開口162內形成導通體170，其中接觸部180曝露於第二表面122。可以單一金屬沈積程序或分離程序而形成該等錨定部141a及141b、該等連接部145a及145b、該等接合部142a及142b及該等導通體170之各者。在該等導通體170係電耦合至曝露於該第二表面122之分離導電接觸件之一實施例中，此等導電接觸件可連同該等導電元件140a及140b及該等導通體以一單一金屬沈積程序予以形成，或可以一分離程序形成此等導電接觸件。
形成該等導電元件140a及140b及該等導通體170之一例示性方法包含：藉由將一主要金屬層濺鍍至該基板120之曝露表面上、電鍍或機械沈積之一或多者而沈積一金屬層。機械沈積可包含：以高速將一加熱金屬粒子流引導至待塗覆之表面上。例如，此步驟可藉由毯覆沈積至該主要表面121及該等內表面163及164中而執行。在一實施例中，該主要金屬層包含鋁或實質上由鋁組成。在另一特定實施例中，該主要金屬層包含銅或實質上由銅組成。在又一實施例中，該主要金屬層包含鈦或實質上由鈦組成。一或多種其他例示性金屬可用於一程序中以形成導電元件 140a及140b及導通體170。在特定實例中，包含複數個金屬層之一堆疊可形成於前述表面之一或多個上。例如，此堆疊金屬層可包含一層鈦，接著覆蓋該鈦之一層銅(Ti-Cu)，一層鎳，接著一層覆蓋該鎳層之一層銅(Ni-Cu)，以類似方式設置之一鎳-鈦-銅(Ni-Ti-Cu)堆疊，或(例如)一鎳-釩堆疊。
在一特定實施例中，例如，如圖2A中所繪示之製作階段所展示，在自基板移除任意材料之前，接合部142a及142b可沈積至基板120之主要表面121上。在此一實施例中，例如，可藉由蝕刻穿過該等接合部142a及/或142b且接著蝕刻至該基板120中形成孔160。在形成穿過該等接合部142a及/或142b之孔160之後，可如上文所描述形成連接部145a及145b、錨定部141a及141b，及導通體170。
在圖4C中所繪示之製作階段中，介電層125係形成於基板120之主要表面121上且用作期望保留該主要表面之剩餘部分之一蝕刻遮罩層。可使用上文參考圖2B中所展示之介電層25所描述之各種方法之任意者而形成該介電層125。該等接合部142a及142b可維持至少部分曝露於該主要表面121(亦即，未由該介電層125覆蓋)以連接至第一微電子單元112之外之一組件。
隨後，在圖4D中所繪示之製作階段中，可如上文關於形成凹部30所描述之一類似方式及使用類似程序形成凹部130。例如，可在形成期望保留該主要表面121之剩餘部分之一遮罩層(例如，介電層25)之後，藉由選擇性地蝕刻該 基板120以移除該基板之材料而形成該等凹部130。該凹部130可經形成使得移除支撐至少接合部142a及142b之基板120之材料。類似於凹部30，該等凹部130之內表面131可以相對於該主要表面121之任意恆定或變化角度延伸。
如圖4D中所展示，該等凹部130可經形成使得其等自該主要表面121的延伸不似該等第一開口161一樣遠，使得該等錨定部141a及141b之輪廓符合該第一開口之內表面163之剩餘部分之一輪廓。在一特定實施例中，該等凹部130可經形成使得其自該主要表面121延伸至少與該等第一開口161一樣遠，使得該等錨定部141a及141b之輪廓不致符合該基板120之任意內表面之輪廓。在此一實施例中，該等錨定部141a及141b可透過該等錨定部與可具有符合該等第二開口162之內表面164之輪廓之輪廓之導通體170之間的附接而固定至該基板120。
隨後，在圖4E中所繪示之製作階段中，可如上文關於在凹部30內形成介電質區域50所描述之一類似方式及使用類似程序而於凹部130之內側形成介電質區域150。例如，該介電質區域150可經形成使得該區域之一曝露外表面151與該基板120之主要表面121(如圖4E中所展示)或該介電層125之一曝露表面共面或實質上共面。
隨後，再參考圖3A，第一微電子單元112可堆疊於第二微電子單元114之頂部上，藉此形成堆疊微電子總成110。如上文所描述，該第一微電子單元112與該第二微電子單元114之間的連接可穿過導電塊118。該等導電塊118可提 供該第一微電子單元112之接合部142a及142b與該第二微電子單元114之導電接觸件116之間的一電連接。在此配置中，該等接合部142a及142b與該等各自導電接觸件116對準。
如圖5中所展示，展示一導電元件240之一基座部241及一接合部242，其適用於上文參考圖1A至圖4E所描述之任意實施例中。該接合部242自該導電元件240之基座部241延伸。該基座部241可為(例如)上文參考圖3A中所展示之第一微電子單元112所描述之接合部142a及142b之部分，或上文參考圖1A中所展示之第一微電子單元12所描述之錨定部41之部分。該基座部241可連接至位於基板220之主要表面221之下或介電質區域250之一外表面251之下之其他導電元件。在圖5中所展示之實施例中，該基座部241包含為順應或可在由該主要表面221界定之一平板之一方向上移動之一區段243，使得該區段可藉由施加至其之一外部負載在沿著該主要表面221之一方向上位移。
現參考圖6，根據另一實施例之一第一微電子總成12'類似於圖1A中所展示之第一微電子總成12，惟導電元件40'電連接至延伸於基板20'之主要表面21與第二表面22之間的導通體70a及70b除外。
該基板20'包含自該主要表面21及該第二表面22延伸之孔60a及60b，及導通體70a及70b於該等各自孔內自該等導電元件40'之各自錨定部41'延伸至該第二表面。各導通體70a及70b包含曝露於該第二表面22以與該第一微電子單元 12'之外之一組件互連之一接觸部80。該孔60a為類似於展示於圖3A中的孔160之一階化孔，惟開口30未與該等孔60a或60b之任一者重疊除外，因此該等孔60a及60b自該第二表面22延伸至該主要表面21，而非自該第二表面延伸至一各自開口。該孔60b未階化，亦即，可(例如)以自該基板20'移除材料之一單一蝕刻或其他程序而形成該孔60b。
類似於圖1A中所展示之第一微電子總成12，各導電元件40'包含可曝露於該主要表面21以與該第一微電子單元12'之外之一組件互連之一接合部42。亦類似於第一微電子單元12，介電質區域50可為順應，使得各接合部42可相對於該基板20'移動。
圖7描繪包含以一單元一起配置之至少兩個微電子總成310之一模組300，其具有用於傳輸信號之該等微電子總成310之各者且自該等微電子總成310之各者傳輸信號之一電介面320。該電介面可包含用於傳輸信號或參考電位(例如，電源及接地)之一或多個接觸件，其等為其內之微電子元件之各者所共有。該等微電子總成310可為上文所描述之總成之任意者。在一特定實例中，該模組300可為一雙列記憶體模組(「DIMM」)或單列記憶體模組(「SIMM」)，其具有經調整大小用於入至(諸如)可設置於一主機板上之一系統之其他連接器之一對應插槽中之一或多個部分。在此DIMM或SIMM中，該電介面可具有適於與此插槽連接器內的複數個對應彈力接觸件相配之接觸件330。此彈力接觸件可安置於各插槽之單一或多個側上以 與對應模組接觸件相配。各種其他模組及互連配置係可能的，其中一模組可具有非堆疊或堆疊微電子總成，或其可具有並列電介面或串列電介面，或用於傳輸電信號至該模組及自該模組傳輸電信號之並列電介面及串列電介面之一組合。藉由本發明可預期該模組300與一進一步系統之間的任意種類之電互連配置。
如圖8中所展示，上文所描述之微電子總成可用於建構多種電子系統。例如，根據本發明之一進一步實施例之一系統400包含結合其他電子組件408及410之如上文所描述之一微電子總成406。在所描繪之實例中，組件408為一半導體晶片，而組件410為一顯示螢幕，但亦可使用任意其他組件。當然，儘管為了繪示之簡潔，於圖8中僅描繪兩個額外組件，然該系統可包含任意數量之此組件。該微電子總成406可為上文所描述之總成之任意者。在一進一步變量中，可使用任意數量之此等微電子總成。
微電子總成406及組件408及410係安裝於一共同外殼401(示意性地以虛線描繪)中，且視需要彼此電互連以形成所需電路。在所展示之例示性系統中，該系統包含一電路板402(諸如，一撓性印刷電路板)，且該電路板包含許多導體404，圖8中僅描繪該等導體之一者，該等組件彼此互連。然而，此僅為例示性，可使用用於製成電連接之任意合適結構。
該外殼401係描繪為用於(例如)一蜂巢式電話或個人數位助理之一可攜式外殼類型，及螢幕410曝露於該外殼之 表面。在結構406包含一光敏感元件(諸如，一成像晶片)之情況下，一透鏡411或其他光學裝置亦可提供用於將光投送至該結構。此外，圖8中所展示之簡化系統僅為例示性；可使用上文所描述之結構製作其他系統，包含統稱為固定結構(諸如，桌上型電腦、路由器及類似物)之系統。
可藉由(諸如)更詳細揭示於2010年7月23日申請之同在申請中共同讓與之美國專利申請案第12/842,587號、第12/842,612號、第12/842,651號、第12/842,669號、第12/842,692號及第12/842,717號中及公開之美國專利申請公開案第2008/0246136號中的該等程序而形成揭示於本文中的導通體及導通孔導體，該等案之揭示內容以引用的方式併入本文中。
儘管本發明在本文中已參考特定實施例予以描述，然應理解，此等實施例僅繪示本發明之原理及應用。因此，應理解，可對繪示性實施例作許多修改且可在不脫離如由隨附申請專利範圍界定之本發明之精神及範疇之情況下想出其他配置。
應瞭解，闡釋於其中之各種獨立申請專利範圍及特徵可以不同於初始申請專利範圍中所存在之方式之方式組合。亦應瞭解，組合個別實施例所描述之特徵可與該等所描述之實施例之其他特徵共用。
10‧‧‧堆疊微電子總成
12‧‧‧第一微電子單元
12'‧‧‧第一微電子總成
14‧‧‧第二微電子單元/第二微電子元件
15‧‧‧基板
16a‧‧‧導電接觸件/導電柱
16b‧‧‧導電接觸件/導電柱
17‧‧‧主要表面
18‧‧‧導電塊
20‧‧‧基板
20'‧‧‧基板
21‧‧‧主要表面
22‧‧‧第二表面
25‧‧‧介電層
30‧‧‧凹部/開口
31‧‧‧內表面
32‧‧‧外邊界
40‧‧‧導電元件
40'‧‧‧導電元件
41‧‧‧錨定部
41'‧‧‧錨定部
42‧‧‧接合部
42'‧‧‧接合部
43‧‧‧頂表面
44‧‧‧底表面
46‧‧‧端部
50‧‧‧介電質區域
51‧‧‧外表面
60a‧‧‧孔
60b‧‧‧孔
70a‧‧‧導通體
70b‧‧‧導通體
80‧‧‧接觸部
110‧‧‧微電子總成
112‧‧‧第一微電子單元/微電子元件
114‧‧‧第二微電子單元
115‧‧‧基板
116‧‧‧導電接觸件
117‧‧‧主要表面
118‧‧‧導電塊
120‧‧‧基板
121‧‧‧主要表面
122‧‧‧第二表面
125‧‧‧介電層
130‧‧‧凹部/開口
130a‧‧‧凹部
130b‧‧‧凹部
131‧‧‧內表面
140a‧‧‧導電元件
140b‧‧‧導電元件
141a‧‧‧錨定部
141b‧‧‧錨定部
142a‧‧‧接合部
142b‧‧‧接合部
142a'‧‧‧接合部區段
142a"‧‧‧接合部
142b"‧‧‧接合部
143a‧‧‧頂表面
143b‧‧‧頂表面
144a‧‧‧底表面
144b‧‧‧底表面
145a‧‧‧連接部
145b‧‧‧連接部
146‧‧‧端部
147‧‧‧孔隙
148‧‧‧間隙
150‧‧‧介電質區域
151‧‧‧外表面
160‧‧‧孔
161‧‧‧第一開口
162‧‧‧第二開口
163‧‧‧內表面
164‧‧‧內表面
170‧‧‧導通體
180‧‧‧接觸部
220‧‧‧基板
221‧‧‧主要表面
240‧‧‧導電元件
241‧‧‧基座部
242‧‧‧接合部
243‧‧‧區段
250‧‧‧介電質區域
251‧‧‧外表面
300‧‧‧模組
310‧‧‧微電子總成
320‧‧‧電介面
330‧‧‧接觸件
400‧‧‧系統
401‧‧‧外殼
402‧‧‧電路板
404‧‧‧導體
406‧‧‧微電子總成/結構
408‧‧‧電子組件
410‧‧‧電子組件/螢幕
411‧‧‧透鏡
L‧‧‧長度
W‧‧‧寬度
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧寬度
W4‧‧‧寬度
圖1A係繪示根據本發明之一實施例之具有一接觸結構之一堆疊總成之一側視截面圖。
圖1B係沿著線A-A截取之圖1A之堆疊總成之一對應仰視截面圖之一實施例。
圖1C係沿著線A-A截取之圖1A之堆疊總成之一對應仰視截面圖之另一實施例。
圖1D係沿著線A-A截取之圖1A之堆疊總成之一對應仰視截面圖之又一實施例。
圖2A至圖2D係繪示圖1A中所描繪之根據本發明之實施例之製作階段之截面圖。
圖3A係繪示根據本發明之一實施例之具有一接觸結構之一堆疊總成之一側視截面圖。
圖3B係沿著線B-B截取之圖3A之堆疊總成之一對應仰視截面圖之一實施例。
圖3C係沿著線B-B截取之圖3A之堆疊總成之一對應仰視截面圖之另一實施例。
圖3D係沿著線B-B截取之圖3A之堆疊總成之一對應仰視截面圖之又一實施例。
圖4A至圖4E係繪示圖3A中所描繪之根據本發明之實施例之製作階段之截面圖。
圖5係根據本發明之具有與一晶片電連接之一墊之一基板之一俯視透視圖。
圖6係繪示根據本發明之另一實施例之具有一接觸結構之一基板之一側視截面圖。
圖7係根據本發明之一實施例之一模組之一示意圖。
圖8係根據本發明之一實施例之一系統之一示意圖。
10‧‧‧堆疊微電子總成
12‧‧‧第一微電子單元/第一微電子元件
14‧‧‧第二微電子單元/第二微電子元件
15‧‧‧基板
16a‧‧‧導電接觸件/導電柱
16b‧‧‧導電接觸件/導電柱
17‧‧‧主要表面
18‧‧‧導電塊
20‧‧‧基板
21‧‧‧主要表面
22‧‧‧第二表面
25‧‧‧介電層
30‧‧‧凹部
40‧‧‧導電元件
41‧‧‧錨定部
42‧‧‧接合部
43‧‧‧頂表面
44‧‧‧底表面
46‧‧‧端部
50‧‧‧介電質區域
51‧‧‧外表面

Claims (36)

  1. 一種微電子單元，其包括：實質上是由半導體材料所組成之一基板、具有一凹部之一主要表面及安置於該凹部內之具有小於10GPa之一彈性模數之一材料，該凹部延伸在該主要表面下方且不延伸穿過該基板；及一導電元件，其包含一接合部，該接合部覆蓋該凹部且自由該基板支撐之一錨定部延伸至覆蓋該凹部且不由該基板支撐之一端部，以使得該端部可相對於該錨定部懸掛在外，該端部以平行於該主要表面之一橫向方向而不延伸超過該凹部之外邊界，該接合部至少部分曝露於該主要表面以連接至該微電子單元之外之一組件。
  2. 如請求項1之微電子單元，進一步包含設置在該基板之該主要表面及該導電元件之該錨定部之間的一介電層。
  3. 如請求項1之微電子單元，其中該接合部可移動以便減少在操作、製造或測試該微電子單元期間之該接合部上的應力。
  4. 如請求項1之微電子單元，其中該凹部定義具有一變化斜率的一內表面，以使得隨著該內表面進一步朝向該基板之相對於該主要表面之一第二表面延伸時，相對於該主要表面之該內表面之角度呈量值減少。
  5. 如請求項1之微電子單元，其中該基板包含複數個主動半導體裝置，並且該導電元件與該複數個主動半導體裝置之至少一者電連接。
  6. 如請求項1之微電子單元，其中安置於該凹部內的該材料包含自聚醯亞胺、聚矽氧及環氧樹脂組成之群組選擇之至少一材料。
  7. 如請求項1之微電子單元，其中該導電元件之該端部係鄰近於設置在該凹部內之材料。
  8. 如請求項1之微電子單元，其中該接合部在實質上平行於該基板之該主要表面之一方向上延伸。
  9. 如請求項1之微電子單元，其中該錨定部及該接合部在相同方向上延伸。
  10. 如請求項9之微電子單元，其中該導電元件與朝向與該主要表面相對之該基板之一第二表面延伸之一導通體電耦合。
  11. 如請求項10之微電子單元，其中該導通體曝露於該第二表面。
  12. 如請求項10之微電子單元，其中該導通體延伸於自該第二表面延伸至該主要表面之該基板中的一孔內。
  13. 如請求項12之微電子單元，其中該孔包含自該主要表面朝向該第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口，其中該第一開口及該第二開口之內表面分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。
  14. 如請求項11之微電子單元，其中該導通體在介於該導電元件之該錨定部與該第二表面之間的基板中延伸穿過一孔。
  15. 一種堆疊總成，其包含至少第一微電子單元及第二微電子單元，該第一微電子單元係如請求項1之微電子單元，該第二微電子單元堆疊有該第一微電子單元，其中該第一微電子單元之基板於其內與該第二微電子單元之一基板電連接，其進一步包含電耦合至該第一微電子單元之接合部一導電塊及該第二微電子單元之一導電元件。
  16. 一種微電子系統，其包括如請求項1之微電子單元及電連接至該微電子單元之一或多個其他電子組件，其進一步包括一外殼，該微電子單元及該等其他電子組件安裝至該外殼。
  17. 一種微電子模組，其包含如請求項1之複數個微電子單元，該微電子模組具有用於將信號傳輸至該等微電子單元之各者及自該等微電子單元之各者傳輸信號之一共同電介面。
  18. 一種製作一微電子單元之方法，其包括：形成支撐於具有小於10ppm/℃之一CTE之一基板之一主要表面上的一導電元件；自該主要表面移除支撐該導電元件之至少一接合部之材料以形成不延伸穿過該基板之一凹部，使得該接合部未藉由該基板支撐，而鄰近該接合部之該導電元件之一錨定部係藉由該基板支撐；及將一具有小於10GPa之一彈性模數之材料沈積於該凹部內， 其中該接合部至少部分曝露於該基板之該主要表面以連接至該微電子單元之外之一組件。
  19. 如請求項18之方法，其中該基板具有小於7ppm/℃之一CTE。
  20. 如請求項18之方法，其中該基板實質上由自半導體、玻璃及陶瓷組成之群組選擇之一材料組成。
  21. 如請求項18之方法，其中該基板包含複數個主動半導體裝置，及形成該導電元件之步驟藉由該複數個主動半導體裝置之至少一者而與該導電元件電連接。
  22. 如請求項18之方法，其中執行形成該導電元件之步驟使得該接合部係實質上平行於該主要表面而安置。
  23. 如請求項18之方法，其進一步包括：自該基板移除材料以形成自該主要表面延伸至與該主要表面相對之該基板之一第二表面之一孔；及形成延伸於該孔內之一導通體使得該導通體與該導電元件電耦合且朝向該第二表面延伸。
  24. 如請求項23之方法，其中自該基板移除材料以形成一孔之步驟包含：形成自該主要表面朝向該第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口，其中該第一開口及該第二開口之內表面分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。
  25. 一種製作包含至少第一微電子單元及第二微電子單元之一堆疊總成之方法，該第一微電子單元如請求項18而製 作，其進一步包括將該第一微電子單元之該基板電連接至該第二微電子單元之一基板之步驟。
  26. 一種製作一微電子單元之方法，其包括：自具有小於10ppm/℃之一CTE之一基板移除材料以形成自該基板至一主要表面延伸至與該主要表面相對之一第二表面之一孔；形成具有延伸在該主要表面之上且支撐於該主要表面上之一接合部之一導電元件、相對於該基板而固定之一錨定部及自該接合部向下延伸至該錨定部之一連接部，該連接部之一表面具有符合該孔之一內表面之一輪廓之一輪廓；自該主要表面移除支撐該導電元件之至少一接合部之材料以形成一凹部使得該接合部至少部分覆蓋該凹部，及使得該連接部之該表面之該輪廓不符合該凹部之一內表面之一輪廓；及將一具有小於10GPa之一彈性模數之材料沈積於該凹部內，其中該接合部至少部分曝露於該基板之該主要表面以連接至該微電子單元之外之一組件。
  27. 如請求項26之方法，其中該基板具有小於7ppm/℃之一CTE。
  28. 如請求項26之方法，其進一步包括：在形成該導電元件之步驟之前，形成延伸於該孔內且朝向該第二表面延伸之一導通體，使得形成該導電元件之步驟藉由該導通體 與該導電元件電耦合。
  29. 如請求項26之方法，其中執行形成該導電元件之步驟使得該接合部相對於該連接部非居中。
  30. 如請求項26之方法，其中該基板實質上由自半導體、玻璃及陶瓷組成之群組選擇之一材料組成。
  31. 如請求項26之方法，其中該基板包含複數個主動半導體裝置，及形成該導電元件之步驟藉由該複數個主動半導體裝置之至少一者而與該導電元件電連接。
  32. 如請求項26之方法，其中執行形成該導電元件之步驟使得該接合部界定一內部孔隙。
  33. 如請求項32之方法，其中執行形成該導電元件之步驟使得該內部孔隙延伸穿過該接合部至該連接部中。
  34. 如請求項33之方法，其進一步包括將一介電質材料沈積至該內部孔隙之至少一部分中。
  35. 如請求項26之方法，其中自該基板移除材料以形成一孔之步驟包含：形成自該主要表面朝向該第二表面延伸之一第一開口及自該第一開口延伸至該第二表面之一第二開口，其中該第一開口及該第二開口之內表面分別在相對於該主要表面之第一方向及第二方向上延伸以界定一實質角度。
  36. 一種製作包含至少第一微電子單元及第二微電子單元之一堆疊總成之方法，該第一微電子單元如請求項26而製作，其進一步包括將該第一微電子單元之該基板電連接至該第二微電子單元之一基板之步驟。
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US9224649B2 (en) 2015-12-29
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