TWI560785B - A microelectornic unit nad method of fabricating thereof - Google Patents
A microelectornic unit nad method of fabricating thereofInfo
- Publication number
- TWI560785B TWI560785B TW104130730A TW104130730A TWI560785B TW I560785 B TWI560785 B TW I560785B TW 104130730 A TW104130730 A TW 104130730A TW 104130730 A TW104130730 A TW 104130730A TW I560785 B TWI560785 B TW I560785B
- Authority
- TW
- Taiwan
- Prior art keywords
- microelectornic
- fabricating
- unit
- nad method
- nad
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US12/962,806 US8610264B2 (en) | 2010-12-08 | 2010-12-08 | Compliant interconnects in wafers |
Publications (2)
Publication Number | Publication Date |
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TW201601226A TW201601226A (zh) | 2016-01-01 |
TWI560785B true TWI560785B (en) | 2016-12-01 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011014584A1 (de) * | 2011-03-21 | 2012-09-27 | Osram Opto Semiconductors Gmbh | Anschlussträger für Halbleiterchips und Halbleiterbauelement |
EP2889901B1 (en) | 2013-12-27 | 2021-02-03 | ams AG | Semiconductor device with through-substrate via and corresponding method |
US9356009B2 (en) | 2014-05-27 | 2016-05-31 | Micron Technology, Inc. | Interconnect structure with redundant electrical connectors and associated systems and methods |
CN104035222A (zh) * | 2014-06-13 | 2014-09-10 | 京东方科技集团股份有限公司 | 阵列基板、显示面板和显示装置 |
TWI560818B (en) * | 2014-12-05 | 2016-12-01 | Siliconware Precision Industries Co Ltd | Electronic package and the manufacture thereof |
US9899236B2 (en) * | 2014-12-24 | 2018-02-20 | Stmicroelectronics, Inc. | Semiconductor package with cantilever pads |
US11652036B2 (en) * | 2018-04-02 | 2023-05-16 | Santa Clara | Via-trace structures |
US10651157B1 (en) * | 2018-12-07 | 2020-05-12 | Nanya Technology Corporation | Semiconductor device and manufacturing method thereof |
KR20210053537A (ko) | 2019-11-04 | 2021-05-12 | 삼성전자주식회사 | 반도체 패키지 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003020404A (ja) * | 2001-07-10 | 2003-01-24 | Hitachi Ltd | 耐熱性低弾性率材およびそれを用いた装置 |
US20060071347A1 (en) * | 2004-10-04 | 2006-04-06 | Sharp Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
Family Cites Families (259)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4074342A (en) | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
JPS60160645U (ja) | 1984-03-30 | 1985-10-25 | 日野自動車株式会社 | トラツクのオ−デイオ装置 |
NL8403613A (nl) | 1984-11-28 | 1986-06-16 | Philips Nv | Elektronenbundelinrichting en halfgeleiderinrichting voor een dergelijke inrichting. |
US4765864A (en) | 1987-07-15 | 1988-08-23 | Sri International | Etching method for producing an electrochemical cell in a crystalline substrate |
EP0316799B1 (en) | 1987-11-13 | 1994-07-27 | Nissan Motor Co., Ltd. | Semiconductor device |
JPH02174255A (ja) | 1988-12-27 | 1990-07-05 | Mitsubishi Electric Corp | 半導体集積回路装置 |
CA2051765C (en) | 1990-09-20 | 1996-05-14 | Shigetomo Matsui | High pressure injection nozzle |
US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5229647A (en) | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
US5322816A (en) | 1993-01-19 | 1994-06-21 | Hughes Aircraft Company | Method for forming deep conductive feedthroughs |
US5380681A (en) | 1994-03-21 | 1995-01-10 | United Microelectronics Corporation | Three-dimensional multichip package and methods of fabricating |
IL110261A0 (en) | 1994-07-10 | 1994-10-21 | Schellcase Ltd | Packaged integrated circuit |
GB2292015B (en) | 1994-07-29 | 1998-07-22 | Plessey Semiconductors Ltd | Trimmable inductor structure |
US6826827B1 (en) | 1994-12-29 | 2004-12-07 | Tessera, Inc. | Forming conductive posts by selective removal of conductive material |
JP3186941B2 (ja) | 1995-02-07 | 2001-07-11 | シャープ株式会社 | 半導体チップおよびマルチチップ半導体モジュール |
US5703408A (en) | 1995-04-10 | 1997-12-30 | United Microelectronics Corporation | Bonding pad structure and method thereof |
US6284563B1 (en) | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US6013948A (en) | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US5686762A (en) | 1995-12-21 | 1997-11-11 | Micron Technology, Inc. | Semiconductor device with improved bond pads |
TW343210B (en) | 1996-01-12 | 1998-10-21 | Matsushita Electric Works Ltd | Process for impregnating a substrate, impregnated substrate and products thereof |
US5808874A (en) | 1996-05-02 | 1998-09-15 | Tessera, Inc. | Microelectronic connections with liquid conductive elements |
US5700735A (en) | 1996-08-22 | 1997-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bond pad structure for the via plug process |
JP3620936B2 (ja) | 1996-10-11 | 2005-02-16 | 浜松ホトニクス株式会社 | 裏面照射型受光デバイスおよびその製造方法 |
US6143396A (en) | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
JP3725300B2 (ja) | 1997-06-26 | 2005-12-07 | 松下電器産業株式会社 | Acf接合構造 |
US6573609B2 (en) | 1997-11-25 | 2003-06-03 | Tessera, Inc. | Microelectronic component with rigid interposer |
EP0926723B1 (en) | 1997-11-26 | 2007-01-17 | STMicroelectronics S.r.l. | Process for forming front-back through contacts in micro-integrated electronic devices |
US6620731B1 (en) | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
JP3447941B2 (ja) | 1998-01-05 | 2003-09-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
TW410392B (en) | 1998-01-23 | 2000-11-01 | Rohm Co Ltd | Damascene interconnection and semiconductor device |
US6982475B1 (en) | 1998-03-20 | 2006-01-03 | Mcsp, Llc | Hermetic wafer scale integrated circuit structure |
JP4207033B2 (ja) * | 1998-03-23 | 2009-01-14 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US5986343A (en) | 1998-05-04 | 1999-11-16 | Lucent Technologies Inc. | Bond pad design for integrated circuits |
US6492201B1 (en) | 1998-07-10 | 2002-12-10 | Tessera, Inc. | Forming microelectronic connection components by electrophoretic deposition |
US6103552A (en) | 1998-08-10 | 2000-08-15 | Lin; Mou-Shiung | Wafer scale packaging scheme |
US6261865B1 (en) | 1998-10-06 | 2001-07-17 | Micron Technology, Inc. | Multi chip semiconductor package and method of construction |
US6037668A (en) | 1998-11-13 | 2000-03-14 | Motorola, Inc. | Integrated circuit having a support structure |
JP2000195896A (ja) | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体装置 |
JP2000299408A (ja) * | 1999-04-15 | 2000-10-24 | Toshiba Corp | 半導体構造体および半導体装置 |
US6181016B1 (en) | 1999-06-08 | 2001-01-30 | Winbond Electronics Corp | Bond-pad with a single anchoring structure |
US6368410B1 (en) | 1999-06-28 | 2002-04-09 | General Electric Company | Semiconductor processing article |
US6168965B1 (en) | 1999-08-12 | 2001-01-02 | Tower Semiconductor Ltd. | Method for making backside illuminated image sensor |
JP4139533B2 (ja) | 1999-09-10 | 2008-08-27 | 大日本印刷株式会社 | 半導体装置とその製造方法 |
US6277669B1 (en) | 1999-09-15 | 2001-08-21 | Industrial Technology Research Institute | Wafer level packaging method and packages formed |
JP2001127243A (ja) | 1999-10-26 | 2001-05-11 | Sharp Corp | 積層半導体装置 |
JP3399456B2 (ja) | 1999-10-29 | 2003-04-21 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
US6507113B1 (en) | 1999-11-19 | 2003-01-14 | General Electric Company | Electronic interface structures and methods of fabrication |
JP3626058B2 (ja) | 2000-01-25 | 2005-03-02 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP3684978B2 (ja) | 2000-02-03 | 2005-08-17 | セイコーエプソン株式会社 | 半導体装置およびその製造方法ならびに電子機器 |
US6498387B1 (en) | 2000-02-15 | 2002-12-24 | Wen-Ken Yang | Wafer level package and the process of the same |
US6586955B2 (en) | 2000-03-13 | 2003-07-01 | Tessera, Inc. | Methods and structures for electronic probing arrays |
JP3879816B2 (ja) | 2000-06-02 | 2007-02-14 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器 |
US6472247B1 (en) | 2000-06-26 | 2002-10-29 | Ricoh Company, Ltd. | Solid-state imaging device and method of production of the same |
US6399892B1 (en) | 2000-09-19 | 2002-06-04 | International Business Machines Corporation | CTE compensated chip interposer |
US6693358B2 (en) | 2000-10-23 | 2004-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
JP3433193B2 (ja) | 2000-10-23 | 2003-08-04 | 松下電器産業株式会社 | 半導体チップおよびその製造方法 |
EP1207015A3 (en) | 2000-11-17 | 2003-07-30 | Keltech Engineering, Inc. | Raised island abrasive, method of use and lapping apparatus |
JP2002162212A (ja) | 2000-11-24 | 2002-06-07 | Foundation Of River & Basin Integrated Communications Japan | 堤体ひずみ計測センサ |
US20020098620A1 (en) | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
KR100352236B1 (ko) | 2001-01-30 | 2002-09-12 | 삼성전자 주식회사 | 접지 금속층을 갖는 웨이퍼 레벨 패키지 |
US6867123B2 (en) | 2001-02-08 | 2005-03-15 | Renesas Technology Corp. | Semiconductor integrated circuit device and its manufacturing method |
KR100364635B1 (ko) | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
US6498381B2 (en) | 2001-02-22 | 2002-12-24 | Tru-Si Technologies, Inc. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
JP2002270718A (ja) | 2001-03-07 | 2002-09-20 | Seiko Epson Corp | 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2002359347A (ja) | 2001-03-28 | 2002-12-13 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2002373957A (ja) | 2001-06-14 | 2002-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6531384B1 (en) | 2001-09-14 | 2003-03-11 | Motorola, Inc. | Method of forming a bond pad and structure thereof |
US20030059976A1 (en) | 2001-09-24 | 2003-03-27 | Nathan Richard J. | Integrated package and methods for making same |
JP2003124393A (ja) | 2001-10-17 | 2003-04-25 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6727576B2 (en) | 2001-10-31 | 2004-04-27 | Infineon Technologies Ag | Transfer wafer level packaging |
US20040051173A1 (en) | 2001-12-10 | 2004-03-18 | Koh Philip Joseph | High frequency interconnect system using micromachined plugs and sockets |
JP4202641B2 (ja) * | 2001-12-26 | 2008-12-24 | 富士通株式会社 | 回路基板及びその製造方法 |
TW517361B (en) | 2001-12-31 | 2003-01-11 | Megic Corp | Chip package structure and its manufacture process |
TW544882B (en) | 2001-12-31 | 2003-08-01 | Megic Corp | Chip package structure and process thereof |
US6743660B2 (en) | 2002-01-12 | 2004-06-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method of making a wafer level chip scale package |
US6908784B1 (en) | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
JP2003282791A (ja) | 2002-03-20 | 2003-10-03 | Fujitsu Ltd | 接触型センサ内蔵半導体装置及びその製造方法 |
JP4365558B2 (ja) | 2002-04-08 | 2009-11-18 | 株式会社テクノ高槻 | 電磁振動型ダイヤフラムポンプ |
JP2003318178A (ja) | 2002-04-24 | 2003-11-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
ATE493760T1 (de) | 2002-05-20 | 2011-01-15 | Imagerlabs Inc | Bilden einer integrierten mehrsegmentschaltung mit isolierten substraten |
TWI229435B (en) | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
US6716737B2 (en) | 2002-07-29 | 2004-04-06 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
US6903442B2 (en) | 2002-08-29 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component having backside pin contacts |
US7030010B2 (en) | 2002-08-29 | 2006-04-18 | Micron Technology, Inc. | Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures |
US7329563B2 (en) | 2002-09-03 | 2008-02-12 | Industrial Technology Research Institute | Method for fabrication of wafer level package incorporating dual compliant layers |
JP4440554B2 (ja) | 2002-09-24 | 2010-03-24 | 浜松ホトニクス株式会社 | 半導体装置 |
EP2506305B1 (en) | 2002-09-24 | 2014-11-05 | Hamamatsu Photonics K. K. | Method for manufacturing a photodiode array |
JP2004128063A (ja) | 2002-09-30 | 2004-04-22 | Toshiba Corp | 半導体装置及びその製造方法 |
US6709965B1 (en) * | 2002-10-02 | 2004-03-23 | Taiwan Semiconductor Manufacturing Company | Aluminum-copper bond pad design and method of fabrication |
US20040104454A1 (en) | 2002-10-10 | 2004-06-03 | Rohm Co., Ltd. | Semiconductor device and method of producing the same |
TW569395B (en) | 2002-10-30 | 2004-01-01 | Intelligent Sources Dev Corp | Method of forming a stacked-gate cell structure and its NAND-type flash memory array |
US20050012225A1 (en) | 2002-11-15 | 2005-01-20 | Choi Seung-Yong | Wafer-level chip scale package and method for fabricating and using the same |
JP3918935B2 (ja) | 2002-12-20 | 2007-05-23 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4072677B2 (ja) | 2003-01-15 | 2008-04-09 | セイコーエプソン株式会社 | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004356618A (ja) | 2003-03-19 | 2004-12-16 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体、中継基板の製造方法 |
SG137651A1 (en) | 2003-03-14 | 2007-12-28 | Micron Technology Inc | Microelectronic devices and methods for packaging microelectronic devices |
JP3680839B2 (ja) | 2003-03-18 | 2005-08-10 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
US6841883B1 (en) | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
EP1519410A1 (en) | 2003-09-25 | 2005-03-30 | Interuniversitair Microelektronica Centrum vzw ( IMEC) | Method for producing electrical through hole interconnects and devices made thereof |
US6908856B2 (en) | 2003-04-03 | 2005-06-21 | Interuniversitair Microelektronica Centrum (Imec) | Method for producing electrical through hole interconnects and devices made thereof |
JP4373695B2 (ja) | 2003-04-16 | 2009-11-25 | 浜松ホトニクス株式会社 | 裏面照射型光検出装置の製造方法 |
DE10319538B4 (de) | 2003-04-30 | 2008-01-17 | Qimonda Ag | Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung |
EP1482553A3 (en) | 2003-05-26 | 2007-03-28 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6972480B2 (en) | 2003-06-16 | 2005-12-06 | Shellcase Ltd. | Methods and apparatus for packaging integrated circuit devices |
US6927156B2 (en) | 2003-06-18 | 2005-08-09 | Intel Corporation | Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon |
JP3646720B2 (ja) | 2003-06-19 | 2005-05-11 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
EP1639634B1 (en) | 2003-06-20 | 2009-04-01 | Nxp B.V. | Electronic device, assembly and methods of manufacturing an electronic device |
JP2005026405A (ja) | 2003-07-01 | 2005-01-27 | Sharp Corp | 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置 |
JP2005045073A (ja) | 2003-07-23 | 2005-02-17 | Hamamatsu Photonics Kk | 裏面入射型光検出素子 |
JP4499386B2 (ja) | 2003-07-29 | 2010-07-07 | 浜松ホトニクス株式会社 | 裏面入射型光検出素子の製造方法 |
KR100537892B1 (ko) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
US7180149B2 (en) | 2003-08-28 | 2007-02-20 | Fujikura Ltd. | Semiconductor package with through-hole |
JP2005093486A (ja) | 2003-09-12 | 2005-04-07 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2005101268A (ja) | 2003-09-25 | 2005-04-14 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
US20050082654A1 (en) | 2003-09-26 | 2005-04-21 | Tessera, Inc. | Structure and self-locating method of making capped chips |
GB2406720B (en) | 2003-09-30 | 2006-09-13 | Agere Systems Inc | An inductor formed in an integrated circuit |
US7495179B2 (en) | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
TWI259564B (en) | 2003-10-15 | 2006-08-01 | Infineon Technologies Ag | Wafer level packages for chips with sawn edge protection |
TWI234244B (en) | 2003-12-26 | 2005-06-11 | Intelligent Sources Dev Corp | Paired stack-gate flash cell structure and its contactless NAND-type flash memory arrays |
US20050156330A1 (en) | 2004-01-21 | 2005-07-21 | Harris James M. | Through-wafer contact to bonding pad |
JP4198072B2 (ja) | 2004-01-23 | 2008-12-17 | シャープ株式会社 | 半導体装置、光学装置用モジュール及び半導体装置の製造方法 |
JP2005216921A (ja) | 2004-01-27 | 2005-08-11 | Hitachi Maxell Ltd | 半導体装置製造用のメタルマスク及び半導体装置の製造方法 |
US7026175B2 (en) | 2004-03-29 | 2006-04-11 | Applied Materials, Inc. | High throughput measurement of via defects in interconnects |
US7368695B2 (en) | 2004-05-03 | 2008-05-06 | Tessera, Inc. | Image sensor package and fabrication method |
US20050248002A1 (en) | 2004-05-07 | 2005-11-10 | Michael Newman | Fill for large volume vias |
EP1748476B1 (en) * | 2004-05-18 | 2016-05-11 | Nippon Telegraph And Telephone Corporation | Electrode pad on conductive semiconductor substrate |
KR100618837B1 (ko) | 2004-06-22 | 2006-09-01 | 삼성전자주식회사 | 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법 |
US7232754B2 (en) | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
JP4343044B2 (ja) | 2004-06-30 | 2009-10-14 | 新光電気工業株式会社 | インターポーザ及びその製造方法並びに半導体装置 |
JP2006019455A (ja) | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
KR100605314B1 (ko) | 2004-07-22 | 2006-07-28 | 삼성전자주식회사 | 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법 |
US7750487B2 (en) | 2004-08-11 | 2010-07-06 | Intel Corporation | Metal-metal bonding of compliant interconnect |
US7598167B2 (en) | 2004-08-24 | 2009-10-06 | Micron Technology, Inc. | Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures |
US7378342B2 (en) | 2004-08-27 | 2008-05-27 | Micron Technology, Inc. | Methods for forming vias varying lateral dimensions |
US7129567B2 (en) | 2004-08-31 | 2006-10-31 | Micron Technology, Inc. | Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements |
KR100604049B1 (ko) | 2004-09-01 | 2006-07-24 | 동부일렉트로닉스 주식회사 | 반도체 칩 패키지 및 그 제조방법 |
US7300857B2 (en) | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
TWI288448B (en) | 2004-09-10 | 2007-10-11 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
CN100481402C (zh) | 2004-09-10 | 2009-04-22 | 株式会社东芝 | 半导体器件和半导体器件的制造方法 |
JP4139803B2 (ja) | 2004-09-28 | 2008-08-27 | シャープ株式会社 | 半導体装置の製造方法 |
US7819119B2 (en) | 2004-10-08 | 2010-10-26 | Ric Investments, Llc | User interface having a pivotable coupling |
TWI273682B (en) | 2004-10-08 | 2007-02-11 | Epworks Co Ltd | Method for manufacturing wafer level chip scale package using redistribution substrate |
US7081408B2 (en) | 2004-10-28 | 2006-07-25 | Intel Corporation | Method of creating a tapered via using a receding mask and resulting structure |
JP4873517B2 (ja) | 2004-10-28 | 2012-02-08 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
US20060278997A1 (en) | 2004-12-01 | 2006-12-14 | Tessera, Inc. | Soldered assemblies and methods of making the same |
JP4795677B2 (ja) | 2004-12-02 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法 |
JP4290158B2 (ja) | 2004-12-20 | 2009-07-01 | 三洋電機株式会社 | 半導体装置 |
KR20060087273A (ko) | 2005-01-28 | 2006-08-02 | 삼성전기주식회사 | 반도체 패키지및 그 제조방법 |
US7675153B2 (en) | 2005-02-02 | 2010-03-09 | Kabushiki Kaisha Toshiba | Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof |
US7538032B2 (en) | 2005-06-23 | 2009-05-26 | Teledyne Scientific & Imaging, Llc | Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method |
TWI244186B (en) | 2005-03-02 | 2005-11-21 | Advanced Semiconductor Eng | Semiconductor package and method for manufacturing the same |
TWI264807B (en) | 2005-03-02 | 2006-10-21 | Advanced Semiconductor Eng | Semiconductor package and method for manufacturing the same |
US20060264029A1 (en) | 2005-05-23 | 2006-11-23 | Intel Corporation | Low inductance via structures |
JP4581864B2 (ja) * | 2005-06-21 | 2010-11-17 | パナソニック電工株式会社 | 半導体基板への貫通配線の形成方法 |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
JP4694305B2 (ja) | 2005-08-16 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | 半導体ウエハの製造方法 |
US20070049470A1 (en) | 2005-08-29 | 2007-03-01 | Johnson Health Tech Co., Ltd. | Rapid circuit training machine with dual resistance |
US7772115B2 (en) | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
US20070052050A1 (en) | 2005-09-07 | 2007-03-08 | Bart Dierickx | Backside thinned image sensor with integrated lens stack |
JP2007096198A (ja) * | 2005-09-30 | 2007-04-12 | Fujikura Ltd | 半導体装置及びその製造方法並びに電子装置 |
JP2007157844A (ja) | 2005-12-01 | 2007-06-21 | Sharp Corp | 半導体装置、および半導体装置の製造方法 |
US20070126085A1 (en) | 2005-12-02 | 2007-06-07 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US7456479B2 (en) | 2005-12-15 | 2008-11-25 | United Microelectronics Corp. | Method for fabricating a probing pad of an integrated circuit chip |
JP4826248B2 (ja) | 2005-12-19 | 2011-11-30 | Tdk株式会社 | Ic内蔵基板の製造方法 |
KR100714310B1 (ko) | 2006-02-23 | 2007-05-02 | 삼성전자주식회사 | 변압기 또는 안테나를 구비하는 반도체 패키지들 |
US20080029879A1 (en) | 2006-03-01 | 2008-02-07 | Tessera, Inc. | Structure and method of making lidded chips |
JP2007250712A (ja) * | 2006-03-15 | 2007-09-27 | Nec Corp | 半導体装置及びその製造方法 |
JP4659660B2 (ja) | 2006-03-31 | 2011-03-30 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
KR100837269B1 (ko) | 2006-05-22 | 2008-06-11 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 그 제조 방법 |
JP2007311676A (ja) | 2006-05-22 | 2007-11-29 | Sony Corp | 半導体装置とその製造方法 |
JP4950559B2 (ja) | 2006-05-25 | 2012-06-13 | パナソニック株式会社 | スルーホール電極の形成方法 |
US7605019B2 (en) | 2006-07-07 | 2009-10-20 | Qimonda Ag | Semiconductor device with stacked chips and method for manufacturing thereof |
KR100750741B1 (ko) | 2006-09-15 | 2007-08-22 | 삼성전기주식회사 | 캡 웨이퍼, 이를 구비한 반도체 칩, 및 그 제조방법 |
US7531445B2 (en) | 2006-09-26 | 2009-05-12 | Hymite A/S | Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane |
US20080079779A1 (en) | 2006-09-28 | 2008-04-03 | Robert Lee Cornell | Method for Improving Thermal Conductivity in Micro-Fluid Ejection Heads |
JP2008091632A (ja) | 2006-10-02 | 2008-04-17 | Manabu Bonshihara | 半導体装置の外部回路接続部の構造及びその形成方法 |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US7759166B2 (en) | 2006-10-17 | 2010-07-20 | Tessera, Inc. | Microelectronic packages fabricated at the wafer level and methods therefor |
US7719121B2 (en) | 2006-10-17 | 2010-05-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7807508B2 (en) | 2006-10-31 | 2010-10-05 | Tessera Technologies Hungary Kft. | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
US7935568B2 (en) | 2006-10-31 | 2011-05-03 | Tessera Technologies Ireland Limited | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
KR100830581B1 (ko) | 2006-11-06 | 2008-05-22 | 삼성전자주식회사 | 관통전극을 구비한 반도체 소자 및 그 형성방법 |
US7781781B2 (en) | 2006-11-17 | 2010-08-24 | International Business Machines Corporation | CMOS imager array with recessed dielectric |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
US20080136038A1 (en) | 2006-12-06 | 2008-06-12 | Sergey Savastiouk | Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate |
FR2911006A1 (fr) | 2007-01-03 | 2008-07-04 | St Microelectronics Sa | Puce de circuit electronique integre comprenant une inductance |
JP2008177249A (ja) | 2007-01-16 | 2008-07-31 | Sharp Corp | 半導体集積回路のボンディングパッド、その製造方法、半導体集積回路、並びに電子機器 |
US7518226B2 (en) | 2007-02-06 | 2009-04-14 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
JP5584474B2 (ja) | 2007-03-05 | 2014-09-03 | インヴェンサス・コーポレイション | 貫通ビアによって前面接点に接続された後面接点を有するチップ |
JP4380718B2 (ja) | 2007-03-15 | 2009-12-09 | ソニー株式会社 | 半導体装置の製造方法 |
KR100845006B1 (ko) | 2007-03-19 | 2008-07-09 | 삼성전자주식회사 | 적층 칩 패키지 및 그 제조 방법 |
US20080237881A1 (en) * | 2007-03-30 | 2008-10-02 | Tony Dambrauskas | Recessed solder socket in a semiconductor substrate |
JP2008258258A (ja) | 2007-04-02 | 2008-10-23 | Sanyo Electric Co Ltd | 半導体装置 |
US7977155B2 (en) | 2007-05-04 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level flip-chip assembly methods |
US20080284041A1 (en) | 2007-05-18 | 2008-11-20 | Samsung Electronics Co., Ltd. | Semiconductor package with through silicon via and related method of fabrication |
JP4937842B2 (ja) | 2007-06-06 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5302522B2 (ja) | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
US7767497B2 (en) | 2007-07-12 | 2010-08-03 | Tessera, Inc. | Microelectronic package element and method of fabricating thereof |
CN101809739B (zh) | 2007-07-27 | 2014-08-20 | 泰塞拉公司 | 具有后应用的衬垫延长部分的重构晶片堆封装 |
US7932179B2 (en) | 2007-07-27 | 2011-04-26 | Micron Technology, Inc. | Method for fabricating semiconductor device having backside redistribution layers |
JP2010535427A (ja) | 2007-07-31 | 2010-11-18 | テッセラ,インコーポレイテッド | 貫通シリコンビアを使用する半導体実装プロセス |
KR101387701B1 (ko) | 2007-08-01 | 2014-04-23 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조방법 |
US7902069B2 (en) | 2007-08-02 | 2011-03-08 | International Business Machines Corporation | Small area, robust silicon via structure and process |
WO2009023462A1 (en) | 2007-08-10 | 2009-02-19 | Spansion Llc | Semiconductor device and method for manufacturing thereof |
KR100885924B1 (ko) | 2007-08-10 | 2009-02-26 | 삼성전자주식회사 | 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 |
KR100905784B1 (ko) | 2007-08-16 | 2009-07-02 | 주식회사 하이닉스반도체 | 반도체 패키지용 관통 전극 및 이를 갖는 반도체 패키지 |
KR101213175B1 (ko) | 2007-08-20 | 2012-12-18 | 삼성전자주식회사 | 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지 |
JP2009088201A (ja) | 2007-09-28 | 2009-04-23 | Nec Electronics Corp | 半導体装置 |
JP5656341B2 (ja) | 2007-10-29 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置およびその製造方法 |
JP2009129953A (ja) | 2007-11-20 | 2009-06-11 | Hitachi Ltd | 半導体装置 |
US20090127667A1 (en) | 2007-11-21 | 2009-05-21 | Powertech Technology Inc. | Semiconductor chip device having through-silicon-via (TSV) and its fabrication method |
US7998524B2 (en) | 2007-12-10 | 2011-08-16 | Abbott Cardiovascular Systems Inc. | Methods to improve adhesion of polymer coatings over stents |
US7446036B1 (en) | 2007-12-18 | 2008-11-04 | International Business Machines Corporation | Gap free anchored conductor and dielectric structure and method for fabrication thereof |
WO2009104668A1 (ja) | 2008-02-21 | 2009-08-27 | 日本電気株式会社 | 配線基板及び半導体装置 |
US20090212381A1 (en) | 2008-02-26 | 2009-08-27 | Tessera, Inc. | Wafer level packages for rear-face illuminated solid state image sensors |
US7791174B2 (en) | 2008-03-07 | 2010-09-07 | Advanced Inquiry Systems, Inc. | Wafer translator having a silicon core isolated from signal paths by a ground plane |
US8049310B2 (en) | 2008-04-01 | 2011-11-01 | Qimonda Ag | Semiconductor device with an interconnect element and method for manufacture |
US7842548B2 (en) | 2008-04-22 | 2010-11-30 | Taiwan Semconductor Manufacturing Co., Ltd. | Fixture for P-through silicon via assembly |
US7838967B2 (en) | 2008-04-24 | 2010-11-23 | Powertech Technology Inc. | Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips |
US20090267183A1 (en) | 2008-04-28 | 2009-10-29 | Research Triangle Institute | Through-substrate power-conducting via with embedded capacitance |
CN101582434B (zh) | 2008-05-13 | 2011-02-02 | 鸿富锦精密工业(深圳)有限公司 | 影像感测器封装结构及其制造方法及相机模组 |
US7939449B2 (en) | 2008-06-03 | 2011-05-10 | Micron Technology, Inc. | Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension back side ends |
US7863721B2 (en) | 2008-06-11 | 2011-01-04 | Stats Chippac, Ltd. | Method and apparatus for wafer level integration using tapered vias |
US20100013060A1 (en) | 2008-06-22 | 2010-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench |
JP5183340B2 (ja) | 2008-07-23 | 2013-04-17 | 日本電波工業株式会社 | 表面実装型の発振器およびこの発振器を搭載した電子機器 |
KR20100020718A (ko) | 2008-08-13 | 2010-02-23 | 삼성전자주식회사 | 반도체 칩, 그 스택 구조 및 이들의 제조 방법 |
KR20100045857A (ko) | 2008-10-24 | 2010-05-04 | 삼성전자주식회사 | 반도체 칩, 스택 모듈, 메모리 카드 및 반도체 칩의 제조 방법 |
US20100117242A1 (en) | 2008-11-10 | 2010-05-13 | Miller Gary L | Technique for packaging multiple integrated circuits |
US7906404B2 (en) | 2008-11-21 | 2011-03-15 | Teledyne Scientific & Imaging, Llc | Power distribution for CMOS circuits using in-substrate decoupling capacitors and back side metal layers |
US7939926B2 (en) | 2008-12-12 | 2011-05-10 | Qualcomm Incorporated | Via first plus via last technique for IC interconnects |
JP5308145B2 (ja) | 2008-12-19 | 2013-10-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20100159699A1 (en) | 2008-12-19 | 2010-06-24 | Yoshimi Takahashi | Sandblast etching for through semiconductor vias |
TWI366890B (en) | 2008-12-31 | 2012-06-21 | Ind Tech Res Inst | Method of manufacturing through-silicon-via and through-silicon-via structure |
US20100174858A1 (en) * | 2009-01-05 | 2010-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Extra high bandwidth memory die stack |
KR20100087566A (ko) | 2009-01-28 | 2010-08-05 | 삼성전자주식회사 | 반도체 소자 패키지의 형성방법 |
US8158515B2 (en) | 2009-02-03 | 2012-04-17 | International Business Machines Corporation | Method of making 3D integrated circuits |
US7998860B2 (en) | 2009-03-12 | 2011-08-16 | Micron Technology, Inc. | Method for fabricating semiconductor components using maskless back side alignment to conductive vias |
US8466542B2 (en) | 2009-03-13 | 2013-06-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
WO2010109746A1 (ja) | 2009-03-27 | 2010-09-30 | パナソニック株式会社 | 半導体装置及びその製造方法 |
TWI466258B (zh) | 2009-04-10 | 2014-12-21 | Nanya Technology Corp | 電性通透連接及其形成方法 |
US8263434B2 (en) | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
JP5715334B2 (ja) | 2009-10-15 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8008121B2 (en) | 2009-11-04 | 2011-08-30 | Stats Chippac, Ltd. | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate |
US8519538B2 (en) | 2010-04-28 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser etch via formation |
US8299608B2 (en) | 2010-07-08 | 2012-10-30 | International Business Machines Corporation | Enhanced thermal management of 3-D stacked die packaging |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8598695B2 (en) | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8697569B2 (en) | 2010-07-23 | 2014-04-15 | Tessera, Inc. | Non-lithographic formation of three-dimensional conductive elements |
US8847376B2 (en) | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8686565B2 (en) | 2010-09-16 | 2014-04-01 | Tessera, Inc. | Stacked chip assembly having vertical vias |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8421193B2 (en) | 2010-11-18 | 2013-04-16 | Nanya Technology Corporation | Integrated circuit device having through via and method for preparing the same |
-
2010
- 2010-12-08 US US12/962,806 patent/US8610264B2/en active Active
-
2011
- 2011-12-07 EP EP11802829.9A patent/EP2649643A2/en not_active Withdrawn
- 2011-12-07 KR KR1020137017820A patent/KR101906467B1/ko active IP Right Grant
- 2011-12-07 CN CN201180066989.0A patent/CN103339725B/zh active Active
- 2011-12-07 JP JP2013543298A patent/JP6153471B2/ja active Active
- 2011-12-07 WO PCT/US2011/063653 patent/WO2012078709A2/en active Application Filing
- 2011-12-08 TW TW104130730A patent/TWI560785B/zh active
- 2011-12-08 TW TW100145366A patent/TWI508195B/zh active
-
2013
- 2013-12-12 US US14/104,431 patent/US8796828B2/en active Active
-
2014
- 2014-08-04 US US14/451,136 patent/US9224649B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003020404A (ja) * | 2001-07-10 | 2003-01-24 | Hitachi Ltd | 耐熱性低弾性率材およびそれを用いた装置 |
US20060071347A1 (en) * | 2004-10-04 | 2006-04-06 | Sharp Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
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US20140342503A1 (en) | 2014-11-20 |
TW201246413A (en) | 2012-11-16 |
TW201601226A (zh) | 2016-01-01 |
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US8796828B2 (en) | 2014-08-05 |
KR101906467B1 (ko) | 2018-10-10 |
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KR20130129404A (ko) | 2013-11-28 |
WO2012078709A2 (en) | 2012-06-14 |
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US8610264B2 (en) | 2013-12-17 |
EP2649643A2 (en) | 2013-10-16 |
JP6153471B2 (ja) | 2017-06-28 |
CN103339725A (zh) | 2013-10-02 |
CN103339725B (zh) | 2016-11-09 |
TWI508195B (zh) | 2015-11-11 |
JP2014504451A (ja) | 2014-02-20 |
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