TW586201B - Semiconductor device and the manufacturing method thereof - Google Patents

Semiconductor device and the manufacturing method thereof Download PDF

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Publication number
TW586201B
TW586201B TW91110661A TW91110661A TW586201B TW 586201 B TW586201 B TW 586201B TW 91110661 A TW91110661 A TW 91110661A TW 91110661 A TW91110661 A TW 91110661A TW 586201 B TW586201 B TW 586201B
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TW
Taiwan
Prior art keywords
semiconductor wafer
main surface
semiconductor
wiring substrate
electrodes
Prior art date
Application number
TW91110661A
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English (en)
Chinese (zh)
Inventor
Yoshiyuki Kado
Takahiro Naito
Toshihiko Sato
Hikaru Ikegami
Takafumi Kikuchi
Original Assignee
Hitachi Ltd
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Publication date
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Publication of TW586201B publication Critical patent/TW586201B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L2924/30105—Capacitance

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW91110661A 2001-06-07 2002-05-21 Semiconductor device and the manufacturing method thereof TW586201B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001172503 2001-06-07

Publications (1)

Publication Number Publication Date
TW586201B true TW586201B (en) 2004-05-01

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Application Number Title Priority Date Filing Date
TW91110661A TW586201B (en) 2001-06-07 2002-05-21 Semiconductor device and the manufacturing method thereof

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Country Link
US (9) US7042073B2 (cg-RX-API-DMAC7.html)
EP (1) EP1401020A4 (cg-RX-API-DMAC7.html)
JP (3) JP4149377B2 (cg-RX-API-DMAC7.html)
KR (1) KR100868419B1 (cg-RX-API-DMAC7.html)
CN (2) CN101303984B (cg-RX-API-DMAC7.html)
TW (1) TW586201B (cg-RX-API-DMAC7.html)
WO (1) WO2002103793A1 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7728445B2 (en) 2005-03-16 2010-06-01 Yamaha Corporation Semiconductor device production method and semiconductor device

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* Cited by examiner, † Cited by third party
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US6979904B2 (en) * 2002-04-19 2005-12-27 Micron Technology, Inc. Integrated circuit package having reduced interconnects
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
JP3844467B2 (ja) * 2003-01-08 2006-11-15 沖電気工業株式会社 半導体装置及びその製造方法
JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
JP4149289B2 (ja) 2003-03-12 2008-09-10 株式会社ルネサステクノロジ 半導体装置
JP4484444B2 (ja) * 2003-04-11 2010-06-16 三洋電機株式会社 回路装置の製造方法
US7371607B2 (en) * 2003-05-02 2008-05-13 Seiko Epson Corporation Method of manufacturing semiconductor device and method of manufacturing electronic device
US7920723B2 (en) * 2005-11-18 2011-04-05 Tessera Technologies Ireland Limited Two stage detection for photographic eye artifacts
JP4398225B2 (ja) * 2003-11-06 2010-01-13 株式会社ルネサステクノロジ 半導体装置
JP4580730B2 (ja) 2003-11-28 2010-11-17 ルネサスエレクトロニクス株式会社 オフセット接合型マルチチップ半導体装置
DE102004013681B3 (de) * 2004-03-18 2005-11-17 Infineon Technologies Ag Halbleitermodul mit einem Kopplungssubstrat und Verfahren zur Herstellung desselben
JP4538830B2 (ja) 2004-03-30 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置
GB2429842B (en) * 2004-05-20 2009-01-28 Spansion Llc Method of fabricating semiconductor device and semiconductor device
JP4592333B2 (ja) * 2004-05-31 2010-12-01 三洋電機株式会社 回路装置およびその製造方法
JP4601365B2 (ja) * 2004-09-21 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
US7332801B2 (en) * 2004-09-30 2008-02-19 Intel Corporation Electronic device
KR100843137B1 (ko) * 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
JP2006216911A (ja) * 2005-02-07 2006-08-17 Renesas Technology Corp 半導体装置およびカプセル型半導体パッケージ
US20060214284A1 (en) * 2005-03-24 2006-09-28 Stuart Haden Apparatus and method for data capture
JP4817892B2 (ja) * 2005-06-28 2011-11-16 富士通セミコンダクター株式会社 半導体装置
JP4750523B2 (ja) * 2005-09-27 2011-08-17 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2007103423A (ja) * 2005-09-30 2007-04-19 Renesas Technology Corp 半導体装置及びその製造方法
US7806731B2 (en) * 2005-12-29 2010-10-05 Sandisk Corporation Rounded contact fingers on substrate/PCB for crack prevention
US7592699B2 (en) * 2005-12-29 2009-09-22 Sandisk Corporation Hidden plating traces
JP2007227558A (ja) * 2006-02-22 2007-09-06 Nec Electronics Corp 半導体装置の製造装置及び半導体装置の製造方法
US8623737B2 (en) * 2006-03-31 2014-01-07 Intel Corporation Sol-gel and mask patterning for thin-film capacitor fabrication, thin-film capacitors fabricated thereby, and systems containing same
JP2007335581A (ja) 2006-06-14 2007-12-27 Renesas Technology Corp 半導体装置の製造方法
WO2008014633A1 (en) * 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
JP2008091795A (ja) * 2006-10-04 2008-04-17 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
KR100887475B1 (ko) * 2007-02-26 2009-03-10 주식회사 네패스 반도체 패키지 및 그 제조방법
JP5205867B2 (ja) * 2007-08-27 2013-06-05 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5222509B2 (ja) * 2007-09-12 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置
US8378472B2 (en) * 2007-10-17 2013-02-19 Panasonic Corporation Mounting structure for semiconductor element with underfill resin
JP5353153B2 (ja) * 2007-11-09 2013-11-27 パナソニック株式会社 実装構造体
JP2008098679A (ja) * 2008-01-07 2008-04-24 Renesas Technology Corp 半導体装置
BRPI0822296A2 (pt) * 2008-02-22 2015-06-30 Toppan Printing Co Ltd Transponder e livreto
JP5538682B2 (ja) * 2008-03-06 2014-07-02 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP2010034294A (ja) * 2008-07-29 2010-02-12 Nec Electronics Corp 半導体装置およびその設計方法
KR101003116B1 (ko) * 2008-08-08 2010-12-21 주식회사 하이닉스반도체 패드를 제어하는 반도체 메모리 장치 및 그 장치가 장착된 멀티칩 패키지
US7925949B2 (en) * 2008-10-15 2011-04-12 Micron Technology, Inc. Embedded processor
US8022539B2 (en) * 2008-11-17 2011-09-20 Stats Chippac Ltd. Integrated circuit packaging system with increased connectivity and method of manufacture thereof
JP5160498B2 (ja) * 2009-05-20 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置
US8743561B2 (en) * 2009-08-26 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level molded structure for package assembly
JP5250524B2 (ja) * 2009-10-14 2013-07-31 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8749074B2 (en) 2009-11-30 2014-06-10 Micron Technology, Inc. Package including an interposer having at least one topological feature
US8399300B2 (en) * 2010-04-27 2013-03-19 Stats Chippac, Ltd. Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101692955B1 (ko) * 2010-10-06 2017-01-05 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
CN102034721B (zh) 2010-11-05 2013-07-10 南通富士通微电子股份有限公司 芯片封装方法
CN102034720B (zh) * 2010-11-05 2013-05-15 南通富士通微电子股份有限公司 芯片封装方法
US8680932B2 (en) * 2011-02-07 2014-03-25 Nihon Dempa Kogyo Co., Ltd Oscillator
US8674483B2 (en) * 2011-06-27 2014-03-18 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies
TWI455280B (zh) * 2011-07-19 2014-10-01 矽品精密工業股份有限公司 半導體封裝件
CN102254891A (zh) * 2011-08-01 2011-11-23 三星半导体(中国)研究开发有限公司 倒装芯片封装结构及其制造方法
US8597986B2 (en) * 2011-09-01 2013-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. System in package and method of fabricating same
US8779599B2 (en) * 2011-11-16 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages including active dies and dummy dies and methods for forming the same
US8871568B2 (en) * 2012-01-06 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and method of forming the same
US9117790B2 (en) 2012-06-25 2015-08-25 Marvell World Trade Ltd. Methods and arrangements relating to semiconductor packages including multi-memory dies
KR20140006587A (ko) 2012-07-06 2014-01-16 삼성전자주식회사 반도체 패키지
US9136213B2 (en) * 2012-08-02 2015-09-15 Infineon Technologies Ag Integrated system and method of making the integrated system
JP2014036179A (ja) * 2012-08-10 2014-02-24 Ps4 Luxco S A R L 半導体装置
CN104919586A (zh) * 2013-01-16 2015-09-16 株式会社村田制作所 模块及其制造方法
US9293404B2 (en) 2013-01-23 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-applying supporting materials between bonded package components
US20140264783A1 (en) * 2013-03-13 2014-09-18 Altera Corporation Apparatus for electronic assembly with improved interconnect and associated methods
US9627229B2 (en) * 2013-06-27 2017-04-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
JP6196092B2 (ja) * 2013-07-30 2017-09-13 ルネサスエレクトロニクス株式会社 半導体装置
TWI541954B (zh) * 2013-08-12 2016-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP6100648B2 (ja) * 2013-08-28 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2015082547A (ja) 2013-10-22 2015-04-27 セイコーエプソン株式会社 回路モジュール及びその製造方法
JP2015109408A (ja) * 2013-10-22 2015-06-11 マイクロン テクノロジー， インク． 複合チップ、半導体装置、及び半導体装置の製造方法
US8912078B1 (en) 2014-04-16 2014-12-16 Applied Materials, Inc. Dicing wafers having solder bumps on wafer backside
KR20160085171A (ko) * 2015-01-07 2016-07-15 삼성전자주식회사 반도체 장치와, 그를 포함하는 전자 장치 및 반도체 장치를 장착하는 방법
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
JP6444269B2 (ja) * 2015-06-19 2018-12-26 新光電気工業株式会社 電子部品装置及びその製造方法
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
JP6922991B2 (ja) 2017-09-29 2021-08-18 株式会社アイシン 回路基板、回路基板の設計方法、及び半導体装置
JP7238481B2 (ja) 2019-03-05 2023-03-14 株式会社アイシン 半導体モジュール及び半導体装置
JP2020150145A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体装置
US11164804B2 (en) 2019-07-23 2021-11-02 International Business Machines Corporation Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste
JP7200899B2 (ja) * 2019-09-30 2023-01-10 三菱電機株式会社 半導体装置および半導体装置の製造方法
US11282716B2 (en) 2019-11-08 2022-03-22 International Business Machines Corporation Integration structure and planar joining
US11621245B2 (en) 2020-06-03 2023-04-04 Micron Technology, Inc. Microelectronic device packages with EMI shielding, methods of fabricating and related electronic systems
KR102877210B1 (ko) 2020-06-22 2025-10-28 삼성전자주식회사 반도체 패키지
US12165983B2 (en) * 2020-08-11 2024-12-10 Intel Corporation Stepped electronic substrate for integrated circuit packages
CN112188728B (zh) * 2020-09-17 2021-09-07 西安交通大学 一种基于倒装芯片的温度压力集成传感器及其封装方法
CN112490182B (zh) * 2020-11-25 2024-07-05 通富微电子股份有限公司 多芯片封装方法
CN116784011A (zh) * 2021-02-03 2023-09-19 铠侠股份有限公司 半导体存储装置
CN115918270A (zh) * 2021-06-18 2023-04-04 庆鼎精密电子（淮安）有限公司 电路板组件及其制作方法
US11729915B1 (en) * 2022-03-22 2023-08-15 Tactotek Oy Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6423562A (en) * 1987-07-20 1989-01-26 Nippon Telegraph & Telephone Semiconductor device
JP2585799B2 (ja) * 1989-06-30 1997-02-26 株式会社東芝 半導体メモリ装置及びそのバーンイン方法
JPH04302164A (ja) 1991-03-29 1992-10-26 Fujitsu Ltd 半導体装置
US5310965A (en) * 1991-08-28 1994-05-10 Nec Corporation Multi-level wiring structure having an organic interlayer insulating film
JPH05226793A (ja) * 1992-02-18 1993-09-03 Ibiden Co Ltd プリント配線板
JPH06224561A (ja) * 1993-01-25 1994-08-12 Ibiden Co Ltd 放熱構造プリント配線板及びその製造方法
US5656945A (en) * 1993-05-12 1997-08-12 Tribotech Apparatus for testing a nonpackaged die
JP3242765B2 (ja) * 1993-09-09 2001-12-25 富士通株式会社 半導体装置及びその製造方法
JPH07115151A (ja) * 1993-10-14 1995-05-02 Toshiba Corp 半導体装置及びその製造方法
JP3085622B2 (ja) * 1993-10-28 2000-09-11 京セラ株式会社 電子素子搭載用基板の製造方法
US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
JP2571024B2 (ja) * 1994-09-28 1997-01-16 日本電気株式会社 マルチチップモジュール
JPH08153819A (ja) * 1994-11-29 1996-06-11 Citizen Watch Co Ltd ボールグリッドアレイ型半導体パッケージの製造方法
US6223429B1 (en) * 1995-06-13 2001-05-01 Hitachi Chemical Company, Ltd. Method of production of semiconductor device
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
JP4026188B2 (ja) * 1996-02-27 2007-12-26 イビデン株式会社 プリント配線板
JP2891665B2 (ja) * 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
EP1447849A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board having the same mounted thereon
JP2976917B2 (ja) * 1997-03-31 1999-11-10 日本電気株式会社 半導体装置
JPH10303334A (ja) * 1997-04-28 1998-11-13 Sumitomo Kinzoku Electro Device:Kk プラスチック配線基板
JPH1154658A (ja) * 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
JPH11121897A (ja) * 1997-10-14 1999-04-30 Fujitsu Ltd 複数の回路素子を基板上に搭載するプリント配線基板の製造方法及びプリント配線基板の構造
US6016256A (en) * 1997-11-14 2000-01-18 The Panda Project Multi-chip module having interconnect dies
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JP3269025B2 (ja) * 1998-04-16 2002-03-25 三洋電機株式会社 半導体装置とその製造方法
US6479887B1 (en) * 1998-08-31 2002-11-12 Amkor Technology, Inc. Circuit pattern tape for wafer-scale production of chip size semiconductor packages
US6281568B1 (en) * 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
US6100564A (en) * 1998-09-30 2000-08-08 International Business Machines Corporation SOI pass-gate disturb solution
JP3472492B2 (ja) * 1998-11-25 2003-12-02 京セラ株式会社 多数個取り配線基板
JP2000183218A (ja) * 1998-12-14 2000-06-30 Mitsumi Electric Co Ltd Ｉｃパッケージの製造方法
JP3512657B2 (ja) * 1998-12-22 2004-03-31 シャープ株式会社 半導体装置
JP2000243900A (ja) * 1999-02-23 2000-09-08 Rohm Co Ltd 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
JP4809957B2 (ja) * 1999-02-24 2011-11-09 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
JP3255895B2 (ja) * 1999-09-20 2002-02-12 ローム株式会社 半導体装置
JP2000294669A (ja) * 1999-04-05 2000-10-20 Hitachi Ltd 配線基板およびそれを用いた半導体装置の製造方法ならびに半導体装置
JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
US6329228B1 (en) * 1999-04-28 2001-12-11 Citizen Watch Co., Ltd. Semiconductor device and method of fabricating the same
JP3718370B2 (ja) 1999-05-19 2005-11-24 ローム株式会社 マルチチップ型半導体装置
JP2001102486A (ja) * 1999-07-28 2001-04-13 Seiko Epson Corp 半導体装置用基板、半導体チップ搭載基板、半導体装置及びその製造方法、回路基板並びに電子機器
JP3339473B2 (ja) 1999-08-26 2002-10-28 日本電気株式会社 パッケージ基板、該パッケージ基板を備える半導体装置及びそれらの製造方法
JP2001056346A (ja) * 1999-08-19 2001-02-27 Fujitsu Ltd プローブカード及び複数の半導体装置が形成されたウエハの試験方法
JP3827497B2 (ja) * 1999-11-29 2006-09-27 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2001160597A (ja) * 1999-11-30 2001-06-12 Nec Corp 半導体装置、配線基板及び半導体装置の製造方法
JP2001274316A (ja) * 2000-03-23 2001-10-05 Hitachi Ltd 半導体装置及びその製造方法
JP2002016181A (ja) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd 半導体装置、その製造方法、及び電着フレーム
JP2001320014A (ja) * 2000-05-11 2001-11-16 Seiko Epson Corp 半導体装置及びその製造方法
JP3916854B2 (ja) * 2000-06-28 2007-05-23 シャープ株式会社 配線基板、半導体装置およびパッケージスタック半導体装置
JP2002026236A (ja) * 2000-07-05 2002-01-25 Canon Inc 半導体素子の実装構造およびその実装方法
JP3581086B2 (ja) * 2000-09-07 2004-10-27 松下電器産業株式会社 半導体装置
US6885106B1 (en) * 2001-01-11 2005-04-26 Tessera, Inc. Stacked microelectronic assemblies and methods of making same
JP2002222914A (ja) * 2001-01-26 2002-08-09 Sony Corp 半導体装置及びその製造方法
US6763486B2 (en) * 2001-05-09 2004-07-13 Agilent Technologies, Inc. Method and apparatus of boundary scan testing for AC-coupled differential data paths
EP1401020A4 (en) * 2001-06-07 2007-12-19 Renesas Tech Corp SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR
JP4790157B2 (ja) * 2001-06-07 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置
JP3831287B2 (ja) * 2002-04-08 2006-10-11 株式会社日立製作所 半導体装置の製造方法
JP3702961B2 (ja) * 2002-10-04 2005-10-05 東洋通信機株式会社 表面実装型ｓａｗデバイスの製造方法
JP4302164B2 (ja) 2006-12-15 2009-07-22 三洋電機株式会社 照明装置及び投写型映像表示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7728445B2 (en) 2005-03-16 2010-06-01 Yamaha Corporation Semiconductor device production method and semiconductor device

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