KR100900831B1 - 반도체 트랜지스터 제조 방법 - Google Patents

반도체 트랜지스터 제조 방법 Download PDF

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KR100900831B1
KR100900831B1 KR1020077007073A KR20077007073A KR100900831B1 KR 100900831 B1 KR100900831 B1 KR 100900831B1 KR 1020077007073 A KR1020077007073 A KR 1020077007073A KR 20077007073 A KR20077007073 A KR 20077007073A KR 100900831 B1 KR100900831 B1 KR 100900831B1
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gate
insulating
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silicon
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브라이언 도일
피터 창
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인텔 코포레이션
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET

Abstract

동일한 프로세스에서 제조된 독립적인 액세스의 2-게이트 트랜지스터 및 3-게이트 트랜지스터가 기술된다. 3-게이트 디바이스가 아닌, I-게이트 디바이스의 반도체 바디 위로부터 절연 플러그가 제거된다. 예컨대, 이것은 3-게이트 디바이스의 3개의 측면상에 금속화부가 형성되도록 허용하며, I-게이트 디바이스에 대한 독립적인 게이트를 허용한다.

Description

반도체 트랜지스터 제조 방법{INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW}
본 발명은 반도체 프로세싱의 분야에 관한 것이다.
반도체 프로세싱에 있어서, 한 가지의 비교적 최근의 진전은 독립 제어형 2-게이트(I-게이트) 트랜지스터이다. 이러한 트랜지스터는 채널의 대향 측면들상에 배치된 2개의 게이트를 가지며, 2개의 게이트 각각은 독립적으로 제어된다. 독립적인 게이트 제어는 몇몇 고유의 트랜지스터 특성을 제공하며, 예를 들면, 단일 바디의 DRAM(dynamic random-access memory) 셀을 가능하게 한다.
반도체 프로세싱에 있어서, 다른 비교적 최근의 진전은 3-게이트 트랜지스터이다. 여기서, 게이트는 채널 영역의 3개의 측면상에 형성된다. 이러한 트랜지스터는, 특히 높은-k 절연체 및 금속 게이트와 함께 이용되는 경우, 실질적인 성능 향상을 제공한다.
몇 가지의 I-게이트 구조물이 제안되어 왔다. 이러한, 그리고 다른 관련된 기법에 대해서는, M. Chan Electron Device Letters, Jan 1994 이후의 C. Kuo, IEDM, Dec. 2002; C. Kuo, IEDM, Dec. 2002, "A Hypothetical Construction of the Double Gate Floating Body Cell"; T. Ohsawa 등의 IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, November 2002; David M. Fried 등의 "High-Performance P-Type Independent-Gate FinFETs", IEEE Electron Device Letters, Vol. 25. No. 4, April 2004; David M. Fried 등의 "Improved Independent Gate N-Type FinFET Fabrication and Characterization", IEEE Electron Device Letters, Vol. 24, No. 9, September 2003의 문헌에 기술되어 있다.
3-게이트 구조물은, 예컨대, 공개 번호 U.S. 2004-0036127-A1에 기술되어 있다.
도 1(a)는 중첩되는 절연 부재를 갖는 2개의 실리콘 바디를 포함하는 기판의 사시도이다.
도 1(b)는 도 1(a)의 섹션 라인 1B-1B를 통해 취해진 도 1(a)의 구조물의 단면 정면도이다.
도 2(a)는 희생층의 패터닝 이후의 도 1의 구조물을 도시한다.
도 2(b)는 도 2(a)의 섹션 라인 2B-2B를 통해 취해진 도 2(a)의 구조물의 단면 정면도이다.
도 3은 ILD(interlayer dielectric)의 증착 이후의 도 2(a)의 구조물의 사시도이다.
도 4(a)는 평탄화 이후의 도 3의 구조물의 사시도이다.
도 4(b)는 도 4(a)의 섹션 라인 4B-4B를 통해 취해진 단면 정면도이다.
도 5는 I-게이트 트랜지스터가 자신의 위에 제조되는 기판의 섹션을 덮은 이후의 도 4의 구조물의 사시도이다.
도 6(a)는 에칭 단계 이후의 도 5의 구조물의 사시도이다.
도 6(b)는 도 6(a)의 섹션 라인 6B-6B를 통해 취해진 도 6(a)의 구조물의 단면도이다.
도 7(a)는 패터닝된 희생층 제거 이후의 도 6(a)의 구조물의 사시도이다.
도 7(b)는 도 7(a)의 섹션 라인 7B-7B를 통해 취해진 도 7(a)의 구조물의 단면 정면도이다.
도 8은 절연층 및 금속층 형성 이후의 도 7(a) 및 7(b)의 구조물의 단면 정면도이다.
도 9(a)는 금속층의 평탄화 이후의 도 8의 구조물의 사시도이다.
도 9(b)는 ILD가 제거된 도 9(a)의 구조물의 사시도이다.
이하의 설명에서, 공통 기판상의 독립적으로 액세스된 2-게이트(I-게이트) 트랜지스터 및 3-게이트 트랜지스터가 기술된다. 본 발명에 대한 완전한 이해를 제공하기 위해, 특정 물질과 같은 다양한 특정 세부 사항이 개시된다. 당업자라면, 이들 특정 세부 사항 없이도 본 발명을 실시할 수 있음을 명백히 알 것이다. 다른 경우, 본 발명을 불필요하게 불명료하게 하지 않도록, 잘 알려진 프로세싱 단계들은 상세히 기술되지 않았다. 예를 들어, 잘 알려진 클리닝 단계, 및 집적 회로의 제조시에 종종 이용되는 몇몇 보호층에 대해서는 기술되지 않는다.
이하의 방법은 단일의 프로세스 흐름에서의 I-게이트 트랜지스터 및 3-게이트 트랜지스터 둘다의 형성을 기술한다. 단일의 I-게이트 트랜지스터 및 단일의 3-게이트 트랜지스터의 제조에 대해서만 예시되지만, 당업자라면, 전형적인 집적 회로에서는 여러 가지의 그러한 트랜지스터들이 동시에 제조됨을 명백히 알 것이다. 더욱이, I-게이트 및 3-게이트 트랜지스터는 집적 회로에서 요구되는 어느 곳에라도 제조될 수 있다. 따라서, 버퍼와 같은 단일의 회로는 I-게이트 트랜지스터 및 3-게이트 트랜지스터 둘다를 가질 수 있다. 몇몇 경우, 예를 들면, DRAM에서, 단지 I-게이트 트랜지스터만을 이용하는 메모리 셀의 어레이가 제조되어, I-게이트 트랜지스터 및 3-게이트 트랜지스터 둘다를 이용하는 주변 회로에 접속될 수 있다. I-게이트 메모리 셀을 이용하는 메모리에 대해서는, 2004년 3월 31일에 출원되어, 본 출원의 양수인에게 양도된 "Memory with Split-Gate Devices and Method of Fabrication" 이란 제목의 제 10/816,282 호에 기술되어 있다.
일 실시예에서, 실리콘 기판(12)상에 형성되는 산화물층(10)상에 트랜지스터가 제조된다. 트랜지스터 바디는 층(10)상에 배치된 (도 1(a) 및 1(b)에서 점선으로 도시된) 단결정 실리콘층(14)으로부터 제조된다. 이러한 SOI(silicon-on-insulator) 기판은 반도체 업계에 잘 알려져 있으며, 도시된 바와 같이, 층(14)이 층(10)상에 배치된다. 예로써, SOI 기판은 산화물층(10) 및 실리콘층(14)을 기판(12)상에 본딩한 후, 층(14)을 평탄화하여, 그것이 비교적 얇아지도록 한다. 이러한 비교적 얇은, 낮은 바디 효과 층은, 전술한 바와 같은, 능동 디바이스의 바디를 형성하는데 이용된다. 예컨대, 매립된 산화물층을 형성하기 위해 실리콘 기판상에 산소를 주입하는 것을 포함하는, SOI 기판을 형성하는 다른 기법들이 알려져 있다. 후속하는 단면도에서, 트랜지스터는 산화물층(10)상에 제조되는 것으로 도시되며, 하부의 실리콘 기판(12)은 도시되지 않는다.
층(14)은 n 채널 디바이스가 제조될 영역에 n 타입 도펀트로 선택적으로 이온 주입되고, p 채널 디바이스가 제조될 영역에 p 타입 도펀트로 선택적으로 이온주입될 수 있다. 이것은 CMOS 집적 회로에 제조된 MOS 디바이스의 채널 영역에서 전형적으로 발견되는 비교적 약한 도핑을 제공하는데 이용된다. I-게이트 트랜지스터 및 3-게이트 트랜지스터 둘다, 기술된 프로세스를 이용하여, p 채널 또는 n 채널 디바이스로서 제조될 수 있다. (트랜지스터의 채널 영역의 도핑은, 도 1(a) 또는 7(a)에 도시된 프로세스에서의 포인트와 같은 프로세스 흐름에서의 다른 포인트에서 수행될 수 있다.)
일 실시예에 대한 프로세싱에서, 보호 산화물(도시되지 않음)이 실리콘층(14)상에 배치되며, 그 후, 실리콘 질화물층이 증착된다. 질화물층은 도 1(a) 및 1(b)의 부재들(17, 18)과 같은 복수의 절연 부재를 규정하도록 마스킹된다. 그 후, 하부의 실리콘층(14)이 이들 부재와 정렬되어 에칭됨으로써, 실리콘 바디(15, 16)를 초래한다.
실리콘 바디(15, 16)의 폭은 특정 프로세스, 예컨대, 30 nm 게이트 길이 프로세스에서 중요한 치수일 수 있으며, 이들 바디는 30 nm의 폭을 가질 수 있다. 층(14), 및 부재(17, 18)가 형성되는 실리콘 질화물층의 두께는 각각, 예컨대, 10-50 nm 범위내일 수 있다.
이제, 희생층이 도 1(a)의 구조물상에서 산화물층(10) 위에 배치된다. 일 실시예에서, 이러한 층은 50-100 nm 두께의 폴리실리콘층이다. 희생층을 위해 다른 물질들이 이용될 수 있다. 후술하는 바와 같이, 희생층을 위한 물질은 디바이스의 채널 영역을, 소스 및 드레인 영역의 형성 동안 이온 주입으로부터 보호할 수 있어야 한다. 더욱이, 후술되는 바와 같이, 희생층은 패터닝 이후에 희생층 주변에 형성된 ILD(interlayer dielectric)의 무결성을 파괴하지 않고서, 에칭될 수 있어야 한다. 또한, 절연 부재는 희생층의 존재시에 선택적으로 에칭될 수 있어야 한다.
다음, 도 2(a)에서 부재(20, 22)로서 도시된 게이트 규정 부재내로 희생층이 패터닝된다. 부재(20)는 I-게이트 트랜지스터를 위한 2개의 게이트가 제조되는 영역 및 이들 게이트에 대한 "핀(fin)"을 점유하여, 이후에 도시된 바와 같은 게이트와의 접촉을 허용한다. 부재(22)는 3-게이트 트랜지스터를 위한 3-게이트가 형성되는 영역 및 핀을 점유하여, 다시 접촉을 허용한다.
프로세싱에서의 이러한 시점에서, 실리콘 질화물 부재(17, 18)가 부재(20, 22)와 정렬되어 에칭됨으로써, 하부의 실리콘 바디(15, 16)의 부분들이 노출된다. 화살표(25)에 의해 도시된 바와 같이, 실리콘 바디가, 그것이 부재(20, 22)에 의해 덮이지 않는 정도까지, 이온 주입되어, I-게이트 트랜지스터 및 3-게이트 트랜지스터 둘다를 위한 소스 및 드레인 영역이 형성된다. 통상적으로 행해지는 바와 같이, 도시되지는 않았지만, p 채널 및 n 채널 디바이스에 대해 분리된 이온 주입 단계가 이용되며, p 채널 및 n 채널 디바이스에 대한 소스 및 드레인의 분리된 주입을 허용하기 위해 보호층이 이용된다.
이와 달리, 실리콘 질화물 부재(17, 18)는 그 자리에 유지되고, 소스 및 드레인 영역은 소정의 각도로 주입되어, 도펀트가 실리콘 바디(15, 16)의 측면들로 들어가도록 할 수 있다.
또한, 스페이서를 형성하여, 보다 약하게 도핑된 소스 및 드레인 영역이 채널 영역에 인접하여 주입되고, 보다 강하게 도핑된 소스 및 드레인 영역은 채널 영역으로부터 떨어지도록 허용할 수 있다. 이것에 대해서는, 위에서 참조한 출원 제 10/816,282 호에 기술되어 있다.
이제, 도 3에 도시된 바와 같이, ILD(30)가 절연층(10)상에 형성된다. ILD(30)는 부재(20, 22)를 둘러싸며, 보이는 바와 같이, 폴리실리콘을 제거시에, 금속의 인레이(inlay)를 허용한다. ILD(30)는, 예컨대, CVD(chemical vapor deposited) 실리콘 이산화물층일 수 있다.
이제, 도 3의 기판은, 예컨대, CMP(chemical mechanical polishing) 프로세스로 평탄화되어, 실리콘 질화물 절연 부재(17, 18)를 노출시킨다. 이것은 도 4(a) 및 4(b)에 도시된다. 부재(17, 18)는, 부재(20, 22)와 같이, ILD(30)의 상부 표면과 동일한 높이로 됨을 주지해야 한다.
이제, 포토레지스트층이 도 4(a) 및 4(b)의 구조물상에 증착되고, 패터닝되어, I-게이트 트랜지스터 영역상의 그 자리에 유지된다. 포토레지스트층(50)은 절연 부재(17)를 덮는다. 도 5에 도시된 바와 같이, 포토레지스트층(50)은 3-게이트 디바이스의 절연 부재(18)를 노출된 채로 남겨둔다.
그 후, 도 6(a) 및 6(b)에 도시된 바와 같이, 에칭 프로세스를 이용하여 플러그 형상 실리콘 질화물 절연 부재(18)를 제거한다. 실리콘 질화물과 ILD(30) 및 희생층 둘다의 사이를 구별하는 에칭제를 이용하여, ILD(30) 및 부재(22)가 실질적으로 그대로 유지되도록 한다. 건식 또는 습식 에칭제가 이용될 수 있다. 부재(18)가 제거되면, 도 6(b)에 도시된 바와 같이, 하부의 실리콘 바디(16)가 노출된다.
다음, 폴리실리콘 희생층이, 예를 들면, 습식 에칭 프로세를 이용하여 제거된다. 결과적인 구조물은 도 7(a) 및 7(b)에 도시되어 있다. 이제, 남아 있는 ILD(30)는, 트랜지스터에 대한 게이트가 제조될 수 있는 형태를 규정한다.
도 8에 도시된 바와 같이, 게이트 유전체층(60)이 각각의 반도체 바디(15, 16) 위 및 그 둘레에 형성된다. 구체적으로, 게이트 유전체는, 그것이 각각의 반도체 바디의 대향 측벽들 뿐만 아니라, 반도체 바디(16) 및 절연 부재(17)의 최상부 표면을 덮도록 증착될 수 있다. 이러한 게이트 유전체는, 금속 산화물 유전체, 예컨대, HfO2 혹은 ZrO, 또는 PZT 혹은 BST와 같은 다른 높은-k 유전체와 같이, 이상적으로 높은 유전 상수를 갖는다. 높은-k 유전체막은 CVD에 의한 것과 같은 임의의 잘 알려진 기법에 의해 형성될 수 있다. 이와 달리, 게이트 유전체는 성장된 유전체일 수 있다. 일 실시예에서, 게이트 유전체층(60)은, 건식/습식 산화 프로세스로 성장된 실리콘 이산화물막이다. 예를 들어, 실리콘 이산화물막은 5 내지 50Å 사이의 두께로 성장된다. (공형으로 증착된 유전체층이 도 8에 도시된다.)
다음, 도 8에 도시된 바와 같이, 게이트 전극 (금속) 층(61)이 게이트 유전체층(60) 위에 형성된다. 게이트 전극층(61)은 적절한 게이트 전극 물질의 블랭킷 증착에 의해 형성될 수 있다. 일 실시예에서, 게이트 전극 물질은 텅스텐, 탄탈, 티타늄 및/또는 질화물 및 그들의 합금과 같은 금속막을 포함한다. n 채널의 I-게이트 및 3-게이트 트랜지스터의 경우, 4.0 내지 4.6 eV 범위내의 일함수가 이용될 수 있다. p 채널의 I-게이트 및 3-게이트 트랜지스터의 경우, 4.6 내지 5.2 eV의 일함수가 이용될 수 있다. 따라서, n 채널 및 p 채널 트랜지스터 둘다를 갖는 기판의 경우, 2개의 분리된 금속 증착 프로세스가 이용될 필요가 있을 수 있다.
금속층(61)은, 예를 들면, CMP를 이용하여 평탄화되며, 도 9(a)에 도시된 바와 같이, 그러한 평탄화는 절연 부재(17)의 적어도 상부 표면이 노출될 때까지 계속된다. 이것은 금속이 부재(17)로 확장되지 않도록 보장하기 위해 수행되는데, 이것은, 그렇지 않은 경우, I-게이트 트랜지스터에서의 게이트들이 함께 단락되기 때문이다. 도 9에서 보이는 바와 같이, I-게이트 트랜지스터에 대해 2개의 독립적인 게이트(62, 64)가 있으며, 3-게이트 디바이스에 대해 하나의 게이트(65)가 있다.
3-게이트 트랜지스터에 대한 게이트(65)는 바닥 표면과 대향하는 최상부 표면을 가지며, 도 9(b)에 가장 잘 도시된 3-게이트 구조물에 인접하여 형성된 한 쌍의 측방향으로 대향하는 측벽을 갖는다. 이들 측벽은 실리콘 바디의 상부 표면상에서 접속된다. 따라서, 게이트는 3개의 측면상의 3-게이트 트랜지스터의 채널 영역을 둘러싼다. I-게이트 트랜지스터의 경우, 2개의 독립적인 게이트(62, 64)가, ILD가 제거된 것으로 도시된 도 9(b)에 다시 가장 잘 도시된, 절연 부재(17)에 의해 분리된다.
또한, 도 9(b)에 가장 잘 도시된 바와 같이, 실리콘 바디(15, 16)가 절연층(10)상에 도시된다. 소스 영역(68, 70)이, 드레인 영역(71, 72)과 더불어 각각의 트랜지스터에 대해 도시된다. 직각으로 배치된 핀과 더불어 독립적인 게이트(62, 64)를 쉽게 볼 수 있다. 게이트(65)에 대해서도 마찬가지의 것이 적용된다. 접촉 영역(80, 81, 82)에 의해 도시된 바와 같이, 이들 핀은 하부의 금속화층으로부터 게이트까지 보다 용이한 접촉이 행해지도록 허용한다. 도 9(b)에는 도시되지 않았지만, 하부의 금속화층으로부터 도시되지 않은 접촉부를 통해 게이트로 및 소스 및 드레인 영역으로 접촉이 행해진다.
I-게이트 트랜지스터는 3-게이트 트랜지스터와 더불어 논리 회로에서 이용될 수 있다. I-게이트 트랜지스터는, 소정의 회로에서 그것을 바람직하게 만드는 특성을 갖는다. 예컨대, 단일의 I-게이트 트랜지스터가, 한 개 또는 두 개의 게이트에 인가된 전위에 따라, 고 전류 및 중간 전류 디바이스 둘다를 제공할 수 있다. 그러한 디바이스는 슬립 모드(sleep mode) 또는 전력 감소 모드(power-down mode)에서의 누설을 감소시키도록 "스트롱 오프(strong off)" 디바이스를 제공할 수 있다. 또한, I-게이트 트랜지스터는, 트리클 전류(trickle current)를 허용함으로써, 사전충전 라인에 대한 디바이스를 제공한다. 전술한 특허 출원에서, I-게이트 디바이스는 DRAM 셀로서 이용되며, 전술한 프로세스는 그러한 DRAM 제조와 관련하여 이용될 수 있다. 이 경우, 실리콘 바디(15)는 복수의 평행한 이격 라인에 형성된 길게 연장된 바디이며, DRAM 셀의 어레이에서 이용된다.
도면들에 있어서, 2개의 분리된 실리콘 바디가 도시되었지만, 단일의 바디가 이용될 수 있음을 이해할 것이다. 그리고, 3-게이트 및 I-게이트 트랜지스터는 서로 직렬로 제조될 수 있다. 이 경우, 직렬 트랜지스터들은 하나의 소스/드레인 영역을 갖는다.
따라서, 소정의 프로세스가 기술되었으며, 집적 회로를 위한 결과적인 구조물은 공통 기판상에 I-게이트 및 3-게이트 구조물 둘다를 갖는다.

Claims (20)

  1. 반도체 트랜지스터를 제조하는 방법으로서,
    중첩되는 절연 부재를 갖는 적어도 2개의 실리콘 바디를 형성하는 단계와,
    상기 2개의 실리콘 바디 및 상기 중첩되는 절연 부재 근처에 희생층을 형성하는 단계와,
    상기 실리콘 바디와 교차되는 게이트 영역을 규정하는 상기 희생층을 패터닝하는 단계와,
    상기 절연 부재가 상기 게이트 영역 위에 노출되도록 상기 패터닝된 희생층 및 상기 실리콘 바디를 상기 중첩되는 절연 부재로 유전체층에 밀봉(enclosing)하는 단계와,
    상기 절연 부재 중 하나가 에칭되는 것을 방지하도록 그 절연 부재를 덮는 단계와,
    상기 절연 부재 중 하나가 덮혀지는 동안 상기 절연 부재 중 다른 하나를 에칭하는 단계와,
    상기 유전체층을 그대로 남겨두면서 상기 패터닝된 희생층을 제거하는 단계와,
    상기 게이트 영역 내에 게이트 절연층 및 금속 게이트층을 형성하는 단계를 포함하며,
    I-게이트 트랜지스터는 상기 절연 부재 중 하나가 에칭되는 것이 방지되는 게이트 영역에 형성되고, 3-게이트 트랜지스터는 상기 절연 부재 중 다른 하나가 에칭되는 게이트 영역에 형성되는
    반도체 트랜지스터 제조 방법.
  2. 제 1 항에 있어서,
    상기 절연 부재를 노출시키도록 상기 유전체층을 평탄화하는 단계를 포함하는 반도체 트랜지스터 제조 방법.
  3. 제 2 항에 있어서,
    상기 실리콘 바디는 단결정 실리콘을 포함하는 반도체 트랜지스터 제조 방법.
  4. 제 3 항에 있어서,
    상기 절연 부재는 실리콘 질화물을 포함하는 반도체 트랜지스터 제조 방법.
  5. 제 4 항에 있어서,
    상기 희생층은 폴리실리콘을 포함하는 반도체 트랜지스터 제조 방법.
  6. 제 5 항에 있어서,
    상기 평탄화는 화학 기계적 연마(CMP)를 포함하는 반도체 트랜지스터 제조 방법.
  7. 제 1 항에 있어서,
    상기 희생층의 패터닝 이후에, 노출되는 상기 절연 부재를 제거하는 단계를 포함하는 반도체 트랜지스터 제조 방법.
  8. 제 7 항에 있어서,
    상기 희생층의 패터닝 이후에, 상기 실리콘 바디에 소스 및 드레인 영역을 도핑하는 단계를 포함하는 반도체 트랜지스터 제조 방법.
  9. 삭제
  10. 제 1 항에 있어서,
    상기 절연 부재 중 다른 하나를 에칭하는 단계는, 상기 유전체층에 대한 에칭율보다 상기 절연 부재에 대해 더 높은 에칭율을 갖는 에칭제로 수행되는 반도체 트랜지스터 제조 방법.
  11. 반도체 트랜지스터를 제조하는 방법으로서,
    제 1 및 제 2 절연 부재를 각각 갖는 제 1 및 제 2 실리콘 바디를 에칭하는 단계와,
    소스 및 드레인 영역을 규정하도록 상기 제 1 및 제 2 절연 부재의 일부분을 제거하는 단계와,
    상기 소스 및 드레인 영역을 도핑하는 단계와,
    상기 절연 부재의 상측 표면이 노출되도록 상기 제 1 및 제 2 실리콘 바디를 절연층으로 둘러싸는 단계와,
    상기 제 1 절연 부재를 그대로 남겨두면서, 상기 제 2 절연 부재를 제거하는 단계와,
    상기 제 1 실리콘 바디의 대향 측면 상에 제 1 게이트 구조물을 형성하는 단계로서, 상기 제 1 게이트 구조물은 상기 제 1 절연 부재에 의해 분리된 2개의 독립적인 게이트를 갖는 단계와,
    상기 제 2 실리콘 바디의 3개의 측면 상에 제 2 게이트 구조물을 형성하는 단계를 포함하는
    반도체 트랜지스터 제조 방법.
  12. 제 11 항에 있어서,
    상기 제 1 및 제 2 게이트 구조물은, 높은-k 절연부에 의해 그들 각각의 실리콘 바디로부터 절연되는 금속인 반도체 트랜지스터 제조 방법.
  13. 제 12 항에 있어서,
    상기 제 1 및 제 2 절연 부재를 규정하도록 희생층을 형성하여 패터닝하는 단계를 포함하며, 상기 제 1 및 제 2 게이트 구조물은 상기 절연층을 둘러싸는 희생층의 제거에 의해 형성되는 반도체 트랜지스터 제조 방법.
  14. 제 13 항에 있어서,
    상기 희생층은 폴리실리콘을 포함하고, 상기 제 1 및 제 2 절연 부재는 실리콘 질화물을 포함하는 반도체 트랜지스터 제조 방법.
  15. 삭제
  16. 삭제
  17. 삭제
  18. 삭제
  19. 삭제
  20. 삭제
KR1020077007073A 2004-09-29 2005-09-29 반도체 트랜지스터 제조 방법 KR100900831B1 (ko)

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US7859053B2 (en) 2010-12-28
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US20060068550A1 (en) 2006-03-30
US7037790B2 (en) 2006-05-02
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