US20070287256A1 - Contact scheme for FINFET structures with multiple FINs - Google Patents
Contact scheme for FINFET structures with multiple FINs Download PDFInfo
- Publication number
- US20070287256A1 US20070287256A1 US11/448,702 US44870206A US2007287256A1 US 20070287256 A1 US20070287256 A1 US 20070287256A1 US 44870206 A US44870206 A US 44870206A US 2007287256 A1 US2007287256 A1 US 2007287256A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor layer
- parallel oriented
- gate electrode
- bodies
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000001459 lithography Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 229910016570 AlCu Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000001878 scanning electron micrograph Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000224 chemical solution deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229910052914 metal silicate Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 125000003821 2-(trimethylsilyl)ethoxymethyl group Chemical group [H]C([H])([H])[Si](C([H])([H])[H])(C([H])([H])[H])C([H])([H])C(OC([H])([H])[*])([H])[H] 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
Definitions
- the present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or local interconnects. The present invention also relates to a method for fabricating a FINFET-containing structure having multiple FINs that are merged together. The inventive method is suitable for actual FINFET technology and greatly improves the layout efficiency of multiple FINFETs.
- Double gated and tri-gated transistors have higher scalability than single gated FETs since the multiple gates help to control the potential in the body.
- the FINFET has been considered as one of the most promising candidates for 32 nm node technology and beyond because it combines the critical elements of superior scalability found in all multi gated devices with the manufacturability of conventional transistors.
- the body of a FINFET device having a double gate or a tri-gate consists of a thin (on the order of about 10 nm n) vertical crystalline semiconducting wall called a FIN which typically extends from a surface of an underlying substrate.
- a FIN thin vertical crystalline semiconducting wall
- gate material warps around both sides of the FIN creating a channel on each side thereof.
- the gate material is located atop the FIN as well as around both sides of the FIN creating a channel on each side of the FIN as well as atop the FIN.
- the main advantages of a FINFET structure over other multi-gated device designs is that the self-aligned gates can be fabricated using a single lithographic and etching step.
- FIG. 1B In a conventional FINFET gate design layout such as shown in FIG. 1B , large source/drain landing (i.e., contact pads) 12 are used to connect an array of narrow FINS 14 in parallel at two ends.
- reference numeral 10 denotes the active area
- reference numeral 16 denotes the gate.
- FIG. 1A shows a conventional design layout for a planar FET.
- the planar FET ground rule is equal to the contact-gate overlay which is the distance d 1 between the source/drain contact pads 12 and the gates 16 .
- the FINFET ground rule is equal to the contact-gate overlay plus the contact-active overlay.
- the ground rule for the FINFET structure is thus represented by the distance d 2 .
- the particular design layout shown in FIG. 1B is, however, unsuitable for actual FINFET technology since the use of source/drain landing pads inevitably increases the gate contact pitch due to overlay requirements.
- the minimum spacing from the source/drain contact to the gate is the contact-to-gate overlay plus the contact-to-active overlay. This is undesirable since the layout efficiency of a FINFET is severely degraded over that of a conventional planar FET. Furthermore, the use of source/drain landing pads also complicates spacer etching of the small space between the FINFET gate and the landing pad.
- the minimum pitch required for active layers will be reduced to approximately 120 mm or less.
- the source/drain contact formation becomes a serious challenge due to gate-to-active overlay requirements and the need for raised source/drain regions for series resistance reduction.
- the present invention provides an alternative contact scheme for FINFET structures including multiple FINs.
- the present invention provides an alternative contact scheme in which each individual FIN within the structure is merged together by selective epitaxy.
- the selective epitaxy provides epitaxially (i.e., epi) grown semiconductor material that straps (i.e., merges) the individual FINs together without the need of large contact pads or local interconnects, as is typically the case with prior art FINFET structures.
- the inventive “FIN only” array design makes it easier to adopt new advanced lithographic methods.
- the inventive approach described herein i.e., the merged FIN approach, provides lower parasitic capacitance and does not require any additional processing steps.
- the present invention thus provides a FINFET structure comprising:
- FINs parallel oriented semiconducting bodies
- a nitride-containing spacer located on a sidewall of said common patterned gate electrode in a region in which said common patterned gate electrode intercrosses with at least one of said parallel oriented semiconducting bodies;
- the present invention also contemplates a method of fabricating the same.
- the inventive method includes the steps of:
- FINs parallel oriented semiconducting bodies
- FIG. 1A is a diagram showing the design layout of a prior art planar MOSFET, where the minimum source/drain contact to gate spacing is determined by the gate-to-contact overlayer
- FIG. 1B is a diagram showing the design layout for a prior art FINFET with source/drain landing pads, where the minimum source/drain contact-to-gate spacing is limited by the contact-to-active overlay in addition to the contact-to-gate overlay.
- FIG. 2 is a diagram of a prior art FINFET structure including multiple FINs that are strapped together with a local interconnect.
- FIG. 3 is a diagram of the inventive FINFET structure including multiple FINs that merged (i.e., strapped) together by selective epitaxial growth of a semiconductor material.
- FIGS. 4-12 are pictorial representations illustrating the basic processing steps of the present application.
- various views including cross sectional and top-down prospective views are shown.
- a view through line A-A′ is shown, while in other a view through line B-B′ is shown.
- the line A-A′ is a line that runs perpendicular to the FINs, while line B-B′ is a line running parallel through one of the FINs.
- FIG. 13 is a scanning electron micrograph (SEM) of a conventional FINFET with multiple FINS at a 120 nm pitch obtained using e-beam lithography; all the FINs in the prior art structure are connected at the end using a large source/drain contact pad.
- SEM scanning electron micrograph
- FIG. 14 is a SEM of the inventive FINFET structure where all the individual FINs are printed without source/drain contacts and prior to epitaxy.
- FIG. 15 is a SEM of a FINFET structure of FIG. 14 after selective raised source/drain formation of a 25 nm epi Si.
- FIG. 16 is a SEM of a FINFET structure of FIG. 14 after merging the individual FINs together using a 50 nm selective epi Si.
- the present invention which provides a FINFET structure with multiple FINs that are merged together by an epitaxially grown semiconductor material and a method of fabricating such a FINFET structure, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application.
- the drawings of the present application which are referred to herein below in greater detail, are provided for illustrative purposes and, as such, they are not drawn to scale.
- the present invention provides a new contact design layout for a FINFET having multiple parallel oriented FINs in which the parallel oriented FINs are merged together without utilizing source/drain contact pads or local interconnects, as is shown, for example, in FIGS. 1B and 2 .
- the multiple parallel oriented FINs of the FINFET structure of the present application are merged (i.e., strapped) together with an epitaxially grown semiconductor material.
- the inventive contact scheme is illustrated in FIG. 3 .
- FIG. 3 is a diagram showing the inventive FINFET contact scheme in which the multiple parallel oriented FINs are merged together with a selectively grown epitaxial semiconductor material.
- FIG. 3 is a diagram showing the inventive FINFET contact scheme in which the multiple parallel oriented FINs are merged together with a selectively grown epitaxial semiconductor material.
- reference numeral 72 ′ represents the epitaxially grown semiconductor material
- reference numeral 60 denotes the parallel oriented FINs
- reference numeral 69 denotes the common patterned gate electrode.
- the design layout shown in FIG. 3 provides lower parasitic capacitance than prior art approaches and thus, it represents an advancement in the art.
- FIG. 4 illustrates a semiconductor-on-insulator (SOI) substrate 50 after forming a hard mask 58 on an upper surface of the SOI substrate 50 .
- SOI semiconductor-on-insulator
- the SOI substrate 50 includes a buried insulating region 54 that is positioned between a bottom semiconductor layer 52 and a top semiconductor layer 56 .
- the top semiconductor layer 56 is sometimes referred to in the art as an SOI layer of an SOI substrate.
- semiconductor as used herein to describe the bottom semiconductor layer 52 and the top semiconductor layer 56 denotes any semiconducting material including, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other like III/V compound semiconductors. Multilayers of these semiconductors are also contemplated herein. In a preferred embodiment, both semiconductor layers, i.e., the bottom semiconductor layer 52 and the top semiconductor layer 56 of the SOI substrate 50 are both comprised of Si.
- the buried insulating layer 54 may be a crystalline or non-crystalline oxide or nitride. In a preferred embodiment of the present invention, the buried insulating layer 54 is an oxide.
- the buried insulating layer 54 may be continuous, as shown, or it may be discontinuous. When a discontinuous buried insulating region is present, the insulating region exists as isolated islands that are surrounded by semiconductor material.
- the SOI substrate 50 may be a standard (100) oriented wafer, a (110) oriented wafer, or any other surface orientation. Hybrid SOI substrates having surface regions of different crystallographic orientations are also contemplated.
- the SOI substrate 50 may be formed utilizing standard processes including for example, SIMOX (separation by ion implantation of oxygen) or layer transfer.
- SIMOX separation by ion implantation of oxygen
- layer transfer an optional thinning step may follow the bonding of two semiconductor wafers together. The optional thinning step reduces the thickness of the top semiconductor layer to a layer having a thickness that is more desirable.
- the thickness of the top semiconductor layer 56 of the SOI substrate 50 is from about 100 to about 1000 ⁇ , with a thickness from about 500 to about 700 ⁇ being more highly preferred. If the thickness of the top semiconductor layer 56 is not within the above mentioned range, a thinning step such as, for example, planarization or etching may be used to reduce the thickness of the top semiconductor layer 56 to a value within the range mentioned above. The thinning step is performed prior to forming the hard mask 58 on a surface of top semiconductor layer 56 .
- the buried insulating layer 54 of the SOI substrate 50 has a thickness from about 10 to about 2000 ⁇ , with a thickness from about 1000 to about 1500 ⁇ being more highly preferred.
- the thickness of the bottom semiconductor layer 52 of the SOI substrate 50 is inconsequential to the present invention.
- the hard mask 58 is then formed on a surface of the top semiconductor layer 56 of the SOI substrate 50 utilizing a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation or other like deposition processes.
- a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation or other like deposition processes.
- the hard mask 58 may be formed by a thermal process such as, for example, oxidation or nitridation. Any combination of the above mentioned processes can also be used in forming the hard mask 58 .
- the hard mask 58 comprises an oxide, nitride, oxynitride or any combination thereof including multilayers.
- the hard mask 58 is an oxide including, for example, silicon oxide or silicon nitride.
- the thickness of the hard mask 58 may vary depending on the technique used in forming the same, the material of the hard mask itself, and the number of layers within the hard mask layer. Typically, the hard mask 58 has a thickness from about 200 to about 800 ⁇ , with a thickness from about 400 to about 600 ⁇ being more typical. It is noted that the hard mask 58 is utilized in the present invention during a subsequent etching of the top semiconductor layer 56 to define the active regions as well as to protect the subsequently formed FIN during a gate etch and also during a spacer etch.
- FIGS. 5A-5C shows the structure of FIG. 4 after formation of a plurality of parallel oriented semiconducting bodies 60 . It is noted that each of the parallel oriented semiconducting bodies 60 thus formed have a narrow width on the order of about 20 nm or less and, a vertical thickness that is within the range provided above as such, they are referred hereinafter as FINs.
- Each of the parallel oriented FINs 60 shown in FIGS. 5A-5C is formed by lithography and etching.
- the lithographic step includes applying a photoresist (not shown) atop the hard mask 58 , exposing the photoresist to a desired pattern of radiation, and developing the exposed resist utilizing a conventional resist developer.
- the etching process comprises drying etching and/or wet chemical etching.
- suitable dry etching processes that can be used in the present invention include reactive ion etching, ion beam etching, plasma etching or laser ablation. Typically, a reactive ion etching process or an ion beam etching process is used.
- the etching process first transfers the pattern from the patterned photoresist to the hard mask 58 and thereafter to the underlying top semiconductor layer 56 .
- the patterned photoresist is typically, but not necessarily always, removed after the pattern has been transferred to the hard mask 58 .
- a conventional resist stripping process is used to remove the patterned photoresist from the structure.
- a trench opening 62 is formed into an exposed portion of the buried insulating layer 54 that extends down into the semiconductor substrate 52 prior to forming the FINS 60 .
- the trench opening 62 is formed by lithography and etching and is used for alignment purposes.
- the trench opening 62 is typically lined with a dielectric material 65 such as an oxide.
- the dielectric material 65 is formed by conventional techniques well known to those skilled in the art.
- the structure including the trench opening 62 and dielectric material 65 is also shown in FIG. 5B . It is noted that the use of this trench opening 62 is optional
- a sacrificial oxide 64 is formed that lines the exposed sidewalls of each of the parallel oriented FINs 60 .
- the sacrificial oxide 64 is formed by a deposition process such as, for example, CVD, PECVD, ALD, evaporation or chemical solution deposition. Alternatively, a thermal oxidation process can be used to form sacrificial oxide 64 .
- the sacrificial oxide 64 is removed from the sidewalls of each FIN 60 prior to forming the gate stack utilizing a conventional stripping process.
- the hard mask 58 can be removed atop each of the FINs 60 at this point of the present invention. This particular embodiment allows for the fabrication of a tri-gated device since the gate dielectric to be subsequently formed would be present on the sides and the top of each of the FINs 60 .
- FIG. 6 is a view through line A-A′ which runs perpendicular to the FINs 60 .
- the gate stack 66 comprises a gate dielectric 67 and a gate electrode 69 .
- the gate dielectric 67 can be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation.
- the gate dielectric 67 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes.
- the gate dielectric 67 may also be formed utilizing any combination of the above processes.
- the gate dielectric 67 is comprised of an insulating material having a dielectric constant of about 4.0 or greater. All dielectric constants mentioned herein are relative to a vacuum unless otherwise noted.
- the gate dielectric 67 comprises a high k material.
- the term “high k” denotes a dielectric having a dielectric constant of greater than 4.0, preferably greater than 7.0.
- the gate dielectric 67 employed in the present invention includes, but is not limited to: an oxide, nitride, oxynitride and/or silicate including metal silicates and nitrided metal silicates.
- the gate dielectric 67 is comprised of an oxide such as, for example, SiO 2 , HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , Ga 2 O 3 , GdGaO and mixtures thereof.
- Highly preferred examples of gate dielectrics include HfO 2 , hafnium silicate and hafnium silicon oxynitride.
- the physical thickness of the gate dielectric 67 may vary, but typically, the gate dielectric 67 has a thickness from about 0.5 to about 10 nm, with a thickness from about 0.5 to about 3 nm being more typical.
- the gate electrode 69 is comprised of a conductive material, including, for example, polySi, SiGe, a metal, a metal alloy, a metal silicide, a metal nitride, a metal carbide or combinations including multilayers thereof.
- a diffusion barrier (not shown), such as TiN or TaN, can be positioned between each of the conductive layers.
- the gate electrode 69 is formed utilizing a conventional deposition process including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, sputtering, plating, evaporation and any other like deposition processes.
- a conventional deposition process including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, sputtering, plating, evaporation and any other like deposition processes.
- an in-situ deposition process can be used or alternatively deposition followed by ion implantation can be used.
- the thickness of the gate electrode 69 is not critically to the present invention. Typically, however, the thickness of the gate electrode 69 is from about 50 to about 200 nm.
- FIGS. 7A-7C show the structure of FIG. 6 after planarization which removes a portion of the gate electrode 69 .
- the planarization process is performed utilizing a conventional planarization process such as, for example, chemical mechanical polishing (CMP) and/or grinding.
- CMP chemical mechanical polishing
- the gate electrode 69 is patterned by lithography and etching providing the structure shown, for example, in FIGS. 8A-8C .
- the patterned gate electrode which is common to each of the parallel oriented FINs 60 , is denoted by reference numeral 69 ′. It is noted that the common patterned gate electrode 69 ′ is oriented perpendicular to each of the parallel oriented FINs 60 .
- the lithographic and etching processes employed in patterning the gate electrode 69 are the same as those mentioned above for patterning the FINs 60 .
- an insulating layer 68 (including an oxide, nitride, or multilayers thereof) is formed on all exposed surfaces of the patterned gate electrode 69 ′.
- the structure including the insulating layer 68 is also shown in FIGS. 8B-8C .
- the insulating layer 68 is formed utilizing a conventional deposition process or by a conventional thermal growth method.
- FIGS. 9A-9C show the structure of FIGS. 8A-8C after forming a nitride-containing spacer 70 on exposed sidewalls of the common patterned gate electrode 69 ′ which includes the insulating layer 68 .
- the nitride-containing spacer 70 is formed only in regions in which a FIN and a corresponding patterned gate conductor intercross.
- the nitride-containing spacer 70 is formed by deposition and etching. Typically, an aggressive over etch using a reactive ion process is employed in forming the nitride-containing spacer 70 .
- FIGS. 10A-10C shows the structure after partial growth of an epitaxial semiconductor layer 72 .
- the partial growth is performed utilizing a selective epitaxial growth process. It is noted that at this point of the present invention the FINs are not merged. This is evidence by the space that is still shown to be present between each of the parallel oriented FINs 60 .
- the epitaxially grown semiconductor material typically comprises a Si-containing semiconductor material such as, for example, Si or SiGe.
- the lateral thickness of the partially grown epitaxial semiconductor layer 72 is typically from about 20 to about 50 nm.
- the partially grown epitaxial semiconductor layer 72 has a thickness that is generally associated with conventional raised source/drain regions of prior art FINFET structures.
- source/drain implantations may be performed to form source/drain regions (not specifically shown or labeled) within the partially grown epitaxial semiconductor layer 72 .
- FIGS. 11A-11C show the structure after full growth of an epitaxial semiconductor layer 72 ′.
- the fully grown epitaxial semiconductor layer 72 ′ merges each of the parallel oriented FINs 60 .
- the lateral thickness of the fully grown epitaxial semiconductor layer 72 ′ varies and is dependent on the number of FINs within a given structure. It is noted that the thickness of the fully grown epitaxial semiconductor layer 72 ′ must merge (i.e., cover) each of the FINs present in the structure.
- FIGS. 12A-12C shows the structure after contact 74 formation.
- the contacts 74 are formed utilizing standard techniques that are well known to those skilled in the art. For example, contact openings are first formed into exposed portions of the fully grown epitaxial semiconductor layer 72 ′ utilizing lithography and etching. After etching and removal of the resist material, a contact metal such as, for example, Cu, Al, W, or AlCu is formed within the contact openings forming contacts 74 .
- FIG. 13 is a scanning electron micrograph (SEM) of a conventional FINFET with multiple FINS at a 120 nm pitch obtained using e-beam lithography. In this SEM, all of the parallel oriented FINs are connected at the end using a large source/drain contact pad.
- SEM scanning electron micrograph
- FIG. 14 is a SEM of the inventive FINFET structure where all the individual parallel oriented FINs are printed without source/drain contacts and prior to epitaxy.
- FIG. 15 is a SEM of the FINFET structure of FIG. 14 after selective raised source/drain formation of a 25 nm epi Si (i.e., formation of the partially epitaxial semiconductor layer).
- FIG. 16 is a SEM of a FINFET structure of FIG. 14 after merging the individual parallel oriented FINs together using a 50 nm selective epi Si layer (i.e., fully grown epitaxially semiconductor layer).
- the merging of the FINs reduces the series resistance. It is noted that after the FINs have been merged, the FINFET devices look exactly the same planar FETs, thus the standard middle of the liner processing can be applied to the FINFET devices of the present invention.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
- The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or local interconnects. The present invention also relates to a method for fabricating a FINFET-containing structure having multiple FINs that are merged together. The inventive method is suitable for actual FINFET technology and greatly improves the layout efficiency of multiple FINFETs.
- Double gated and tri-gated transistors have higher scalability than single gated FETs since the multiple gates help to control the potential in the body. Among the several double gated and tri-gated device architectures, the FINFET has been considered as one of the most promising candidates for 32 nm node technology and beyond because it combines the critical elements of superior scalability found in all multi gated devices with the manufacturability of conventional transistors.
- The body of a FINFET device having a double gate or a tri-gate consists of a thin (on the order of about 10 nm n) vertical crystalline semiconducting wall called a FIN which typically extends from a surface of an underlying substrate. In double gated FINFETs, gate material warps around both sides of the FIN creating a channel on each side thereof. For a tri-gate FINFET device, the gate material is located atop the FIN as well as around both sides of the FIN creating a channel on each side of the FIN as well as atop the FIN.
- The main advantages of a FINFET structure over other multi-gated device designs is that the self-aligned gates can be fabricated using a single lithographic and etching step.
- In a conventional FINFET gate design layout such as shown in
FIG. 1B , large source/drain landing (i.e., contact pads) 12 are used to connect an array ofnarrow FINS 14 in parallel at two ends. InFIG. 1B ,reference numeral 10 denotes the active area, whilereference numeral 16 denotes the gate. For comparison,FIG. 1A shows a conventional design layout for a planar FET. - For
FIG. 1A , the planar FET ground rule is equal to the contact-gate overlay which is the distance d1 between the source/drain contact pads 12 and thegates 16. InFIG. 1B , the FINFET ground rule is equal to the contact-gate overlay plus the contact-active overlay. The ground rule for the FINFET structure is thus represented by the distance d2. The particular design layout shown inFIG. 1B is, however, unsuitable for actual FINFET technology since the use of source/drain landing pads inevitably increases the gate contact pitch due to overlay requirements. - Moreover, and in a conventional FINFET design layout, the minimum spacing from the source/drain contact to the gate is the contact-to-gate overlay plus the contact-to-active overlay. This is undesirable since the layout efficiency of a FINFET is severely degraded over that of a conventional planar FET. Furthermore, the use of source/drain landing pads also complicates spacer etching of the small space between the FINFET gate and the landing pad.
- In 32 nm node technology and beyond, the minimum pitch required for active layers will be reduced to approximately 120 mm or less. When such a small pitch is used, the source/drain contact formation becomes a serious challenge due to gate-to-active overlay requirements and the need for raised source/drain regions for series resistance reduction.
- Elimination of source/drain landing pads simultaneously solves both of the above mentioned problems, but requires that parallel FINS be strapped together. One reported idea, which is described by J. A. Choi et al., IEDM, 2004, p. 647, is to strap the FINs together by local interconnects. This particular scheme is shown, for example, in
FIG. 2 . One problem with the scheme described by J. A. Choi et al. is that the addition of local interconnects significantly increases the parasitic capacitance, thus degrading the overall circuit performance. - In view of the above, there is a need for providing an alternative contact scheme for FINFET structures that include multiple FINs.
- The present invention provides an alternative contact scheme for FINFET structures including multiple FINs. In particular, the present invention provides an alternative contact scheme in which each individual FIN within the structure is merged together by selective epitaxy. The selective epitaxy provides epitaxially (i.e., epi) grown semiconductor material that straps (i.e., merges) the individual FINs together without the need of large contact pads or local interconnects, as is typically the case with prior art FINFET structures. The inventive “FIN only” array design makes it easier to adopt new advanced lithographic methods.
- Compared with the local interconnect approach mentioned above, the inventive approach described herein, i.e., the merged FIN approach, provides lower parasitic capacitance and does not require any additional processing steps.
- In general terms, the present invention thus provides a FINFET structure comprising:
- a plurality of parallel oriented semiconducting bodies (i.e., FINs) which extend above a surface of a substrate;
- a common patterned gate electrode surrounding said plurality of parallel oriented semiconducting bodies;
- a nitride-containing spacer located on a sidewall of said common patterned gate electrode in a region in which said common patterned gate electrode intercrosses with at least one of said parallel oriented semiconducting bodies; and
- an epitaxial semiconductor layer that merges each of said parallel oriented semiconducting bodies together.
- In addition to the above structure, the present invention also contemplates a method of fabricating the same. The inventive method includes the steps of:
- providing a plurality of parallel oriented semiconducting bodies (i.e., FINs) which extend above a surface of a substrate;
- forming a common patterned gate electrode surrounding said plurality of parallel oriented semiconducting bodies;
- forming a nitride-containing spacer on a sidewall of said common patterned gate electrode in a region in which said common patterned gate electrode intercrosses with at least one of said parallel oriented semiconducting bodies; and
- epitaxially growing an epitaxial semiconductor layer that merges each of said parallel oriented semiconducting bodies together.
-
FIG. 1A is a diagram showing the design layout of a prior art planar MOSFET, where the minimum source/drain contact to gate spacing is determined by the gate-to-contact overlayer, whileFIG. 1B is a diagram showing the design layout for a prior art FINFET with source/drain landing pads, where the minimum source/drain contact-to-gate spacing is limited by the contact-to-active overlay in addition to the contact-to-gate overlay. -
FIG. 2 is a diagram of a prior art FINFET structure including multiple FINs that are strapped together with a local interconnect. -
FIG. 3 is a diagram of the inventive FINFET structure including multiple FINs that merged (i.e., strapped) together by selective epitaxial growth of a semiconductor material. -
FIGS. 4-12 are pictorial representations illustrating the basic processing steps of the present application. In some of these drawings, various views including cross sectional and top-down prospective views are shown. In some embodiments, a view through line A-A′ is shown, while in other a view through line B-B′ is shown. The line A-A′ is a line that runs perpendicular to the FINs, while line B-B′ is a line running parallel through one of the FINs. -
FIG. 13 is a scanning electron micrograph (SEM) of a conventional FINFET with multiple FINS at a 120 nm pitch obtained using e-beam lithography; all the FINs in the prior art structure are connected at the end using a large source/drain contact pad. -
FIG. 14 is a SEM of the inventive FINFET structure where all the individual FINs are printed without source/drain contacts and prior to epitaxy. -
FIG. 15 is a SEM of a FINFET structure ofFIG. 14 after selective raised source/drain formation of a 25 nm epi Si. -
FIG. 16 is a SEM of a FINFET structure ofFIG. 14 after merging the individual FINs together using a 50 nm selective epi Si. - The present invention, which provides a FINFET structure with multiple FINs that are merged together by an epitaxially grown semiconductor material and a method of fabricating such a FINFET structure, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. The drawings of the present application, which are referred to herein below in greater detail, are provided for illustrative purposes and, as such, they are not drawn to scale.
- In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
- It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
- As stated above, the present invention provides a new contact design layout for a FINFET having multiple parallel oriented FINs in which the parallel oriented FINs are merged together without utilizing source/drain contact pads or local interconnects, as is shown, for example, in
FIGS. 1B and 2 . Instead, the multiple parallel oriented FINs of the FINFET structure of the present application are merged (i.e., strapped) together with an epitaxially grown semiconductor material. The inventive contact scheme is illustrated inFIG. 3 . Specifically,FIG. 3 is a diagram showing the inventive FINFET contact scheme in which the multiple parallel oriented FINs are merged together with a selectively grown epitaxial semiconductor material. InFIG. 3 ,reference numeral 72′ represents the epitaxially grown semiconductor material,reference numeral 60 denotes the parallel oriented FINs andreference numeral 69 denotes the common patterned gate electrode. The design layout shown inFIG. 3 provides lower parasitic capacitance than prior art approaches and thus, it represents an advancement in the art. - Reference is now made to
FIGS. 4-12 which illustrate the basic processing steps that are utilized in the present invention to provide the contact scheme shown inFIG. 3 .FIG. 4 illustrates a semiconductor-on-insulator (SOI)substrate 50 after forming ahard mask 58 on an upper surface of theSOI substrate 50. - The
SOI substrate 50 includes a buried insulatingregion 54 that is positioned between abottom semiconductor layer 52 and atop semiconductor layer 56. Thetop semiconductor layer 56 is sometimes referred to in the art as an SOI layer of an SOI substrate. - The term “semiconductor” as used herein to describe the
bottom semiconductor layer 52 and thetop semiconductor layer 56 denotes any semiconducting material including, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other like III/V compound semiconductors. Multilayers of these semiconductors are also contemplated herein. In a preferred embodiment, both semiconductor layers, i.e., thebottom semiconductor layer 52 and thetop semiconductor layer 56 of theSOI substrate 50 are both comprised of Si. - The buried insulating
layer 54 may be a crystalline or non-crystalline oxide or nitride. In a preferred embodiment of the present invention, the buried insulatinglayer 54 is an oxide. The buried insulatinglayer 54 may be continuous, as shown, or it may be discontinuous. When a discontinuous buried insulating region is present, the insulating region exists as isolated islands that are surrounded by semiconductor material. - The
SOI substrate 50 may be a standard (100) oriented wafer, a (110) oriented wafer, or any other surface orientation. Hybrid SOI substrates having surface regions of different crystallographic orientations are also contemplated. - The
SOI substrate 50 may be formed utilizing standard processes including for example, SIMOX (separation by ion implantation of oxygen) or layer transfer. When a layer transfer process is employed, an optional thinning step may follow the bonding of two semiconductor wafers together. The optional thinning step reduces the thickness of the top semiconductor layer to a layer having a thickness that is more desirable. - The thickness of the
top semiconductor layer 56 of theSOI substrate 50 is from about 100 to about 1000 Å, with a thickness from about 500 to about 700 Å being more highly preferred. If the thickness of thetop semiconductor layer 56 is not within the above mentioned range, a thinning step such as, for example, planarization or etching may be used to reduce the thickness of thetop semiconductor layer 56 to a value within the range mentioned above. The thinning step is performed prior to forming thehard mask 58 on a surface oftop semiconductor layer 56. - The buried insulating
layer 54 of theSOI substrate 50 has a thickness from about 10 to about 2000 Å, with a thickness from about 1000 to about 1500 Å being more highly preferred. The thickness of thebottom semiconductor layer 52 of theSOI substrate 50 is inconsequential to the present invention. - The
hard mask 58 is then formed on a surface of thetop semiconductor layer 56 of theSOI substrate 50 utilizing a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation or other like deposition processes. Alternatively, thehard mask 58 may be formed by a thermal process such as, for example, oxidation or nitridation. Any combination of the above mentioned processes can also be used in forming thehard mask 58. - The
hard mask 58 comprises an oxide, nitride, oxynitride or any combination thereof including multilayers. In one embodiment of the present invention, thehard mask 58 is an oxide including, for example, silicon oxide or silicon nitride. The thickness of thehard mask 58 may vary depending on the technique used in forming the same, the material of the hard mask itself, and the number of layers within the hard mask layer. Typically, thehard mask 58 has a thickness from about 200 to about 800 Å, with a thickness from about 400 to about 600 Å being more typical. It is noted that thehard mask 58 is utilized in the present invention during a subsequent etching of thetop semiconductor layer 56 to define the active regions as well as to protect the subsequently formed FIN during a gate etch and also during a spacer etch. -
FIGS. 5A-5C shows the structure ofFIG. 4 after formation of a plurality of parallel orientedsemiconducting bodies 60. It is noted that each of the parallel orientedsemiconducting bodies 60 thus formed have a narrow width on the order of about 20 nm or less and, a vertical thickness that is within the range provided above as such, they are referred hereinafter as FINs. - Each of the parallel oriented
FINs 60 shown inFIGS. 5A-5C is formed by lithography and etching. The lithographic step includes applying a photoresist (not shown) atop thehard mask 58, exposing the photoresist to a desired pattern of radiation, and developing the exposed resist utilizing a conventional resist developer. The etching process comprises drying etching and/or wet chemical etching. Illustrative examples of suitable dry etching processes that can be used in the present invention include reactive ion etching, ion beam etching, plasma etching or laser ablation. Typically, a reactive ion etching process or an ion beam etching process is used. The etching process first transfers the pattern from the patterned photoresist to thehard mask 58 and thereafter to the underlyingtop semiconductor layer 56. The patterned photoresist is typically, but not necessarily always, removed after the pattern has been transferred to thehard mask 58. A conventional resist stripping process is used to remove the patterned photoresist from the structure. - In some embodiments of the present invention, a
trench opening 62 is formed into an exposed portion of the buried insulatinglayer 54 that extends down into thesemiconductor substrate 52 prior to forming theFINS 60. Thetrench opening 62 is formed by lithography and etching and is used for alignment purposes. Thetrench opening 62 is typically lined with adielectric material 65 such as an oxide. Thedielectric material 65 is formed by conventional techniques well known to those skilled in the art. The structure including thetrench opening 62 anddielectric material 65 is also shown inFIG. 5B . It is noted that the use of thistrench opening 62 is optional - At this point of the present invention (See,
FIGS. 5B-5C as well), asacrificial oxide 64 is formed that lines the exposed sidewalls of each of the parallel orientedFINs 60. Thesacrificial oxide 64 is formed by a deposition process such as, for example, CVD, PECVD, ALD, evaporation or chemical solution deposition. Alternatively, a thermal oxidation process can be used to formsacrificial oxide 64. Thesacrificial oxide 64 is removed from the sidewalls of eachFIN 60 prior to forming the gate stack utilizing a conventional stripping process. - In some embodiments of the present invention (not shown herein), the
hard mask 58 can be removed atop each of theFINs 60 at this point of the present invention. This particular embodiment allows for the fabrication of a tri-gated device since the gate dielectric to be subsequently formed would be present on the sides and the top of each of theFINs 60. - Next, a
gate stack 66 is formed over the entire structure. The resultant structure including thegate stack 66 is shown, for example, inFIG. 6 . It is noted thatFIG. 6 is a view through line A-A′ which runs perpendicular to theFINs 60. - The
gate stack 66 comprises agate dielectric 67 and agate electrode 69. Thegate dielectric 67 can be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. Alternatively, thegate dielectric 67 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes. Thegate dielectric 67 may also be formed utilizing any combination of the above processes. - The
gate dielectric 67 is comprised of an insulating material having a dielectric constant of about 4.0 or greater. All dielectric constants mentioned herein are relative to a vacuum unless otherwise noted. In one embodiment, thegate dielectric 67 comprises a high k material. The term “high k” denotes a dielectric having a dielectric constant of greater than 4.0, preferably greater than 7.0. Specifically, thegate dielectric 67 employed in the present invention includes, but is not limited to: an oxide, nitride, oxynitride and/or silicate including metal silicates and nitrided metal silicates. In one embodiment, it is preferred that thegate dielectric 67 is comprised of an oxide such as, for example, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, Ga2O3, GdGaO and mixtures thereof. Highly preferred examples of gate dielectrics include HfO2, hafnium silicate and hafnium silicon oxynitride. The physical thickness of thegate dielectric 67 may vary, but typically, thegate dielectric 67 has a thickness from about 0.5 to about 10 nm, with a thickness from about 0.5 to about 3 nm being more typical. - Next, a
gate electrode 69 is formed. Thegate electrode 69 is comprised of a conductive material, including, for example, polySi, SiGe, a metal, a metal alloy, a metal silicide, a metal nitride, a metal carbide or combinations including multilayers thereof. When multilayers are present, a diffusion barrier (not shown), such as TiN or TaN, can be positioned between each of the conductive layers. - The
gate electrode 69 is formed utilizing a conventional deposition process including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, sputtering, plating, evaporation and any other like deposition processes. In embodiments in which poly Si or SiGe are used as thegate electrode 69, an in-situ deposition process can be used or alternatively deposition followed by ion implantation can be used. The thickness of thegate electrode 69 is not critically to the present invention. Typically, however, the thickness of thegate electrode 69 is from about 50 to about 200 nm. -
FIGS. 7A-7C show the structure ofFIG. 6 after planarization which removes a portion of thegate electrode 69. The planarization process is performed utilizing a conventional planarization process such as, for example, chemical mechanical polishing (CMP) and/or grinding. - Next, the
gate electrode 69 is patterned by lithography and etching providing the structure shown, for example, inFIGS. 8A-8C . In these drawings, the patterned gate electrode, which is common to each of the parallel orientedFINs 60, is denoted byreference numeral 69′. It is noted that the common patternedgate electrode 69′ is oriented perpendicular to each of the parallel orientedFINs 60. The lithographic and etching processes employed in patterning thegate electrode 69 are the same as those mentioned above for patterning theFINs 60. After formation of the common patternedgate electrode 69′, an insulating layer 68 (including an oxide, nitride, or multilayers thereof) is formed on all exposed surfaces of the patternedgate electrode 69′. The structure including the insulatinglayer 68 is also shown inFIGS. 8B-8C . The insulatinglayer 68 is formed utilizing a conventional deposition process or by a conventional thermal growth method. -
FIGS. 9A-9C show the structure ofFIGS. 8A-8C after forming a nitride-containingspacer 70 on exposed sidewalls of the common patternedgate electrode 69′ which includes the insulatinglayer 68. The nitride-containingspacer 70 is formed only in regions in which a FIN and a corresponding patterned gate conductor intercross. The nitride-containingspacer 70 is formed by deposition and etching. Typically, an aggressive over etch using a reactive ion process is employed in forming the nitride-containingspacer 70. -
FIGS. 10A-10C shows the structure after partial growth of anepitaxial semiconductor layer 72. The partial growth is performed utilizing a selective epitaxial growth process. It is noted that at this point of the present invention the FINs are not merged. This is evidence by the space that is still shown to be present between each of the parallel orientedFINs 60. The epitaxially grown semiconductor material typically comprises a Si-containing semiconductor material such as, for example, Si or SiGe. The lateral thickness of the partially grownepitaxial semiconductor layer 72 is typically from about 20 to about 50 nm. The partially grownepitaxial semiconductor layer 72 has a thickness that is generally associated with conventional raised source/drain regions of prior art FINFET structures. - It is noted that at this point of the present application source/drain implantations may be performed to form source/drain regions (not specifically shown or labeled) within the partially grown
epitaxial semiconductor layer 72. -
FIGS. 11A-11C show the structure after full growth of anepitaxial semiconductor layer 72′. The fully grownepitaxial semiconductor layer 72′ merges each of the parallel orientedFINs 60. The lateral thickness of the fully grownepitaxial semiconductor layer 72′ varies and is dependent on the number of FINs within a given structure. It is noted that the thickness of the fully grownepitaxial semiconductor layer 72′ must merge (i.e., cover) each of the FINs present in the structure. -
FIGS. 12A-12C shows the structure aftercontact 74 formation. Thecontacts 74 are formed utilizing standard techniques that are well known to those skilled in the art. For example, contact openings are first formed into exposed portions of the fully grownepitaxial semiconductor layer 72′ utilizing lithography and etching. After etching and removal of the resist material, a contact metal such as, for example, Cu, Al, W, or AlCu is formed within the contactopenings forming contacts 74. - Reference is now made to the various SEMs shown in
FIGS. 13-16 . Specifically,FIG. 13 is a scanning electron micrograph (SEM) of a conventional FINFET with multiple FINS at a 120 nm pitch obtained using e-beam lithography. In this SEM, all of the parallel oriented FINs are connected at the end using a large source/drain contact pad. -
FIG. 14 is a SEM of the inventive FINFET structure where all the individual parallel oriented FINs are printed without source/drain contacts and prior to epitaxy.FIG. 15 is a SEM of the FINFET structure ofFIG. 14 after selective raised source/drain formation of a 25 nm epi Si (i.e., formation of the partially epitaxial semiconductor layer).FIG. 16 is a SEM of a FINFET structure ofFIG. 14 after merging the individual parallel oriented FINs together using a 50 nm selective epi Si layer (i.e., fully grown epitaxially semiconductor layer). In accordance with the present invention, the merging of the FINs reduces the series resistance. It is noted that after the FINs have been merged, the FINFET devices look exactly the same planar FETs, thus the standard middle of the liner processing can be applied to the FINFET devices of the present invention. - While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/448,702 US20070287256A1 (en) | 2006-06-07 | 2006-06-07 | Contact scheme for FINFET structures with multiple FINs |
US12/434,233 US8080838B2 (en) | 2006-06-07 | 2009-05-01 | Contact scheme for FINFET structures with multiple FINs |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/448,702 US20070287256A1 (en) | 2006-06-07 | 2006-06-07 | Contact scheme for FINFET structures with multiple FINs |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/434,233 Division US8080838B2 (en) | 2006-06-07 | 2009-05-01 | Contact scheme for FINFET structures with multiple FINs |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070287256A1 true US20070287256A1 (en) | 2007-12-13 |
Family
ID=38822479
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/448,702 Abandoned US20070287256A1 (en) | 2006-06-07 | 2006-06-07 | Contact scheme for FINFET structures with multiple FINs |
US12/434,233 Active 2027-01-26 US8080838B2 (en) | 2006-06-07 | 2009-05-01 | Contact scheme for FINFET structures with multiple FINs |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/434,233 Active 2027-01-26 US8080838B2 (en) | 2006-06-07 | 2009-05-01 | Contact scheme for FINFET structures with multiple FINs |
Country Status (1)
Country | Link |
---|---|
US (2) | US20070287256A1 (en) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060073647A1 (en) * | 2004-09-30 | 2006-04-06 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US7692222B2 (en) * | 2006-11-07 | 2010-04-06 | Raytheon Company | Atomic layer deposition in the formation of gate structures for III-V semiconductor |
US20100248441A1 (en) * | 2006-06-29 | 2010-09-30 | International Business Machines Corporation | Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices |
US20110193163A1 (en) * | 2010-02-09 | 2011-08-11 | International Business Machines Corporation | Semiconductor Devices with Improved Self-Aligned Contact Areas |
US8378394B2 (en) | 2010-09-07 | 2013-02-19 | International Business Machines Corporation | Method for forming and structure of a recessed source/drain strap for a MUGFET |
US8377759B2 (en) | 2010-08-17 | 2013-02-19 | International Business Machines Corporation | Controlled fin-merging for fin type FET devices |
US8652932B2 (en) | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US20140145248A1 (en) * | 2012-11-26 | 2014-05-29 | International Business Machines Corporation | Dummy fin formation by gas cluster ion beam |
US20140295584A1 (en) * | 2013-03-27 | 2014-10-02 | International Business Machines Corporation | Low energy collimated ion milling of semiconductor structures |
US20150279935A1 (en) * | 2014-04-01 | 2015-10-01 | Globalfoundries Inc. | Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material |
US9171952B2 (en) | 2013-05-30 | 2015-10-27 | Globalfoundries U.S. 2 Llc | Low gate-to-drain capacitance fully merged finFET |
US20150340489A1 (en) * | 2014-05-26 | 2015-11-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Fin tunneling field effect transistor and manufacturing method thereof |
US9257427B2 (en) | 2013-07-15 | 2016-02-09 | Globalfoundries Inc. | Merged tapered finFET |
US9279849B2 (en) | 2013-12-09 | 2016-03-08 | International Business Machines Corporation | Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices |
US9312273B2 (en) | 2013-12-02 | 2016-04-12 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US9496282B2 (en) | 2013-12-02 | 2016-11-15 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US9570555B1 (en) | 2015-10-29 | 2017-02-14 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
US9905662B2 (en) | 2013-05-31 | 2018-02-27 | Stmicroelectronics, Inc. | Method of making a semiconductor device using a dummy gate |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7422946B2 (en) * | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
WO2011067821A1 (en) * | 2009-12-04 | 2011-06-09 | 株式会社 東芝 | Method for manufacturing semiconductor device |
US8174055B2 (en) * | 2010-02-17 | 2012-05-08 | Globalfoundries Inc. | Formation of FinFET gate spacer |
US8445334B1 (en) * | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
US8871626B2 (en) | 2011-12-20 | 2014-10-28 | International Business Machines Corporation | FinFET with vertical silicide structure |
US8592263B2 (en) * | 2012-04-26 | 2013-11-26 | International Business Machines Corporation | FinFET diode with increased junction area |
US8604546B1 (en) | 2012-07-09 | 2013-12-10 | International Business Machines Corporation | Reducing gate resistance in nonplanar multi-gate transistor |
US8946033B2 (en) | 2012-07-30 | 2015-02-03 | International Business Machines Corporation | Merged fin finFET with (100) sidewall surfaces and method of making same |
US8815656B2 (en) | 2012-09-19 | 2014-08-26 | International Business Machines Corporation | Semiconductor device and method with greater epitaxial growth on 110 crystal plane |
US9000489B2 (en) | 2012-10-31 | 2015-04-07 | International Business Machines Corporation | Local interconnects for field effect transistor devices |
US20140239395A1 (en) * | 2013-02-25 | 2014-08-28 | International Business Machines Corporation | Contact resistance reduction in finfets |
US9257536B2 (en) | 2013-04-22 | 2016-02-09 | Globalfoundries Inc. | FinFET with crystalline insulator |
US8993406B1 (en) | 2013-09-10 | 2015-03-31 | International Business Machines Corporation | FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same |
US9048262B2 (en) | 2013-09-20 | 2015-06-02 | International Business Machines Corporation | Multi-fin finFETs with merged-fin source/drains and replacement gates |
US9698222B2 (en) * | 2013-12-23 | 2017-07-04 | Intel Corporation | Method of fabricating semiconductor structures on dissimilar substrates |
US10204989B2 (en) | 2013-12-23 | 2019-02-12 | Intel Corporation | Method of fabricating semiconductor structures on dissimilar substrates |
US9564506B2 (en) | 2015-01-06 | 2017-02-07 | International Business Machines Corporation | Low end parasitic capacitance FinFET |
US9793271B1 (en) | 2016-04-29 | 2017-10-17 | International Business Machines Corporation | Semiconductor device with different fin pitches |
KR102291559B1 (en) | 2017-06-09 | 2021-08-18 | 삼성전자주식회사 | semiconductor device |
KR102343202B1 (en) | 2017-06-20 | 2021-12-23 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US11171237B2 (en) | 2019-04-17 | 2021-11-09 | Globalfoundries U.S. Inc. | Middle of line gate structures |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050202618A1 (en) * | 2004-03-10 | 2005-09-15 | Atsushi Yagishita | Semiconductor device and manufacturing method of the same |
US20050242395A1 (en) * | 2004-04-30 | 2005-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET transistor device on SOI and method of fabrication |
US20070026629A1 (en) * | 2005-07-29 | 2007-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel structure for a multiple-gate FET device and a method for its fabrication |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100541657B1 (en) * | 2004-06-29 | 2006-01-11 | 삼성전자주식회사 | Multi-gate transistor fabrication method and multi-gate transistor fabricated thereby |
JP2006013303A (en) * | 2004-06-29 | 2006-01-12 | Toshiba Corp | Semiconductor device and its manufacturing method |
US7968394B2 (en) * | 2005-12-16 | 2011-06-28 | Freescale Semiconductor, Inc. | Transistor with immersed contacts and methods of forming thereof |
-
2006
- 2006-06-07 US US11/448,702 patent/US20070287256A1/en not_active Abandoned
-
2009
- 2009-05-01 US US12/434,233 patent/US8080838B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050202618A1 (en) * | 2004-03-10 | 2005-09-15 | Atsushi Yagishita | Semiconductor device and manufacturing method of the same |
US20050242395A1 (en) * | 2004-04-30 | 2005-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET transistor device on SOI and method of fabrication |
US20070026629A1 (en) * | 2005-07-29 | 2007-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel structure for a multiple-gate FET device and a method for its fabrication |
Cited By (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060073647A1 (en) * | 2004-09-30 | 2006-04-06 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US7456472B2 (en) | 2004-09-30 | 2008-11-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US20100248441A1 (en) * | 2006-06-29 | 2010-09-30 | International Business Machines Corporation | Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices |
US8114723B2 (en) * | 2006-06-29 | 2012-02-14 | International Business Machines Corporation | Method of forming multi-high-density memory devices and architectures |
US7692222B2 (en) * | 2006-11-07 | 2010-04-06 | Raytheon Company | Atomic layer deposition in the formation of gate structures for III-V semiconductor |
US20110193163A1 (en) * | 2010-02-09 | 2011-08-11 | International Business Machines Corporation | Semiconductor Devices with Improved Self-Aligned Contact Areas |
US8242561B2 (en) | 2010-02-09 | 2012-08-14 | International Business Machines Corporation | Semiconductor devices with improved self-aligned contact areas |
US8377759B2 (en) | 2010-08-17 | 2013-02-19 | International Business Machines Corporation | Controlled fin-merging for fin type FET devices |
US8564064B2 (en) | 2010-08-17 | 2013-10-22 | International Business Machines Corporation | Controlled fin-merging for fin type FET devices |
US8623719B2 (en) | 2010-09-07 | 2014-01-07 | International Business Machines Corporation | Method for forming and structure of a recessed source/drain strap for a MUGFET |
US8378394B2 (en) | 2010-09-07 | 2013-02-19 | International Business Machines Corporation | Method for forming and structure of a recessed source/drain strap for a MUGFET |
US9219139B2 (en) | 2012-04-17 | 2015-12-22 | Globalfoundries Inc. | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US8652932B2 (en) | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US20140145248A1 (en) * | 2012-11-26 | 2014-05-29 | International Business Machines Corporation | Dummy fin formation by gas cluster ion beam |
US8946792B2 (en) * | 2012-11-26 | 2015-02-03 | International Business Machines Corporation | Dummy fin formation by gas cluster ion beam |
US9269629B2 (en) | 2012-11-26 | 2016-02-23 | Globalfoundries Inc. | Dummy fin formation by gas cluster ion beam |
US20140295584A1 (en) * | 2013-03-27 | 2014-10-02 | International Business Machines Corporation | Low energy collimated ion milling of semiconductor structures |
US9171952B2 (en) | 2013-05-30 | 2015-10-27 | Globalfoundries U.S. 2 Llc | Low gate-to-drain capacitance fully merged finFET |
US9905662B2 (en) | 2013-05-31 | 2018-02-27 | Stmicroelectronics, Inc. | Method of making a semiconductor device using a dummy gate |
US9991351B2 (en) | 2013-05-31 | 2018-06-05 | Stmicroelectronics, Inc. | Method of making a semiconductor device using a dummy gate |
US9257427B2 (en) | 2013-07-15 | 2016-02-09 | Globalfoundries Inc. | Merged tapered finFET |
US9312273B2 (en) | 2013-12-02 | 2016-04-12 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US9472576B2 (en) | 2013-12-02 | 2016-10-18 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US9496282B2 (en) | 2013-12-02 | 2016-11-15 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US9279849B2 (en) | 2013-12-09 | 2016-03-08 | International Business Machines Corporation | Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices |
US20150279935A1 (en) * | 2014-04-01 | 2015-10-01 | Globalfoundries Inc. | Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material |
US9299781B2 (en) * | 2014-04-01 | 2016-03-29 | Globalfoundries Inc. | Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material |
US10615081B2 (en) * | 2014-05-26 | 2020-04-07 | Semiconductor Manufacturing International (Shanghai) Corporation | Fin tunneling field effect transistor and manufacturing method thereof |
US20150340489A1 (en) * | 2014-05-26 | 2015-11-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Fin tunneling field effect transistor and manufacturing method thereof |
US9570555B1 (en) | 2015-10-29 | 2017-02-14 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
US10236212B2 (en) | 2015-10-29 | 2019-03-19 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
US10304741B2 (en) | 2015-10-29 | 2019-05-28 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
US10340189B2 (en) | 2015-10-29 | 2019-07-02 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
US10090202B2 (en) | 2015-10-29 | 2018-10-02 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US8080838B2 (en) | 2011-12-20 |
US20090212366A1 (en) | 2009-08-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8080838B2 (en) | Contact scheme for FINFET structures with multiple FINs | |
US8614485B2 (en) | Process for fabrication of FINFETs | |
US7034362B2 (en) | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures | |
US7309626B2 (en) | Quasi self-aligned source/drain FinFET process | |
EP1593150B1 (en) | Tri-gate and gate around mosfet devices and methods for making same | |
US10872965B2 (en) | Method of forming semiconductor structure | |
JP5305969B2 (en) | Semiconductor device | |
KR20220133165A (en) | Ferroelectric random access memory devices and methods | |
US7932141B2 (en) | Semiconductor device and method for fabricating the same | |
US11177361B2 (en) | FinFET and gate-all-around FET with selective high-k oxide deposition | |
US10777468B1 (en) | Stacked vertical field-effect transistors with sacrificial layer patterning | |
US11532723B2 (en) | Fin-end gate structures and method forming same | |
US20230299159A1 (en) | Semiconductor Devices and Methods | |
US9911601B2 (en) | Epitaxial silicon germanium fin formation using sacrificial silicon fin templates | |
US20190252267A1 (en) | Vertical field effect transistor with self-aligned contacts | |
US20220359722A1 (en) | Fin-End Gate Structures and Method Forming Same | |
US20240014265A1 (en) | Gate Isolation Wall for Semiconductor Device | |
US20230361114A1 (en) | Semiconductor structure and methods of forming the same | |
US12080588B2 (en) | Buried metal for FinFET device and method | |
US20230135392A1 (en) | Isolation structures for semiconductor devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINS CORPORATION, NEW YO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, LELAND;HAENSCH, WILFRIED E.;IEONG, MEIKEI;AND OTHERS;REEL/FRAME:018076/0101;SIGNING DATES FROM 20060606 TO 20060607 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: AURIGA INNOVATIONS, INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:041804/0940 Effective date: 20161207 |