JP6135709B2 - トレンチゲート型半導体装置の製造方法 - Google Patents
トレンチゲート型半導体装置の製造方法 Download PDFInfo
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- JP6135709B2 JP6135709B2 JP2015100210A JP2015100210A JP6135709B2 JP 6135709 B2 JP6135709 B2 JP 6135709B2 JP 2015100210 A JP2015100210 A JP 2015100210A JP 2015100210 A JP2015100210 A JP 2015100210A JP 6135709 B2 JP6135709 B2 JP 6135709B2
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Classifications
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Description
製造方法とする ことにより、前記第3の課題を解決することができる。
は成膜によりSiO2膜が張り出してきてしまうため、2μmで塞がる寸前となり、2.5μm堆積すると完全に塞がる。この張り出しがあるため最初のSiO2膜パターニングは80°の角度にテーパーをつけておく必要がある。垂直だとパターンエッジの塞がりが更に薄い膜厚で起こってしまい充分パターン幅が狭くできなくなるためである。2度目のSiO2膜の堆積後、堆積した膜厚分を2度目のドライエッチングを行い、パターン底部分に堆積したSiO2膜をSiC表面が完全に露出するまで除去する。エッチング条件はCHF3/Ar=1:1混合ガスを用いて、3Paの圧力でRFパワー75Wの条件でエッチングする。図45に2度目のSiO2膜エッチング後の断面図を示す。パターン底に堆積しているSiO2膜がエッチングされて狭い幅のSiO2膜パターンが形成できる。最初の図43の状態ではSiO2膜パターン幅は1.9μmあったが、図45のSiO2膜再堆積と再エッチングの工程を行うとパターン幅は0.4μmまで狭めることができる。
した断面図を図47に示す。図46の従来のマスク幅ではSiCウエハのエッチング断面形状はトレンチ深さ3.2μmでトレンチ幅は2.3μmであるが、図47の実施例6の方法を用いた場合は、トレンチ深さ3.2μmでトレンチ幅は0.9μmまで狭めることができる。
られる。しかし、前述の実施例1〜7で説明したゲートトレンチの構成では、ゲートトレンチの内部間隔がたとえば2μm程度しかないので、数百nmといった厚いSiO2をゲートトレンチ内面に設けると、ゲート電極とショットキー電極自体の厚さが極端に薄くなる。この場合、ゲート電極の内部抵抗を増大させるので、好ましくない。
2 フィールドストッピング層
3 耐圧層
5 ボディー領域、ボディー層
5a、5b ボディー層
6 ソース領域
6−1 ソースイオン注入領域
6a ソースコンタクト領域
6a−1 ソースコンタクトイオン注入領域
6b ソース拡張領域
6b−1 ソース拡張イオン注入領域
6c ソース延長領域
6c−1 ソース延長イオン注入領域
7 ボディーコンタクト領域
7−1 ボディーコンタクト層
10 トレンチ
10a 第一トレンチ
10b 第三トレンチ
10c 第二トレンチ
10p 交差トレンチ
11 ゲート絶縁膜
12 ゲート電極
15 埋め込み絶縁物
20 コンタクトホール
21 層間絶縁膜
22 ドレイン電極
23 ソース電極
24 ショットキー電極
101 マスク酸化膜
106a、110p 第1マスク
106b、110、110c 第2マスク
106c 第3マスク
110q エッチストップ膜
111p 交差トレンチ保護物。
Claims (2)
- 高不純物濃度のワイドバンドギャップ半導体基板の上に、第1導電型のワイドバンドギャップ半導体の耐圧層と第2導電型のワイドバンドギャップ半導体のボディー層と高不純物濃度表面を有する第2導電型のワイドバンドギャップ半導体のボディーコンタクト層とをこの順にそれぞれ全面エピタキシャル成長により積層する第一工程と、前記ボディーコンタクト層の表面に、第1開口部を有する第1マスクを形成する第二工程と、前記第1開口部から異方性エッチングにより前記ボディーコンタクト層を貫通して前記ボディー層中に底部を有する第一トレンチを形成する第三a工程と、該第一トレンチ底部にイオン注入もしくはエピタキシャル成長により、少なくとも前記ボディーコンタクト層より深い位置に第1導電型のソースイオン注入領域を形成する第三b工程と、第三b工程後の半導体基板の全面に前記第一トレンチの幅の二分の一未満の厚さを有する第2マスクを堆積し、異方性エッチングにより前記第一トレンチの底部の前記第2マスクに第2開口部を設ける第四工程と、該第2開口部から異方性エッチングにより前記耐圧層に達する第二トレンチを形成する第五工程と、該第二トレンチの内壁面に絶縁膜を形成し、該絶縁膜を介して前記ソースイオン注入領域と前記ボディー領域と前記耐圧層とにそれぞれ対向する位置までゲート電極を埋め込む第六工程とを含むことを特徴とするトレンチゲート型半導体装置の製造方法。
- 前記第三b工程が、前記第一トレンチ底部にイオン注入もしくはエピタキシャル成長により、少なくとも前記ボディーコンタクト層より深い位置に、オーミック接触が得られる高不純物濃度表面を有する表面側の第1導電型のソースコンタクトイオン注入領域と下層側の第1導電型のソース拡張イオン注入領域とを形成する工程に置き換え、前記第六工程が、前記第二トレンチの内壁面に絶縁膜を形成し、該絶縁膜を介して前記ソース拡張イオン注入領域と前記ボディー領域と前記耐圧層とにそれぞれ対向する位置までゲート電極を埋め込む工程に置き換えることを特徴とする請求項1記載のトレンチゲート型半導体装置の製造方法。
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