JP2000505241A - 基板上の半導体膜領域の結晶化処理及びこの方法により製造されたデバイス - Google Patents
基板上の半導体膜領域の結晶化処理及びこの方法により製造されたデバイスInfo
- Publication number
- JP2000505241A JP2000505241A JP09542270A JP54227097A JP2000505241A JP 2000505241 A JP2000505241 A JP 2000505241A JP 09542270 A JP09542270 A JP 09542270A JP 54227097 A JP54227097 A JP 54227097A JP 2000505241 A JP2000505241 A JP 2000505241A
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- semiconductor
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Links
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Classifications
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
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- C30B13/00—Single-crystal growth by zone-melting; Refining by zone-melting
- C30B13/16—Heating of the molten zone
- C30B13/22—Heating of the molten zone by irradiation or electric discharge
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
- Y10S117/903—Dendrite or web or cage technique
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Electromagnetism (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.支持された半導体材料の膜の横方向に延在する部分として多結晶領域を形成 するに当たり、 半導体材料中に熱を誘導するパルス状の放射を用いて、後側に位置する放射 透過性の基板と、基板上の第1の半導体膜と、第1の半導体膜上の耐熱性の膜 と、耐熱性の膜上の第2の半導体膜とを具える構造体の前側及び後側から同時に 露光し、前記横方向に延在する部分を含む半導体膜の横方向に延在する領域の全 ての半導体材料を溶融し、 同時露光の後、前記領域の境界から横方向に凝固させることにより、多結晶 の微細構造体を前記領域に形成する多結晶領域の形成方法。 2.請求項1に記載の方法において、前記領域が平行な縁部により範囲が規定さ れている方法。 3.請求項2に記載の方法において、前記平行な縁部が、同時に生ずる横方向か らの凝固により前記領域の全体が結晶化する距離だけ離間している方法。 4.請求項1に記載の方法において、前記半導体材料がシリコンで構成される方 法。 5.請求項1に記載の方法において、前記耐熱層がほぼSiO2で構成されてい る方法。 6.請求項1に記載の本発明において、前記基板をガラス基板とした方法。 7.請求項1に記載の本発明において、前記基板を水晶基板とした方法。 8.請求項1に記載の方法において、前記横方向に延在する部分が前記第1の半 導体膜にある方法。 9.請求項1に記載の方法において、前記横方向に延在する部分が前記第2の半 導体膜にある方法。 10.請求項1に記載の方法において、前記領域がマスクパターンにより規定され た形状を有する方法。 11.請求項10に記載の方法において、前記マスクパターンが投影される方法。 12.請求項10に記載の方法において、前記マスクパターンが近接マスクにより 規定される方法。 13.請求項10に記載の方法において、前記マスクパターンが接触マスクにより 規定される方法。 14.請求項1に記載の方法において、前記放射がレーザ放射により構成される方 法。 15.請求項1に記載の方法において、前記領域がカプセル化されている方法。 16.支持基板上の請求項1に記載の方法により処理された半導体膜。 17.支持基板上の、請求項1に記載の方法により処理された半導体膜で構成され る複数の半導体デバイス。 18.支持基板上の、少なくともアクティブチャネル領域が請求項1に記載の方法 により処理されている薄膜トランジスタを有する集積回路。 19.少なくともアクティブチャネル領域が請求項1に記載の方法により処理され ている複数の画素コントローラ薄膜トランジスタを具える液晶表示装置。 20.少なくともアクティブチャネル領域が請求項1に記載の方法により処理され ている複数の薄膜トランジスタを具える画素ドライバ集積回路を有する液晶表 示装置。 21.基板上の半導体材料の膜に横方向に延在する結晶領域を形成するに当たり、 半導体材料中に熱を誘導するパルス状の放射を用い、前記半導体膜の一部部 分を露光して前記半導体膜の部分の半導体材料を全体とし.て溶融させ、 当該部分の溶融した半導体材料を凝固させ、 前記部分を、第1のサブ部分と、この第1のサブ部分と連続する第2のサブ 部分と、第2のサブ部分と連続する第3のサブ部分とを含むような形態とし、 前記第1のサブ部分が、その境界部で半導体結晶に凝固する形態を有し、 前記第2の部分が、1個の凝固した結晶が前記第1のザブ部分から第2のサ ブ部分を経て第3のサブ部分に成長する形態を有し、 前記第3のサブ部分が、1個の結晶が全体として前記第3のサブ部分を占め る形態を有する結晶領域の形成方法。 22.請求項21に記載の方法において、前記第1のサブ部分が、複数の半導体結 晶に凝固するアイランド部分の形態を有する方法。 23.請求項21に記載の方法において、前記第2のサブ部分の形態が、前記第1 のサブ部分と第3のサブ部分との間の直線状の経路を構成する方法。 24.請求項21に記載の方法において、前記半導体材料がシリコンで構成される 方法。 25.請求項21に記載の方法において、前記基板が加熱される方法。 26.請求項21に記載の方法において、前記基板をガラス基板とした方法。 27.請求項21に記載の方法において、前記基板を水晶基板とした方法。 28.請求項21に記載の方法において、前記パルス状の放射を前記半導体膜の後 側及び前側に投射する方法。 29.請求項21に記載の方法において、前記半導体膜が、100nmを超えない 厚さを有する方法。 30.請求項22に記載の方法において、前記アイランド部分がマスクパターンに より規定される形状を有する方法。 31.請求項30に記載の方法において、前記マスクパターンが投影される方法。 32.請求項30に記載の方法において、前記マスクパターンが近接マスクにより 規定される方法。 33.請求項30に記載の方法において、前記マスクパターンが接触マスクにより 規定される方法。 34.請求項21に記載の方法において、前記放射がレーザ放射により構成される 方法。 35.請求項21に記載の方法において、前記領域がカプセル化されている方法。 36.支持基板上の、請求項21に記載の方法により処理された半導体膜。 37.支持基板上の、請求項21に記載の方法により処理された半導体膜で構成さ れる含むの半導体デバイス。 38.支持基板上の、少なくともアクティブチャネル領域が請求項21に記載の方 法により処理されている薄膜トランジスタを有する集積回路。 39.少なくともアクティブチャネル領域が請求項21に記載の方法により処理さ れている複数の画素コントローラ薄膜トランジスタを具える液晶表示装置。 40.少なくともアクティブチャネル領域が請求項21に記載の方法により処理さ れている複数の薄膜トランジスタを具える画素ドライバ集積回路を有する液晶表 示装置。 41.基板上の半導体材料の膜に横方向に延在する結晶領域を形成するに当たり、 (a)半導体材料中に熱を誘導するパルス状の放射を用い、前記膜の第1の部 分を露光してその厚さにわたって第1の部分の半導体材料を溶融し、 (b)前記第1の部分の半導体を凝固させ、前記第1の部分の境界部分に少な くとも1個の半導体結晶を形成し、この第1の部分を次のの処理に対する以前 の部分とし、 (c)前記以前の部分からステップ移動方向にステップ移動すると共に少なく とも1個の半導体結晶と部分的に重なり合う半導体の別の部分を露光し、 (d)前記別の部分の溶融した半導体材料を凝固させ、半導体結晶をステップ 移動方向に成長させることにより半導体結晶を拡大させ、 (e)工程(c)と(d)の組合せを繰り返し、所望の結晶領域が形成される まで、各工程の別の部分を次の工程の対して以前の部分とする方法。 42.請求項41に記載の方法において、前記露光される部分を細条とした方法。 43.請求項42に記載の方法において、前記細条が縁部間の幅を有し、縁部から の横方向の同時凝固により前記細条全体が凝固しない方法。 44.請求項41に記載の方法において、前記半導体材料をシリコンで構成した方 法。 45.請求項41に記載の方法において、前記露光される部分を山形とした方法。 46.請求項41に記載の方法において、前記基板をガラス基板とした方法。 47.請求項41に記載の方法において、前記基板を水晶基板とした方法。 48.請求項41に記載の方法において、前記横方向に延在する結晶領域が、半導 体材料の膜をパターニングすることにより規定される方法。 49.請求項48に記載の方法において、前記膜のパターンが、テイル部分と、こ のテイル部分に連続するボトルネック部分と、このボトルネック部分と連続す る主アイランド部分とを有する方法。 50.請求項41に記載の方法において、前記露光される部分がマスクパターンに より規定される方法。 51.請求項50に記載の方法において、前記マスクパターンが投影される方法。 52.請求項50に記載の方法において、前記マスクパターンが近接マスクにより 規定される方法。 53.請求項50に記載の方法において、前記マスクパターンが接触マスクにより 規定される方法。 54.請求項41に記載の方法において、前記放射がレーザ放射により構成される 方法。 55.請求項41に記載の方法において、前記領域がカプセル化されている方法。 56.支持基板上の、請求項41に記載の方法により処理された半導体膜。 57.支持基板上の、請求項41に記載の方法により処理された半導体膜で構成さ れる複数の半導体デバイス。 58.支持基板上の、少なくともアクティブチャネル領域が請求項41に記載の方 法により処理されている薄膜トランジスタを有する集積回路。 59.少なくともアクティブチャネル領域が請求項41に記載の方法により処理さ れている複数の画素コントローラ薄膜トランジスタを具える液晶表示装置。 60.少なくともアクティブチャネル領域が請求項41に記載の方法により処理さ れている複数の薄膜トランジスタを具える画素ドライバ集積回路を有する液晶表 示装置。
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Also Published As
Publication number | Publication date |
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CA2256699A1 (en) | 1997-12-04 |
JP3204986B2 (ja) | 2001-09-04 |
US6322625B2 (en) | 2001-11-27 |
WO1997045827A1 (en) | 1997-12-04 |
US20010001745A1 (en) | 2001-05-24 |
CA2256699C (en) | 2003-02-25 |
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