JPWO2007055270A1 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JPWO2007055270A1 JPWO2007055270A1 JP2007544174A JP2007544174A JPWO2007055270A1 JP WO2007055270 A1 JPWO2007055270 A1 JP WO2007055270A1 JP 2007544174 A JP2007544174 A JP 2007544174A JP 2007544174 A JP2007544174 A JP 2007544174A JP WO2007055270 A1 JPWO2007055270 A1 JP WO2007055270A1
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Abstract
Description
本実施の形態1の半導体装置の製造方法を図1のフロー図に沿って説明する。
本実施の形態2では、チップ1C内のパッド1LBの配置の変形例を説明する。図26は、本実施の形態2のチップ1Cの全体平面図を示している。本実施の形態2では、チップ1Cの互いに交差(直交)する2辺の各々に沿って複数のパッド1LBが配置されている。それ以外は前記実施の形態1と同じであり、チップ1Cの外周(互いに交差(直交)する2辺)に切断領域CRの一部が残され、その切断領域CR内にテスト用のパッド1LBtが残されている。
まず、実施の形態3の説明の前に発明者が初めて見出した課題について説明する。上記のようにウエハ1Wの分割においては、切断領域CRに存在するテスト用のパッド1LBtやアライメントターゲットAm等のような金属パターンの切断部分に上記ひげ状の導体異物が生じる問題がある。この問題を回避すべく、本発明者は切断領域CRのパッド1LBtやアライメントターゲットAm等のような金属パターンにミシン目状または直線状の溝を形成するようにした。しかし、分割方式として上記エキスパンド方式を採用した場合は、上記金属パターンにミシン目状または直線状の溝を形成しても、ひげ状の導体異物の発生を上手く抑えることができないという問題がある。また、切断領域CRの隣接する金属パターンの間の絶縁膜のみの部分では切断線が蛇行し綺麗に切断できないという問題がある。
前記実施の形態1〜3では、チップ1Cの外周にテスト用のパッド1LBtやTEG用の素子が残されるので、外部にTEG情報が漏れる、という問題がある。本実施の形態4は、このような問題を回避するための手段を説明するものである。以下、本実施の形態4の半導体装置の製造方法例を図40のフロー図に沿って図41〜図50により説明する。
前記実施の形態4では、TEG情報の漏洩を防止できるが、前記実施の形態3で説明した切断線が蛇行してしまう問題がある。本実施の形態5では、その問題を回避するための手段を説明するものである。
本実施の形態6ではTEG情報の漏洩防止のためTEGをレーザ光により除去する方法例を説明する。
前記実施の形態6では、TEG情報の漏洩を防止できるが、前記実施の形態3で説明した切断線が蛇行してしまう問題がある。本実施の形態7では、その問題を回避するための手段を説明するものである。
前記実施の形態4および5では、ダイシングソー(ブレードダイシング方式)によりTEGを除去することで、TEG情報の漏洩や、TEGのひげ状の導体異物(ひげ不良)により生じる実装不良を防止できるが、半導体装置の更なる薄型化の要求に伴い、例えばウエハの厚さが70μm厚以下と薄くなった場合、図66に示すように、チップクラックの問題が発生し易い。この原因は、TEGの除去方法としてダイシングソー26を用いることと、ウエハ1Wの薄型化に伴い、破砕層(改質領域PR)からTEGまでの距離(間隔)が近く(短く)なることと、ウエハ1W(チップ1C)の抗折強度が低下することにある。ブレードダイシング方式は、高速回転するダイシングソー26をウエハ1Wに接触させることでウエハ1Wを切断(破断)するため、ステルスダイシング方式に比べウエハ1Wに加わる切断応力(破断応力)は大きい。すなわち、実施の形態4および5で説明したように、ウエハ1Wに予めレーザ光を照射して破砕層(改質領域PR)を形成した後にダイシングソー26を用いてTEGを除去すると、破砕層からTEGまでの距離(間隔)は近く、更には、ウエハ1Wの抗折強度が低下していることから、ダイシングソー26の切断応力が破砕層まで進展し易く、亀裂(クラック)CRKが発生してしまう。そこで、本実施の形態8では、その問題を回避するための手段を説明するものである。
ブレードダイシング方式により半導体ウエハを分割する場合は、使用するダイシングソーの幅よりも太い幅の切断領域が必要であった。これに対し、ステルスダイシング方式の場合、半導体ウエハの内部に破砕層(改質領域PR)を形成し、その破砕層を起点として半導体ウエハを分割するため、ブレードダイシング方式に比べ切断領域の幅は狭くすることが可能である。
半導体装置の小型化に伴い、チップのサイズもより小型化することが要求される。小型化されたチップの分割方法として、ウエハの薄型化にも対応できるステルスダイシング方式を用いた場合、1つのウエハから個々のチップに分割するためには、レーザ光をウエハに照射した後にエキスパンド工程を行うことで実現できる。
Claims (17)
- (a)厚さ方向に沿って互いに反対側になる主面および裏面を有する半導体ウエハを用意する工程と、
(b)前記半導体ウエハの主面に素子を形成する工程と、
(c)前記半導体ウエハの主面上に配線層を形成する工程と、
(d)前記半導体ウエハを薄型化する工程と、
(e)前記半導体ウエハのチップ分離領域に沿って前記半導体ウエハの内部に集光点を合わせてレーザを照射することにより、後の半導体ウエハ切断工程において前記半導体ウエハの分割起点となる改質領域を形成する工程と、
(f)前記半導体ウエハを折り曲げることにより前記改質領域を起点として前記半導体ウエハを切断して半導体チップに分割する工程とを有し、
前記(e)工程においては、前記レーザを、前記チップ分離領域の検査用のパッドの脇に照射することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記検査用のパッドを前記チップ分離領域の片側に寄せて配置することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記配線層は低誘電率膜を有することを特徴とする半導体装置の製造方法。
- 配線基板と、その配線基板上に実装された半導体チップとを備え、前記半導体チップは、その外周に検査用のパッドが配置された領域を有することを特徴とする半導体装置。
- 請求項4記載の半導体装置において、前記半導体チップを複数積層した構成を有することを特徴とする半導体装置。
- 請求項4記載の半導体装置の製造方法において、前記半導体チップの主面の配線層は低誘電率膜を有することを特徴とする半導体装置。
- (a)厚さ方向に沿って互いに反対側になる主面および裏面を有する半導体ウエハを用意する工程と、
(b)前記半導体ウエハの主面に素子を形成する工程と、
(c)前記半導体ウエハの主面上に配線層を形成する工程と、
(d)前記半導体ウエハを薄型化する工程と、
(e)前記半導体ウエハのチップ分離領域に沿って前記半導体ウエハの内部に集光点を合わせてレーザを照射することにより、後の半導体ウエハ切断工程において前記半導体ウエハの分割起点となる改質領域を形成する工程と、
(f)前記半導体ウエハを折り曲げることにより前記改質領域を起点として前記半導体ウエハを切断して半導体チップに分割する工程とを有し、
前記(f)工程の前に、前記チップ分離領域に配置された検査用のパッドに、前記(f)工程において前記検査用のパッドの分割起点となる溝または孔を形成する工程を有することを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、前記検査用のパッドの隣接間に金属パターンを形成し、前記検査用のパッドに前記溝または孔を形成する工程において、前記金属パターンにも溝または孔を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、前記配線層は低誘電率膜を有することを特徴とする半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、前記金属パターンの切断線に交差する方向の長さは、前記検査用のパッドの前記切断線に交差する方向の長さよりも短いことを特徴とする半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、前記溝または孔をレーザにより形成することを特徴とする半導体装置の製造方法。
- (a)厚さ方向に沿って互いに反対側になる主面および裏面を有する半導体ウエハを用意する工程と、
(b)前記半導体ウエハの主面に素子を形成する工程と、
(c)前記半導体ウエハの主面上に配線層を形成する工程と、
(d)前記半導体ウエハを薄型化する工程と、
(e)前記半導体ウエハのチップ分離領域に沿って前記半導体ウエハの内部に集光点を合わせて第1レーザを照射することにより、後の半導体ウエハ切断工程において前記半導体ウエハの分割起点となる改質領域を形成する工程と、
(f)前記半導体ウエハのチップ分離領域に配置された検査用のパッドを除去する工程と、
(g)前記半導体ウエハを前記改質領域を起点として切断して半導体チップに分割する工程とを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法の前記(g)工程において、前記半導体ウエハを折り曲げることにより前記半導体ウエハを前記改質領域を起点として切断して半導体チップに分割することを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法の前記(f)工程において、前記検査用のパッドをブレードダイシング方式により除去することを特徴とする半導体装置の製造方法。
- 請求項14記載の半導体装置の製造方法において、前記ブレードダイシング方式により前記チップ分割領域の前記配線層の上面に溝を形成することを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法の前記(f)工程において、前記検査用のパッドに前記(e)工程時の第1レーザよりも短波長の第2レーザを照射することにより、前記検査用のパッドを溶融し除去することを特徴とする半導体装置の製造方法。
- 請求項16記載の半導体装置の製造方法において、
前記(f)工程においては、前記第2レーザの照射により前記チップ分離領域の前記配線層の上面に溝または孔を形成し、
前記(g)工程においては、前記半導体ウエハを折り曲げることにより、前記半導体ウエハを前記改質領域および前記溝または孔を起点として切断することを特徴とする半導体装置の製造方法。
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US9070560B2 (en) | 2015-06-30 |
US20180277456A1 (en) | 2018-09-27 |
US20110124180A1 (en) | 2011-05-26 |
US8084334B2 (en) | 2011-12-27 |
US10002808B2 (en) | 2018-06-19 |
CN101297394A (zh) | 2008-10-29 |
CN101930943B (zh) | 2012-08-29 |
CN101930943A (zh) | 2010-12-29 |
US7892949B2 (en) | 2011-02-22 |
US8772135B2 (en) | 2014-07-08 |
CN101297394B (zh) | 2010-10-13 |
US20140252643A1 (en) | 2014-09-11 |
US20150235973A1 (en) | 2015-08-20 |
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