JP6815692B2 - ウェーハの加工方法 - Google Patents
ウェーハの加工方法 Download PDFInfo
- Publication number
- JP6815692B2 JP6815692B2 JP2016239559A JP2016239559A JP6815692B2 JP 6815692 B2 JP6815692 B2 JP 6815692B2 JP 2016239559 A JP2016239559 A JP 2016239559A JP 2016239559 A JP2016239559 A JP 2016239559A JP 6815692 B2 JP6815692 B2 JP 6815692B2
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- Prior art keywords
- wafer
- division line
- planned division
- teg
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000003672 processing method Methods 0.000 title claims description 15
- 239000010410 layer Substances 0.000 claims description 71
- 238000012545 processing Methods 0.000 claims description 64
- 239000002346 layers by function Substances 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 6
- 238000000638 solvent extraction Methods 0.000 claims description 5
- 238000012986 modification Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims description 2
- 238000003754 machining Methods 0.000 description 27
- 239000000463 material Substances 0.000 description 13
- 238000002679 ablation Methods 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000003028 elevating effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Plasma & Fusion (AREA)
- Optics & Photonics (AREA)
- Dicing (AREA)
- Laser Beam Processing (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Processing Of Stones Or Stones Resemblance Materials (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
1a 表面
1b 裏面
3 分割予定ライン
5 デバイス
5a 機能層
7 TEG
9,23 フレーム
11 テープ
13 加工溝
15 表面保護テープ
17 改質層
19 クラック
21 ダイシングテープ
25 デバイスチップ
2,8 レーザ加工装置
4,10,22 チャックテーブル
4a,10a,22a 保持面
6,12 加工ヘッド
14 研削装置
16 スピンドル
18 研削砥石
20 研削ホイール
24 拡張装置
26 拡張ドラム
28 支持部材
Claims (2)
- 機能層と、該機能層を含む複数のデバイスと、該デバイスを区画する分割予定ラインと、該分割予定ラインと重なる金属を含むTEGと、を表面に有するウェーハを該分割予定ラインに沿って分割するウェーハの加工方法であって、
該機能層に吸収される波長のレーザビームを、ウェーハの該表面側から該分割予定ラインに沿って照射し、該機能層を分断する加工溝を形成する加工溝形成ステップと、
該ウェーハに対して透過性を有する波長のレーザビームを、該ウェーハの裏面側から該分割予定ラインに沿って照射し、該ウェーハの内部に該分割予定ラインに沿う改質層を形成する改質層形成ステップと、
該加工溝及び該改質層が形成されたウェーハに外力を付与し、該改質層を起点にウェーハを該分割予定ラインに沿って分割する分割ステップと、を備え、
該加工溝形成ステップでは、該分割予定ラインの該TEGが形成されていない領域にのみ該レーザビームを照射し、該TEGの前後に分かれた該加工溝を形成することを特徴とするウェーハの加工方法。 - 該分割ステップは、該ウェーハを裏面側から研削して仕上がり厚さまで薄化する研削ステップを含み、
該研削ステップでは、該TEGの形成箇所において該改質層から該ウェーハの該表面にクラックを伸長させて該TEGを分断することを特徴とする請求項1に記載のウェーハの加工方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016239559A JP6815692B2 (ja) | 2016-12-09 | 2016-12-09 | ウェーハの加工方法 |
KR1020170167305A KR102349663B1 (ko) | 2016-12-09 | 2017-12-07 | 웨이퍼의 가공 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016239559A JP6815692B2 (ja) | 2016-12-09 | 2016-12-09 | ウェーハの加工方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018098296A JP2018098296A (ja) | 2018-06-21 |
JP6815692B2 true JP6815692B2 (ja) | 2021-01-20 |
Family
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Family Applications (1)
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---|---|---|---|
JP2016239559A Active JP6815692B2 (ja) | 2016-12-09 | 2016-12-09 | ウェーハの加工方法 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP6815692B2 (ja) |
KR (1) | KR102349663B1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200059888A (ko) * | 2018-11-22 | 2020-05-29 | 삼성전자주식회사 | 반도체 장치, 반도체 칩 및 반도체 기판의 반도체 기판의 소잉 방법 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7154860B2 (ja) * | 2018-07-31 | 2022-10-18 | 株式会社ディスコ | ウエーハの加工方法 |
JP7307534B2 (ja) * | 2018-10-04 | 2023-07-12 | 浜松ホトニクス株式会社 | レーザ加工方法、半導体デバイス製造方法及び検査装置 |
JP7307533B2 (ja) * | 2018-10-04 | 2023-07-12 | 浜松ホトニクス株式会社 | レーザ加工方法、半導体デバイス製造方法及び検査装置 |
JP7171353B2 (ja) * | 2018-10-04 | 2022-11-15 | 浜松ホトニクス株式会社 | レーザ加工方法、半導体デバイス製造方法及び検査装置 |
JP2020077782A (ja) * | 2018-11-08 | 2020-05-21 | 株式会社ディスコ | ウエーハの加工方法 |
JP7313253B2 (ja) * | 2019-10-10 | 2023-07-24 | 株式会社ディスコ | ウエーハの加工方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4377300B2 (ja) * | 2004-06-22 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体ウエハおよび半導体装置の製造方法 |
JP2006318966A (ja) * | 2005-05-10 | 2006-11-24 | Disco Abrasive Syst Ltd | 半導体ウエーハ |
JP2006344795A (ja) * | 2005-06-09 | 2006-12-21 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
JP2007012878A (ja) * | 2005-06-30 | 2007-01-18 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
WO2007055010A1 (ja) * | 2005-11-10 | 2007-05-18 | Renesas Technology Corp. | 半導体装置の製造方法および半導体装置 |
JP2007173475A (ja) | 2005-12-21 | 2007-07-05 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
JP2009032726A (ja) * | 2007-07-24 | 2009-02-12 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
JP2011187479A (ja) * | 2010-03-04 | 2011-09-22 | Disco Corp | ウエーハの加工方法 |
JP5608521B2 (ja) * | 2010-11-26 | 2014-10-15 | 新光電気工業株式会社 | 半導体ウエハの分割方法と半導体チップ及び半導体装置 |
US8952497B2 (en) * | 2012-09-14 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scribe lines in wafers |
JP2015106693A (ja) * | 2013-12-02 | 2015-06-08 | 旭化成エレクトロニクス株式会社 | 半導体ウェハ及び半導体装置の製造方法 |
JP5906265B2 (ja) * | 2014-03-03 | 2016-04-20 | 株式会社ディスコ | ウエーハの分割方法 |
-
2016
- 2016-12-09 JP JP2016239559A patent/JP6815692B2/ja active Active
-
2017
- 2017-12-07 KR KR1020170167305A patent/KR102349663B1/ko active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200059888A (ko) * | 2018-11-22 | 2020-05-29 | 삼성전자주식회사 | 반도체 장치, 반도체 칩 및 반도체 기판의 반도체 기판의 소잉 방법 |
KR102653165B1 (ko) | 2018-11-22 | 2024-04-01 | 삼성전자주식회사 | 반도체 장치, 반도체 칩 및 반도체 기판의 반도체 기판의 소잉 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20180066864A (ko) | 2018-06-19 |
JP2018098296A (ja) | 2018-06-21 |
KR102349663B1 (ko) | 2022-01-11 |
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