JP2022024547A - 半導体装置の製造方法、半導体パッケージ及び半導体パッケージの製造方法 - Google Patents
半導体装置の製造方法、半導体パッケージ及び半導体パッケージの製造方法 Download PDFInfo
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- JP2022024547A JP2022024547A JP2020127200A JP2020127200A JP2022024547A JP 2022024547 A JP2022024547 A JP 2022024547A JP 2020127200 A JP2020127200 A JP 2020127200A JP 2020127200 A JP2020127200 A JP 2020127200A JP 2022024547 A JP2022024547 A JP 2022024547A
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Abstract
【解決手段】半導体装置の製造方法において、スクライブ領域4Xは、第1の方向に延在する第1の領域10と、第1の領域の、平面視で第1の方向に直交する第2の方向の両側に位置し、第1の方向に延在する第2の領域20と、第2の領域に設けられたモニタパッド5と、を有する。半導体装置の製造方法は、複数の半導体チップに個片化する工程の前に、第2の領域にレーザ光を照射してモニタパッド5の少なくとも一部を除去する工程を有する。複数の半導体チップに個片化する工程において、第1の領域にて半導体ウェハを切断する。
【選択図】図4
Description
まず、第1の実施形態について説明する。第1の実施形態は半導体装置の製造方法に関する。図1は、第1の実施形態で用いられる半導体ウェハを示す図である。
図2~図5は、第1の実施形態に係る半導体装置の製造方法を示す模式図である。
図6~図9は、第1の実施形態に係る半導体装置の製造方法を示す断面図である。
図2~図5は、図1中の一部の領域2を拡大して示す図である。
図6~図9は、それぞれ図2~図5中のVI-VI線~IX-IX線に沿った断面図に相当する。
次に、第2の実施形態について説明する。第2の実施形態は、主に、スクライブ領域4Xの処理の点で第1の実施形態と相違する。図12~図13は、第2の実施形態に係る半導体装置の製造方法を示す模式図である。図14~図15は、第2の実施形態に係る半導体装置の製造方法を示す断面図である。図12~図13は、図1中の一部の領域2を拡大して示す図である。図14~図15は、それぞれ図12~図13中のXIV-XIV線~XV-XV線に沿った断面図に相当する。
次に、第3の実施形態について説明する。第3の実施形態は、主に、スクライブ領域4X及び4Yの処理の点で第1の実施形態等と相違する。図16は、第3の実施形態に係る半導体装置の製造方法を示す模式図である。図17は、第3の実施形態に係る半導体装置の製造方法を示す断面図である。図16は、図1中の一部の領域2を拡大して示す図である。図17は、図16中のXVI-XVI線に沿った断面図に相当する。
次に、第4の実施形態について説明する。第4の実施形態は、主に、スクライブ領域4Xの処理の点で第1の実施形態等と相違する。図18は、第4の実施形態に係る半導体装置の製造方法を示す断面図である。
次に、第5の実施形態について説明する。第5の実施形態は、主に、スクライブ領域4X及び4Yの処理の点で第1の実施形態等と相違する。図19は、第5の実施形態に係る半導体装置の製造方法を示す断面図である。
次に、第6の実施形態について説明する。第6の実施形態は、主に、スクライブ領域4X及び4Yの処理の点で第2の実施形態等と相違する。図20は、第6の実施形態に係る半導体装置の製造方法を示す断面図である。
次に、第7の実施形態について説明する。第7の実施形態は、主に、スクライブ領域4X及び4Yの処理の点で第3の実施形態等と相違する。図21は、第7の実施形態に係る半導体装置の製造方法を示す断面図である。
3:回路領域
4X、4Y:スクライブ領域
5:モニタパッド
100、200、300、400、500、600、700:半導体装置
10、20、30:領域
31、32、33、34:溝
60:半導体パッケージ
62:配線基板
65:アンダーフィル
Claims (7)
- 複数の回路領域と、前記複数の回路領域の間に設けられ、平面視で第1の方向に延在し、モニタパッドを備えたスクライブ領域と、を備えた半導体ウェハの前記スクライブ領域にて前記半導体ウェハを切断して、それぞれが前記回路領域を備えた複数の半導体チップに個片化する工程を有し、
前記スクライブ領域は、
前記第1の方向に延在する第1の領域と、
前記第1の領域の、平面視で前記第1の方向に直交する第2の方向の両側に位置し、前記第1の方向に延在する第2の領域と、
前記第2の領域に設けられたモニタパッドと、
を有し、
前記複数の半導体チップに個片化する工程の前に、前記第2の領域にレーザ光を照射して前記モニタパッドの少なくとも一部を除去する工程を有し、
前記複数の半導体チップに個片化する工程において、前記第1の領域にて前記半導体ウェハを切断することを特徴とする半導体装置の製造方法。 - 前記スクライブ領域はモニタパターンを有する請求項1に記載の半導体装置の製造方法。
- 前記スクライブ領域は、
基板と、
前記基板と前記モニタパッドとの間に設けられた配線層と、
を有し、
前記モニタパッドを除去する工程は、
前記モニタパッド及び前記配線層に、前記基板に到達する溝を形成する工程を有することを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記溝を前記基板に入り込むように形成することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記半導体チップは、前記第2の領域を含むことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 請求項1乃至5のいずれか1項に記載の方法で半導体装置を製造する工程と、
前記半導体装置を配線基板にフリップチップ実装する工程と、
前記半導体装置と前記配線基板との間にアンダーフィルを充填する工程と、
を有することを特徴とする半導体パッケージの製造方法。 - 回路領域と、
前記回路領域の側方に設けられ、平面視で第1の方向に延在するスクライブ領域と、
を有し、
前記スクライブ領域は、
基板と、
前記基板の上に形成された配線層と、
前記配線層の上に形成されたモニタパッドと、
前記モニタパッド及び前記配線層に形成され、前記基板に到達する溝と、
前記溝内に設けられたアンダーフィルと、
を有することを特徴とする半導体パッケージ。
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