JP2007048958A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP2007048958A JP2007048958A JP2005231946A JP2005231946A JP2007048958A JP 2007048958 A JP2007048958 A JP 2007048958A JP 2005231946 A JP2005231946 A JP 2005231946A JP 2005231946 A JP2005231946 A JP 2005231946A JP 2007048958 A JP2007048958 A JP 2007048958A
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Abstract
【解決手段】 半導体ウエハ1Wの半導体基板1Sの内部に集光点を合わせた状態でレーザ光を照射することにより改質領域PLを形成する。続いて、半導体ウエハ1Wの裏面に回転塗布法により液状の接着材を塗布した後、これを乾燥させて固体状の接着層8aを形成する。その後、上記改質領域PLを分割起点として半導体ウエハ1Wを個々の半導体チップに分割する。この半導体チップをその裏面の接着層8aにより他の半導体チップの主面上に接着することにより、半導体チップが多段に積層された構成を有する半導体装置を製造する。
【選択図】 図13
Description
本実施の形態1の半導体装置の製造方法を図1のフロー図に沿って説明する。
本実施の形態2では、前記実施の形態1と同様に、図1の前工程100からレーザ照射工程102B1を経た後、チップ分割工程102Bの接着層形成工程102B2において、ウエハの裏面に印刷法により接着層を形成する。
前記実施の形態1,2では、チップ分割工程において、改質領域LBを形成するためのレーザ照射工程後に、ウエハ1Wの裏面に接着層を形成する場合について説明した。本実施の形態3では、チップ分割工程において、ウエハ1Wの裏面に接着層を形成した後、、改質領域LBを形成するためのレーザ照射工程を行う場合について説明する。
本実施の形態4では、前記実施の形態3と同様に、図36の前工程200から裏面研磨工程202A3を経た後、チップ分割工程202Bの接着層形成工程202B1において、ウエハ1Wの裏面に印刷法により接着層を形成する。
本実施の形態5では、ウエハの裏面に印刷法により接着層を形成する場合の変形例について説明する。
図55は本実施の形態6の半導体装置の断面図を示している。本実施の形態6では、下層のチップ18Cが、その主面(デバイス形成面)を配線基板17の主面に向けた状態で、バンプ電極30を介して配線基板17の主面上に実装されている。チップ18Cの集積回路は、バンプ電極30を通じて配線基板17の主面上の電極に電気的に接続され、さらに配線基板17の配線に電気的に接続されている。バンプ電極30は、例えば鉛(Pb)−錫(Sn)半田により形成されている。チップ18Cと配線基板17との対向面間にはアンダーフィル31が充填されている。
図56は本実施の形態7の半導体装置の断面図を示している。本実施の形態7では、チップ1C1(1C)の主面上に、他のチップ1C2(1C)がその主面を上に向けた状態で実装されている。最上層のチップ1C2の裏面は接着層8aを介してチップ1C1の主面に接着されている。チップ1C2の主面の集積回路はワイヤ21を介して配線基板17の電極17aに電気的に接続されている。チップ1C1,1C2の裏面の接着層8aは薄く形成されているので、チップ18C,1C1,1C2の多段構成を有する半導体装置を薄型にすることができる。また、最上層のチップ1C2の裏面の接着層8aの厚さは、中間層のチップ1C1の裏面の接着層8aの厚さと等しい。各チップ1C1,1C2の裏面の接着層8aの厚さを等しくすることにより、各チップ1C1,1C2の裏面の接着層8aの厚さ設計を容易にすることができる。
図57は本実施の形態8の半導体装置の断面図を示している。本実施の形態8の半導体装置は、1つのパッケージ内に所望の機能のシステムが構築されたSIP(System In Package)とされている。配線基板17の主面上には、複数の薄型のチップ18,1C,37Cが積層されている。最下層のチップ18Cは、その主面のバンプ電極30を介して配線基板17の主面上に実装されている。このチップ18Cの主面には、例えばCPU(Central Processing Unit)やDSP(Digital Signal Processor)等のような論理回路が形成されている。このチップ18Cの裏面上には、接着層8aを介してチップ1Cが実装されている。このチップ1Cの主面には、例えばSRAM(Static Random Access Memory)やフラッシュメモリ等のようなメモリ回路が形成されている。このチップ1Cの主面のパッド1LBは、ワイヤ21を介して配線基板17の主面の電極17aと電気的に接続されている。このチップ1Cの主面上には、スペーサ35およびDAF36を介してチップ37Cが実装されている。このチップ37Cには、例えばSRAMやフラッシュメモリ等のようなメモリ回路が形成されており、チップ37Cの主面のパッドは、ワイヤ21を介して配線基板17の主面の電極17aと電気的に接続されている。このようなチップ18C,1C,37Cおよびワイヤ21は封止体22により封止されている。
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
1C 半導体チップ(第2チップ)
1S 半導体基板
1L 配線層
1Li,1Li1,1Li2,1Li3 層間絶縁膜
1LB ボンディングパッド
1LBt テスト用のボンディングパッド
1Lp 表面保護膜
2 開口部
3 接着層
4 支持基板
4a 剥離層
5 レーザ発生部
7 ノズル
8 接着材
8a,8b,8c 接着層
10 治具
10a テープ
10b リング
11 レーザ発生部
12 載置台
15 載置台
17 配線基板
17a,17b 電極
18C 半導体チップ(第1チップ)
18S 半導体基板
18L 配線層
18LB ボンディングパッド
20a 接着層
21 ボンディングワイヤ
22 封止体
23 はんだボール
25A,25B マスク
25A1,25B1 開口部
25A2,25B2 マスクパターン
26 スキージ
30 バンプ電極
31 アンダーフィル
35 スペーサ
36 DAF
37C 半導体チップ
CR 切断領域
CL 切断線
Am アライメントターゲット
LB1 レーザ光
LB2 レーザ光
PL 改質領域
Claims (15)
- 以下の工程を有することを特徴とする半導体装置の製造方法:
(a)厚さ方向に沿って互いに反対側になる主面および裏面を有する配線基板を用意する工程と、
(b)前記配線基板の主面上に第1チップを搭載する工程と、
(c)前記第1チップ上に第2チップを積み重ね、前記第2チップをその裏面の固体状の接着層により前記第1チップに接着する工程とを有し、
前記第2チップの作成工程は、
厚さ方向に沿って互いに反対側になる主面および裏面を有するウエハを用意する工程と、
前記ウエハの主面に素子を形成する工程と、
前記ウエハの主面上に配線層を形成する工程と、
前記ウエハを薄型化する工程、
前記ウエハのチップ分離領域に沿って前記ウエハの内部に集光点を合わせてレーザを照射することにより、後のウエハ切断工程において前記ウエハの分割起点となる改質領域を形成する工程と、
前記ウエハの裏面に液状の接着材を回転塗布法により塗布し、前記ウエハの裏面に前記固体状の接着層を形成する工程と、
前記改質領域を起点として前記ウエハを切断し、前記固体状の接着層を裏面に持つ前記第2チップを得る工程とを有することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記配線層は低誘電率膜を有することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記第1チップの搭載工程は、前記第1チップをフィルム状の接着部材により前記配線基板に接着する工程を有することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記第1チップの搭載工程は、前記第1チップをペースト状の接着材により前記配線基板に接着する工程と、前記ペースト状の接着材を乾燥させて固体状にする工程とを有することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記第1チップと前記第2チップとを接着する前記固体状の接着層の厚さは、前記第1チップと前記配線基板とを接着する接着層の厚さよりも薄いことを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記配線基板の主面に多段に積み重ねられたチップ間の接着層の厚さは互いに等しいことを特徴とする半導体装置の製造方法。
- 以下の工程を有することを特徴とする半導体装置の製造方法:
(a)厚さ方向に沿って互いに反対側になる主面および裏面を有する配線基板を用意する工程と、
(b)前記配線基板の主面上に第1チップを搭載する工程と、
(c)前記第1チップ上に第2チップを積み重ね、前記第2チップをその裏面の固体状の接着層により前記第1チップに接着する工程とを有し、
前記第2チップの作成工程は、
厚さ方向に沿って互いに反対側になる主面および裏面を有するウエハを用意する工程と、
前記ウエハの主面に素子を形成する工程と、
前記ウエハの主面上に配線層を形成する工程と、
前記ウエハを薄型化する工程と、
前記ウエハのチップ分離領域に沿って前記ウエハの内部に集光点を合わせてレーザを照射することにより、後のウエハ切断工程において前記ウエハの分割起点となる改質領域を形成する工程と、
前記ウエハの裏面に液状の接着材を印刷法により塗布し、前記ウエハの裏面に前記固体状の接着層を形成する工程と、
前記改質領域を起点として前記ウエハを切断し、前記固体状の接着層を裏面に持つ前記第2チップを得る工程とを有することを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、前記配線層は低誘電率膜を有することを特徴とする半導体装置の製造方法。
- 請求項7記載の半導体装置の製造方法において、前記第1チップの搭載工程は、前記第1チップをフィルム状の接着部材により前記配線基板に接着する工程を有することを特徴とする半導体装置の製造方法。
- 請求項7記載の半導体装置の製造方法において、前記第1チップの搭載工程は、前記第1チップをペースト状の接着材により前記配線基板に接着する工程と、前記ペースト状の接着材を乾燥させて固体状にする工程とを有することを特徴とする半導体装置の製造方法。
- 請求項7記載の半導体装置の製造方法において、前記第1チップと前記第2チップとを接着する前記固体状の接着層の厚さは、前記第1チップと前記配線基板とを接着する接着層の厚さよりも薄いことを特徴とする半導体装置の製造方法。
- 請求項7記載の半導体装置の製造方法において、2段目以降の多段に積み重ねられたチップ間の接着層の厚さは互いに等しいことを特徴とする半導体装置の製造方法。
- 請求項7記載の半導体装置の製造方法において、前記ウエハの裏面に液状の接着材を印刷法により塗布する際に、前記液状の接着材が前記ウエハの裏面のチップ領域に塗布され、チップ分離領域には塗布されないように、前記液状の接着材を選択的に塗布することを特徴とする半導体装置の製造方法。
- 厚さ方向に沿って互いに反対側になる主面および裏面を有する配線基板と、
前記配線基板の主面上に固体状の第1接着層を介して搭載された第1チップと、
前記第1チップ上に固体状の第2接着層を介して搭載された第2チップとを備え、
前記第2接着層の厚さは、前記第1接着層の厚さよりも薄いことを特徴とする半導体装置。 - 厚さ方向に沿って互いに反対側になる主面および裏面を有する配線基板と、
前記配線基板の主面上に接着層を介して搭載されたチップと、
前記チップ上に、多段に積み重ねられた複数のチップとを備え、
前記配線基板の主面上に多段に積み重ねられたチップ間の接着層の厚さは互いに等しいことを特徴とする半導体装置。
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Also Published As
Publication number | Publication date |
---|---|
US20130143359A1 (en) | 2013-06-06 |
US7514294B2 (en) | 2009-04-07 |
US20070037321A1 (en) | 2007-02-15 |
US20100213594A1 (en) | 2010-08-26 |
CN1913113A (zh) | 2007-02-14 |
CN100568473C (zh) | 2009-12-09 |
US20090191667A1 (en) | 2009-07-30 |
TW200707565A (en) | 2007-02-16 |
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